1 /*
2 ** ###################################################################
3 ** Processors: LPC54114J256BD64_cm0plus
4 ** LPC54114J256UK49_cm0plus
5 **
6 ** Compilers: Keil ARM C/C++ Compiler
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
12 ** Version: rev. 1.0, 2016-04-29
13 ** Build: b180802
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2018 NXP
22 **
23 ** SPDX-License-Identifier: BSD-3-Clause
24 **
25 ** http: www.nxp.com
26 ** mail: support@nxp.com
27 **
28 ** Revisions:
29 ** - rev. 1.0 (2016-04-29)
30 ** Initial version.
31 **
32 ** ###################################################################
33 */
34
35 /*!
36 * @file LPC54114_cm0plus
37 * @version 1.0
38 * @date 2016-04-29
39 * @brief Device specific configuration file for LPC54114_cm0plus
40 * (implementation file)
41 *
42 * Provides a system configuration function and a global variable that contains
43 * the system frequency. It configures the device and initializes the oscillator
44 * (PLL) that is part of the microcontroller device.
45 */
46
47 #include <stdint.h>
48 #include "fsl_device_registers.h"
49
50 #define NVALMAX (0x100U)
51 #define PVALMAX (0x20U)
52 #define MVALMAX (0x8000U)
53 #define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */
54 #define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */
55 #define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
56 #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
57 #define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
58 #define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
59
60 /* ----------------------------------------------------------------------------
61 -- Core clock
62 ---------------------------------------------------------------------------- */
63
64 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
65
66 static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
67 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
68
GetWdtOscFreq(void)69 static uint32_t GetWdtOscFreq(void)
70 {
71 uint8_t freq_sel;
72 uint32_t div_sel;
73 div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1U) << 1U;
74 freq_sel =
75 wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
76 return ((uint32_t)freq_sel * 50000U) / div_sel;
77 }
78
79 /* Find decoded N value for raw NDEC value */
pllDecodeN(uint32_t NDEC)80 static uint32_t pllDecodeN(uint32_t NDEC)
81 {
82 uint32_t n, x, i;
83
84 /* Find NDec */
85 switch (NDEC)
86 {
87 case 0xFFFU:
88 n = 0U;
89 break;
90 case 0x302U:
91 n = 1U;
92 break;
93 case 0x202U:
94 n = 2U;
95 break;
96 default:
97 x = 0x080U;
98 n = 0xFFFFFFFFU;
99 for (i = NVALMAX; i >= 3U; i--)
100 {
101 x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
102 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
103 {
104 /* Decoded value of NDEC */
105 n = i;
106 }
107 }
108 break;
109 }
110 return n;
111 }
112
113 /* Find decoded P value for raw PDEC value */
pllDecodeP(uint32_t PDEC)114 static uint32_t pllDecodeP(uint32_t PDEC)
115 {
116 uint32_t p, x, i;
117 /* Find PDec */
118 switch (PDEC)
119 {
120 case 0xFFU:
121 p = 0U;
122 break;
123 case 0x62U:
124 p = 1U;
125 break;
126 case 0x42U:
127 p = 2U;
128 break;
129 default:
130 x = 0x10U;
131 p = 0xFFFFFFFFU;
132 for (i = PVALMAX; i >= 3U; i--)
133 {
134 x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
135 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
136 {
137 /* Decoded value of PDEC */
138 p = i;
139 }
140 }
141 break;
142 }
143 return p;
144 }
145
146 /* Find decoded M value for raw MDEC value */
pllDecodeM(uint32_t MDEC)147 static uint32_t pllDecodeM(uint32_t MDEC)
148 {
149 uint32_t m, i, x;
150
151 /* Find MDec */
152 switch (MDEC)
153 {
154 case 0xFFFFFU:
155 m = 0U;
156 break;
157 case 0x18003U:
158 m = 1U;
159 break;
160 case 0x10003U:
161 m = 2U;
162 break;
163 default:
164 x = 0x04000U;
165 m = 0xFFFFFFFFU;
166 for (i = MVALMAX; i >= 3U; i--)
167 {
168 x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
169 if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
170 {
171 /* Decoded value of MDEC */
172 m = i;
173 }
174 }
175 break;
176 }
177 return m;
178 }
179
180 /* Get predivider (N) from PLL NDEC setting */
findPllPreDiv(uint32_t ctrlReg,uint32_t nDecReg)181 static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
182 {
183 uint32_t preDiv = 1U;
184
185 /* Direct input is not used? */
186 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U)
187 {
188 /* Decode NDEC value to get (N) pre divider */
189 preDiv = pllDecodeN(nDecReg & 0x3FFU);
190 if (preDiv == 0U)
191 {
192 preDiv = 1U;
193 }
194 }
195 /* Adjusted by 1, directi is used to bypass */
196 return preDiv;
197 }
198
199 /* Get postdivider (P) from PLL PDEC setting */
findPllPostDiv(uint32_t ctrlReg,uint32_t pDecReg)200 static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
201 {
202 uint32_t postDiv = 1U;
203
204 /* Direct input is not used? */
205 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
206 {
207 /* Decode PDEC value to get (P) post divider */
208 postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
209 if (postDiv == 0U)
210 {
211 postDiv = 2U;
212 }
213 }
214 /* Adjusted by 1, directo is used to bypass */
215 return postDiv;
216 }
217
218 /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
findPllMMult(uint32_t ctrlReg,uint32_t mDecReg)219 static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
220 {
221 uint32_t mMult = 1U;
222
223 /* Decode MDEC value to get (M) multiplier */
224 mMult = pllDecodeM(mDecReg & 0x1FFFFU);
225 /* Extra multiply by 2 needed? */
226 if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0U)
227 {
228 mMult = mMult << 1U;
229 }
230 if (mMult == 0U)
231 {
232 mMult = 1U;
233 }
234 return mMult;
235 }
236
237 /* ----------------------------------------------------------------------------
238 -- SystemInit()
239 ---------------------------------------------------------------------------- */
240
SystemInit(void)241 void SystemInit(void)
242 {
243 extern void *__Vectors;
244 SCB->VTOR = (uint32_t)&__Vectors;
245 SystemInitHook();
246 }
247
248 /* ----------------------------------------------------------------------------
249 -- SystemCoreClockUpdate()
250 ---------------------------------------------------------------------------- */
251
SystemCoreClockUpdate(void)252 void SystemCoreClockUpdate(void)
253 {
254 uint32_t clkRate = 0U;
255 uint32_t prediv, postdiv;
256 uint32_t bypassccodiv2;
257 uint64_t workRate;
258
259 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
260 {
261 case 0x00U: /* MAINCLKSELA clock (main_clk_a)*/
262 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
263 {
264 case 0x00U: /* FRO 12 MHz (fro_12m) */
265 clkRate = CLK_FRO_12MHZ;
266 break;
267 case 0x01U: /* CLKIN (clk_in) */
268 clkRate = CLK_CLK_IN;
269 break;
270 case 0x02U: /* Watchdog oscillator (wdt_clk) */
271 clkRate = GetWdtOscFreq();
272 break;
273 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
274 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
275 {
276 clkRate = CLK_FRO_96MHZ;
277 }
278 else
279 {
280 clkRate = CLK_FRO_48MHZ;
281 }
282 break;
283 }
284 break;
285 case 0x02U: /* System PLL clock (pll_clk)*/
286 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
287 {
288 case 0x00U: /* FRO 12 MHz (fro_12m) */
289 clkRate = CLK_FRO_12MHZ;
290 break;
291 case 0x01U: /* CLKIN (clk_in) */
292 clkRate = CLK_CLK_IN;
293 break;
294 case 0x02U: /* Watchdog oscillator (wdt_clk) */
295 clkRate = GetWdtOscFreq();
296 break;
297 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
298 clkRate = CLK_RTC_32K_CLK;
299 break;
300 default:
301 clkRate = 0U;
302 break;
303 }
304 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
305 {
306 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
307 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
308 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
309 /* Adjust input clock */
310 clkRate = clkRate / prediv;
311 /* If using the SS, use the multiplier */
312 if ((SYSCON->SYSPLLSSCTRL0 & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) == SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK)
313 {
314 /* MDEC used for rate */
315 workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0);
316 }
317 else
318 {
319 /* SS multipler used for rate */
320 workRate = 0UL;
321 /* Adjust by fractional */
322 bypassccodiv2 = (uint32_t)((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) >>
323 SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT);
324 workRate = (2UL - bypassccodiv2) * (uint64_t)(clkRate) *
325 ((SYSCON->SYSPLLSSCTRL1 & 0x7FFFFUL) >> 11UL);
326 }
327 clkRate = (uint32_t)workRate / postdiv;
328 }
329 break;
330 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
331 clkRate = CLK_RTC_32K_CLK;
332 break;
333 default:
334 clkRate = 0U;
335 break;
336 }
337 SystemCoreClock = (uint32_t)(clkRate / ((uint64_t)(SYSCON->AHBCLKDIV & 0xFFUL) + 1UL));
338 }
339
340 /* ----------------------------------------------------------------------------
341 -- SystemInitHook()
342 ---------------------------------------------------------------------------- */
343
SystemInitHook(void)344 __attribute__((weak)) void SystemInitHook(void)
345 {
346 /* Void implementation of the weak function. */
347 }
348
