1 2 /* 3 * Copyright (c) 2021 ARM Limited 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 19 /** 20 * \file syscounter_armv8-m_cntrl_reg_map.h 21 * \brief Armv8-M System Counter Control, covering CNTControlBase Frame 22 */ 23 24 #ifndef __SYSCOUNTER_ARMV8_M_CNTRL_REG_MAP_H__ 25 #define __SYSCOUNTER_ARMV8_M_CNTRL_REG_MAP_H__ 26 27 #include <stdint.h> 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /** 34 * \brief CNTControlBase Register map structure 35 */ 36 struct cnt_control_base_reg_map_t { 37 volatile uint32_t cntcr; 38 /*!< Offset: 0x000 (R/W) Counter Control Register */ 39 volatile const uint32_t cntsr; 40 /*!< Offset: 0x004 (RO) Counter Status Register */ 41 volatile uint32_t cntcv_low; 42 /*!< Offset: 0x008 (R/W) Counter Count Value [31:0] Register */ 43 volatile uint32_t cntcv_high; 44 /*!< Offset: 0x00C (R/W) Counter Count Value [63:32] Register */ 45 volatile uint32_t cntscr; 46 /*!< Offset: 0x010 (R/W) Counter Scale Register 47 * Aliased with CNTSCR0, meaning that either addresses of CNTSCR and 48 * CNTSCR0 will physically access a single register 49 */ 50 volatile const uint32_t reserved0[2]; 51 /*!< Offset: 0x014-0x018 Reserved (RAZWI) */ 52 volatile const uint32_t cntid; 53 /*!< Offset: 0x01C (RO) Counter ID Register */ 54 volatile const uint32_t reserved1[40]; 55 /*!< Offset: 0x020-0x0BC Reserved (RAZWI) */ 56 volatile const uint32_t reserved2[4]; 57 /*!< Offset: 0x0C0-0x0CC Reserved (RAZWI) */ 58 volatile uint32_t cntscr0; 59 /*!< Offset: 0x0D0 (R/W) Counter Scale Register 0 */ 60 volatile uint32_t cntscr1; 61 /*!< Offset: 0x0D4 (R/W) Counter Scale Register 1 */ 62 volatile const uint32_t reserved3[958]; 63 /*!< Offset: 0x0D8-0xFCC Reserved (RAZWI) */ 64 volatile const uint32_t cntpidr4; 65 /*!< Offset: 0xFD0 (RO) Peripheral ID Register */ 66 volatile const uint32_t reserved4[3]; 67 /*!< Offset: 0xFD4-0xFDC Reserved (RAZWI) */ 68 volatile const uint32_t cntpidr0; 69 /*!< Offset: 0xFE0 (RO) Peripheral ID Register */ 70 volatile const uint32_t cntpidr1; 71 /*!< Offset: 0xFE4 (RO) Peripheral ID Register */ 72 volatile const uint32_t cntpidr2; 73 /*!< Offset: 0xFE8 (RO) Peripheral ID Register */ 74 volatile const uint32_t cntpidr3; 75 /*!< Offset: 0xFEC (RO) Peripheral ID Register */ 76 volatile const uint32_t cntcidr0; 77 /*!< Offset: 0xFF0 (RO) Component ID Register */ 78 volatile const uint32_t cntcidr1; 79 /*!< Offset: 0xFF4 (RO) Component ID Register */ 80 volatile const uint32_t cntcidr2; 81 /*!< Offset: 0xFF8 (RO) Component ID Register */ 82 volatile const uint32_t cntcidr3; 83 /*!< Offset: 0xFFC (RO) Component ID Register */ 84 }; 85 86 #ifdef __cplusplus 87 } 88 #endif 89 90 #endif /* __SYSCOUNTER_ARMV8_M_CNTRL_REG_MAP_H__ */ 91
