1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 /********************************************************************************************************
20 * @file sys.c
21 *
22 * @brief This is the source file for B91
23 *
24 * @author Driver Group
25 *
26 *******************************************************************************************************/
27 #include "sys.h"
28 #include "core.h"
29 #include "pm.h"
30 #include "compiler.h"
31 #include "analog.h"
32 #include "gpio.h"
33 #include "mspi.h"
34 #include "stimer.h"
35
36
37 unsigned int g_chip_version=0;
38
39 extern void pm_update_status_info(void);
40
41 /**
42 * @brief This function serves to initialize system.
43 * @param[in] power_mode - power mode(LDO/DCDC/LDO_DCDC)
44 * @param[in] vbat_v - vbat voltage type: 0 vbat may be greater than 3.6V, 1 vbat must be below 3.6V.
45 * @return none
46 */
sys_init(power_mode_e power_mode,vbat_type_e vbat_v)47 void sys_init(power_mode_e power_mode, vbat_type_e vbat_v)
48 {
49 /**
50 * reset function will be cleared by set "1",which is different from the previous configuration.
51 * This setting turns off the TRNG and NPE modules in order to test power consumption.The current
52 * decrease about 3mA when those two modules be turn off.changed by zhiwei,confirmed by kaixin.20200828.
53 */
54 reg_rst = 0xffbbffff;
55 reg_clk_en = 0xffbbffff;
56
57 analog_write_reg8(0x8c,0x02); //<1>:reg_xo_en_clk_ana_ana=1
58
59 //when VBAT power supply > 4.1V and LDO switch to DCDC,DCDC_1V8 voltage will ascend to the supply power in a period time,
60 //cause the program can not run. Need to trim down dcdc_flash_out before switch power mode.
61 //confirmed by haitao,modify by yi.bao(20210119)
62 if(DCDC_1P4_DCDC_1P8 == power_mode)
63 {
64 analog_write_reg8(0x0c, 0x40); //poweron_dft: 0x44 --> 0x40.
65 //<2:0> dcdc_trim_flash_out,flash/codec 1.8V/2.8V trim down 0.2V in DCDC mode.
66 }
67 analog_write_reg8(0x0a, power_mode);//poweron_dft: 0x90.
68 //<0-1>:pd_dcdc_ldo_sw, default:00, dcdc & bypass ldo status bits.
69 // dcdc_1p4 dcdc_1p8 ldo_1p4 ldo_1p8
70 //00: N N Y Y
71 //01: Y N N Y
72 //10: Y N N N
73 //11: Y Y N N
74 analog_write_reg8(0x0b, 0x3b); //poweron_dft: 0x7b -> 0x3b.
75 //<6>:mscn_pullup_res_enb, default:1,->0 enable 1M pullup resistor for mscn PAD.
76 analog_write_reg8(0x05,analog_read_reg8(0x05) & (~BIT(3)));//poweron_dft: 0x02 -> 0x02.
77 //<3>:24M_xtl_pd, default:0,->0 Power up 24MHz XTL oscillator.
78 analog_write_reg8(0x06,analog_read_reg8(0x06) & ~(BIT(0) | vbat_v | BIT(6) | BIT(7)));//poweron_dft: 0xff -> 0x36 or 0x3e.
79 //<0>:pd_bbpll_ldo, default:1,->0 Power on ana LDO.
80 //<3>:pd_vbus_sw, default:1,->0 Power up of bypass switch.
81 //<6>:spd_ldo_pd, default:1,->0 Power up spd ldo.
82 //<7>:dig_ret_pd, default:1,->0 Power up retention ldo.
83 analog_write_reg8(0x01, 0x45); //poweron_dft: 0x44 -> 0x45.
84 //<0-2>:bbpll_ldo_trim, default:100,->101 measured 1.186V.The default value is sometimes crashes.
85 //<4-6>:ana_ldo_trim,1.0-1.4V default:100,->100 analog LDO output voltage trim: 1.2V
86
87 write_csr(NDS_MILMB,0x01);
88 write_csr(NDS_MDLMB,0x80001);
89
90 pm_update_status_info();
91 g_pm_vbat_v = vbat_v>>3;
92
93 //xo_ready check should be done after Xtal manual on_off, we put it here to save code running time, code running time between
94 //Xtal manual on_off and xo_ready check can be used as Xtal be stable timimg.
95 while( BIT(7) != (analog_read_reg8(0x88) & (BIT(7)))); //<7>: xo_ready_ana, R, aura xtl ready signal.
96
97 //When bbpll_ldo_trim is set to the default voltage value, when doing high and low temperature stability tests,it is found that
98 //there is a crash.The current workaround is to set other voltage values to see if it is stable.If it fails,repeat the setting
99 //up to three times.The bbpll ldo trim must wait until 24M is stable.(add by weihua.zhang, confirmed by yi.bao and wenfeng 20200924)
100 pm_wait_bbpll_done();
101
102 if(g_pm_status_info.mcu_status == MCU_STATUS_DEEPRET_BACK)
103 {
104 pm_stimer_recover();
105 }else{
106 #if SYS_TIMER_AUTO_MODE
107 reg_system_ctrl |=(FLD_SYSTEM_TIMER_AUTO|FLD_SYSTEM_32K_TRACK_EN); //enable 32k track and stimer auto.
108 reg_system_tick = 0x01; //initial next tick is 1,kick system timer
109 #else
110 reg_system_ctrl |= FLD_SYSTEM_32K_TRACK_EN | FLD_SYSTEM_TIMER_EN; //enable 32k track and stimer. Wait for pll to stabilize before using stimer.
111 #endif
112 }
113
114 g_chip_version = read_reg8(0x1401fd);
115
116 //if clock src is PAD or PLL, and hclk = 1/2cclk, use reboot may cause problem, need deep to resolve(add by yi.bao, confirm by guangjun 20201016)
117 if(g_pm_status_info.mcu_status == MCU_STATUS_REBOOT_BACK)
118 {
119 //Use PM_ANA_REG_POWER_ON_CLR_BUF0 BIT(1) to represent the reboot+deep process, which is related to the function pm_update_status_info.
120 analog_write_reg8(PM_ANA_REG_POWER_ON_CLR_BUF0, analog_read_reg8(PM_ANA_REG_POWER_ON_CLR_BUF0) | BIT(1)); //(add by weihua.zhang, confirmed by yi.bao 20201222)
121 pm_sleep_wakeup(DEEPSLEEP_MODE, PM_WAKEUP_TIMER, PM_TICK_STIMER_16M, (stimer_get_tick() + 100*SYSTEM_TIMER_TICK_1MS));
122 }
123 //**When testing AES_demo, it was found that the timing of baseband was wrong when it was powered on, which caused some of
124 //the registers of ceva to go wrong, which caused the program to run abnormally.(add by weihua.zhang, confirmed by junwen 20200819)
125 else if(0xff == g_chip_version) //A0
126 {
127 if(g_pm_status_info.mcu_status == MCU_STATUS_POWER_ON) //power on
128 {
129 analog_write_reg8(0x7d, 0x80); //power on baseband
130 pm_sleep_wakeup(DEEPSLEEP_MODE, PM_WAKEUP_TIMER, PM_TICK_STIMER_16M, (stimer_get_tick() + 100*SYSTEM_TIMER_TICK_1MS));
131 }
132 }
133 analog_write_reg8(0x7d, 0x80); //poweron_dft: 0x03 -> 0x80.
134 //<0>:pg_zb_en, default:1,->0 power on baseband.
135 //<1>:pg_usb_en, default:1,->0 power on usb.
136 //<2>:pg_npe_en, default:1,->0 power on npe.
137 //<7>:pg_clk_en, default:0,->1 enable change power sequence clk.
138 }
139
140
