1/*
2 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <zephyr/dt-bindings/i2c/i2c.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10
11#define DT_APB_CLK_HZ	50000000
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "snps,arcem";
21			reg = <0>;
22		};
23	};
24
25	intc: arcv2-intc {
26		compatible = "snps,arcv2-intc";
27		interrupt-controller;
28		#interrupt-cells = <2>;
29	};
30
31	timer0: timer0 {
32		compatible = "snps,arc-timer";
33		interrupts = <16 1>;
34		interrupt-parent = <&intc>;
35	};
36
37	timer1: timer1 {
38		compatible = "snps,arc-timer";
39		interrupts = <17 1>;
40		interrupt-parent = <&intc>;
41	};
42
43	sysclk: system-clock {
44		compatible = "fixed-clock";
45		clock-frequency = <DT_APB_CLK_HZ>;
46		#clock-cells = <0>;
47	};
48
49	soc {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		compatible = "simple-bus";
53		ranges;
54
55		ddr0: memory@10000000 {
56			device_type = "memory";
57			reg = <0x10000000 0x8000000>;
58		};
59
60
61		i2c0: i2c@f0004000 {
62			compatible = "snps,designware-i2c";
63			clock-frequency = <I2C_BITRATE_STANDARD>;
64			#address-cells = <1>;
65			#size-cells = <0>;
66			reg = <0xf0004000 0x1000>;
67			interrupt-parent = <&intc>;
68		};
69
70		i2c1: i2c@f0005000 {
71			compatible = "snps,designware-i2c";
72			clock-frequency = <I2C_BITRATE_STANDARD>;
73			#address-cells = <1>;
74			#size-cells = <0>;
75			reg = <0xf0005000 0x1000>;
76			interrupt-parent = <&intc>;
77		};
78
79		uart0: uart@f0008000 {
80			compatible = "ns16550";
81			clock-frequency = <DT_APB_CLK_HZ>;
82			reg = <0xf0008000 0x1000>;
83			interrupt-parent = <&intc>;
84			reg-shift = <2>;
85		};
86
87		uart1: uart@f0009000 {
88			compatible = "ns16550";
89			clock-frequency = <DT_APB_CLK_HZ>;
90			reg = <0xf0009000 0x1000>;
91			interrupt-parent = <&intc>;
92			reg-shift = <2>;
93		};
94
95		uart2: uart@f000a000 {
96			compatible = "ns16550";
97			clock-frequency = <DT_APB_CLK_HZ>;
98			reg = <0xf000a000 0x1000>;
99			interrupt-parent = <&intc>;
100			reg-shift = <2>;
101		};
102
103		gpio0: gpio@f0002000 {
104			compatible = "snps,designware-gpio";
105			reg = <0xf0002000 0xc>;
106			ngpios = <32>;
107			interrupt-parent = <&intc>;
108
109			gpio-controller;
110			#gpio-cells = <2>;
111		};
112
113		gpio1: gpio@f000200c {
114			compatible = "snps,designware-gpio";
115			reg = <0xf000200c 0xc>;
116			ngpios = <9>;
117			interrupt-parent = <&intc>;
118
119			gpio-controller;
120			#gpio-cells = <2>;
121		};
122
123		gpio2: gpio@f0002018 {
124			compatible = "snps,designware-gpio";
125			reg = <0xF0002018 0xc>;
126			ngpios = <32>;
127
128			interrupt-parent = <&intc>;
129
130			gpio-controller;
131			#gpio-cells = <2>;
132		};
133
134		gpio3: gpio@f0002024 {
135			compatible = "snps,designware-gpio";
136			reg = <0xF0002024 0xc>;
137			ngpios = <12>;
138
139			interrupt-parent = <&intc>;
140
141			gpio-controller;
142			#gpio-cells = <2>;
143		};
144
145		spi0: spi@f0006000 {
146			compatible = "snps,designware-spi";
147			reg = <0xf0006000 0x1000>;
148			clocks = <&sysclk>;
149			interrupt-parent = <&intc>;
150			fifo-depth = <32>;
151			#address-cells = <1>;
152			#size-cells = <0>;
153
154		};
155
156		spi1: spi@f0007000 {
157			compatible = "snps,designware-spi";
158			reg = <0xf0007000 0x1000>;
159			clocks = <&sysclk>;
160			interrupt-parent = <&intc>;
161			fifo-depth = <32>;
162			#address-cells = <1>;
163			#size-cells = <0>;
164
165		};
166
167	};
168};
169