1 /*
2 * Copyright (c) 2017-2021 IAR Systems
3 * Copyright (c) 2017-2024 Arm Limited. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19
20 /*
21 * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File
22 */
23
24 #ifndef __CMSIS_ICCARM_M_H__
25 #define __CMSIS_ICCARM_M_H__
26
27 #ifndef __ICCARM__
28 #error This file should only be compiled by ICCARM
29 #endif
30
31 #pragma system_include
32
33 #define __IAR_FT _Pragma("inline=forced") __intrinsic
34
35 #if (__VER__ >= 8000000)
36 #define __ICCARM_V8 1
37 #else
38 #define __ICCARM_V8 0
39 #endif
40
41 #ifndef __ALIGNED
42 #if __ICCARM_V8
43 #define __ALIGNED(x) __attribute__((aligned(x)))
44 #elif (__VER__ >= 7080000)
45 /* Needs IAR language extensions */
46 #define __ALIGNED(x) __attribute__((aligned(x)))
47 #else
48 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
49 #define __ALIGNED(x)
50 #endif
51 #endif
52
53
54 /* Define compiler macros for CPU architecture, used in CMSIS 5.
55 */
56 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__
57 /* Macros already defined */
58 #else
59 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
60 #define __ARM_ARCH_8M_MAIN__ 1
61 #elif defined(__ARM8M_BASELINE__)
62 #define __ARM_ARCH_8M_BASE__ 1
63 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
64 #if __ARM_ARCH == 6
65 #define __ARM_ARCH_6M__ 1
66 #elif __ARM_ARCH == 7
67 #if __ARM_FEATURE_DSP
68 #define __ARM_ARCH_7EM__ 1
69 #else
70 #define __ARM_ARCH_7M__ 1
71 #endif
72 #elif __ARM_ARCH == 801
73 #define __ARM_ARCH_8_1M_MAIN__ 1
74 #endif /* __ARM_ARCH */
75 #endif /* __ARM_ARCH_PROFILE == 'M' */
76 #endif
77
78 /* Alternativ core deduction for older ICCARM's */
79 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
80 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__)
81 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
82 #define __ARM_ARCH_6M__ 1
83 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
84 #define __ARM_ARCH_7M__ 1
85 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
86 #define __ARM_ARCH_7EM__ 1
87 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
88 #define __ARM_ARCH_8M_BASE__ 1
89 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
90 #define __ARM_ARCH_8M_MAIN__ 1
91 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
92 #define __ARM_ARCH_8M_MAIN__ 1
93 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801
94 #define __ARM_ARCH_8_1M_MAIN__ 1
95 #else
96 #error "Unknown target."
97 #endif
98 #endif
99
100
101
102 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
103 #define __IAR_M0_FAMILY 1
104 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
105 #define __IAR_M0_FAMILY 1
106 #else
107 #define __IAR_M0_FAMILY 0
108 #endif
109
110 #ifndef __NO_INIT
111 #define __NO_INIT __attribute__ ((section (".noinit")))
112 #endif
113 #ifndef __ALIAS
114 #define __ALIAS(x) __attribute__ ((alias(x)))
115 #endif
116
117 #ifndef __ASM
118 #define __ASM __asm
119 #endif
120
121 #ifndef __COMPILER_BARRIER
122 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
123 #endif
124
125 #ifndef __INLINE
126 #define __INLINE inline
127 #endif
128
129 #ifndef __NO_RETURN
130 #if defined(__cplusplus) && __cplusplus >= 201103L
131 #define __NO_RETURN [[noreturn]]
132 #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
133 #define __NO_RETURN _Noreturn
134 #else
135 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
136 #endif
137 #endif
138
139 #ifndef __PACKED
140 #if __ICCARM_V8
141 #define __PACKED __attribute__((packed, aligned(1)))
142 #else
143 /* Needs IAR language extensions */
144 #define __PACKED __packed
145 #endif
146 #endif
147
148 #ifndef __PACKED_STRUCT
149 #if __ICCARM_V8
150 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
151 #else
152 /* Needs IAR language extensions */
153 #define __PACKED_STRUCT __packed struct
154 #endif
155 #endif
156
157 #ifndef __PACKED_UNION
158 #if __ICCARM_V8
159 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
160 #else
161 /* Needs IAR language extensions */
162 #define __PACKED_UNION __packed union
163 #endif
164 #endif
165
166 #ifndef __RESTRICT
167 #if __ICCARM_V8
168 #define __RESTRICT __restrict
169 #else
170 /* Needs IAR language extensions */
171 #define __RESTRICT restrict
172 #endif
173 #endif
174
175 #ifndef __STATIC_INLINE
176 #define __STATIC_INLINE static inline
177 #endif
178
179 #ifndef __FORCEINLINE
180 #define __FORCEINLINE _Pragma("inline=forced")
181 #endif
182
183 #ifndef __STATIC_FORCEINLINE
184 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
185 #endif
186
187 #ifndef __UNALIGNED_UINT16_READ
188 #pragma language=save
189 #pragma language=extended
__iar_uint16_read(void const * ptr)190 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
191 {
192 return *(__packed uint16_t*)(ptr);
193 }
194 #pragma language=restore
195 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
196 #endif
197
198
199 #ifndef __UNALIGNED_UINT16_WRITE
200 #pragma language=save
201 #pragma language=extended
__iar_uint16_write(void const * ptr,uint16_t val)202 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
203 {
204 *(__packed uint16_t*)(ptr) = val;;
205 }
206 #pragma language=restore
207 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
208 #endif
209
210 #ifndef __UNALIGNED_UINT32_READ
211 #pragma language=save
212 #pragma language=extended
__iar_uint32_read(void const * ptr)213 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
214 {
215 return *(__packed uint32_t*)(ptr);
216 }
217 #pragma language=restore
218 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
219 #endif
220
221 #ifndef __UNALIGNED_UINT32_WRITE
222 #pragma language=save
223 #pragma language=extended
__iar_uint32_write(void const * ptr,uint32_t val)224 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
225 {
226 *(__packed uint32_t*)(ptr) = val;;
227 }
228 #pragma language=restore
229 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
230 #endif
231
232 #ifndef __UNALIGNED_UINT32 /* deprecated */
233 #pragma language=save
234 #pragma language=extended
235 __packed struct __iar_u32 { uint32_t v; };
236 #pragma language=restore
237 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
238 #endif
239
240 #ifndef __USED
241 #if __ICCARM_V8
242 #define __USED __attribute__((used))
243 #else
244 #define __USED _Pragma("__root")
245 #endif
246 #endif
247
248 #undef __WEAK /* undo the definition from DLib_Defaults.h */
249 #ifndef __WEAK
250 #if __ICCARM_V8
251 #define __WEAK __attribute__((weak))
252 #else
253 #define __WEAK _Pragma("__weak")
254 #endif
255 #endif
256
257 #ifndef __PROGRAM_START
258 #define __PROGRAM_START __iar_program_start
259 #endif
260
261 #ifndef __INITIAL_SP
262 #define __INITIAL_SP CSTACK$$Limit
263 #endif
264
265 #ifndef __STACK_LIMIT
266 #define __STACK_LIMIT CSTACK$$Base
267 #endif
268
269 #ifndef __VECTOR_TABLE
270 #define __VECTOR_TABLE __vector_table
271 #endif
272
273 #ifndef __VECTOR_TABLE_ATTRIBUTE
274 #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
275 #endif
276
277 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
278 #ifndef __STACK_SEAL
279 #define __STACK_SEAL STACKSEAL$$Base
280 #endif
281
282 #ifndef __TZ_STACK_SEAL_SIZE
283 #define __TZ_STACK_SEAL_SIZE 8U
284 #endif
285
286 #ifndef __TZ_STACK_SEAL_VALUE
287 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
288 #endif
289
__TZ_set_STACKSEAL_S(uint32_t * stackTop)290 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
291 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
292 }
293 #endif
294
295 #ifndef __ICCARM_INTRINSICS_VERSION__
296 #define __ICCARM_INTRINSICS_VERSION__ 0
297 #endif
298
299 #if __ICCARM_INTRINSICS_VERSION__ == 2
300
301 #if defined(__CLZ)
302 #undef __CLZ
303 #endif
304 #if defined(__REVSH)
305 #undef __REVSH
306 #endif
307 #if defined(__RBIT)
308 #undef __RBIT
309 #endif
310 #if defined(__SSAT)
311 #undef __SSAT
312 #endif
313 #if defined(__USAT)
314 #undef __USAT
315 #endif
316
317 #include "iccarm_builtin.h"
318
319 #define __disable_irq __iar_builtin_disable_interrupt
320 #define __enable_irq __iar_builtin_enable_interrupt
321 #define __arm_rsr __iar_builtin_rsr
322 #define __arm_wsr __iar_builtin_wsr
323
324
325 #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2)
__disable_fault_irq()326 __IAR_FT void __disable_fault_irq()
327 {
328 __ASM volatile ("CPSID F" ::: "memory");
329 }
330
__enable_fault_irq()331 __IAR_FT void __enable_fault_irq()
332 {
333 __ASM volatile ("CPSIE F" ::: "memory");
334 }
335 #endif
336
337
338 #define __get_APSR() (__arm_rsr("APSR"))
339 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
340 #define __get_CONTROL() (__arm_rsr("CONTROL"))
341 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
342
343 #if (defined (__ARM_FP) && (__ARM_FP >= 1))
344 #define __get_FPSCR() (__arm_rsr("FPSCR"))
345 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
346 #else
347 #define __get_FPSCR() ( 0 )
348 #define __set_FPSCR(VALUE) ((void)VALUE)
349 #endif
350
351 #define __get_IPSR() (__arm_rsr("IPSR"))
352 #define __get_MSP() (__arm_rsr("MSP"))
353 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
354 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
355 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
356 // without main extensions, the non-secure MSPLIM is RAZ/WI
357 #define __get_MSPLIM() (0U)
358 #else
359 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
360 #endif
361 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
362 #define __get_PSP() (__arm_rsr("PSP"))
363
364 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
365 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
366 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
367 // without main extensions, the non-secure PSPLIM is RAZ/WI
368 #define __get_PSPLIM() (0U)
369 #else
370 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
371 #endif
372
373 #define __get_xPSR() (__arm_rsr("xPSR"))
374
375 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
376 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
377
__set_CONTROL(uint32_t control)378 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
379 {
380 __arm_wsr("CONTROL", control);
381 __iar_builtin_ISB();
382 }
383
384 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
385 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
386
387 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
388 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
389 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
390 // without main extensions, the non-secure MSPLIM is RAZ/WI
391 #define __set_MSPLIM(VALUE) ((void)(VALUE))
392 #else
393 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
394 #endif
395 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
396 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
397 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
398 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
399 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
400 // without main extensions, the non-secure PSPLIM is RAZ/WI
401 #define __set_PSPLIM(VALUE) ((void)(VALUE))
402 #else
403 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
404 #endif
405
406 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
407
__TZ_set_CONTROL_NS(uint32_t control)408 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
409 {
410 __arm_wsr("CONTROL_NS", control);
411 __iar_builtin_ISB();
412 }
413
414 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
415 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
416 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
417 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
418 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
419 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
420 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
421 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
422 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
423 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
424 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
425 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
426
427 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
428 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
429 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
430 // without main extensions, the non-secure PSPLIM is RAZ/WI
431 #define __TZ_get_PSPLIM_NS() (0U)
432 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
433 #else
434 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
435 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
436 #endif
437
438 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
439 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
440
441 #define __NOP __iar_builtin_no_operation
442
443 #define __CLZ __iar_builtin_CLZ
444
445 /*
446 * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations.
447 * As a workaround we use inline assembly and a memory barrier.
448 * (IAR issue EWARM-11901)
449 */
450 #define __CLREX() (__ASM volatile ("CLREX" ::: "memory"))
451
452 #define __DMB __iar_builtin_DMB
453 #define __DSB __iar_builtin_DSB
454 #define __ISB __iar_builtin_ISB
455
456 #define __LDREXB __iar_builtin_LDREXB
457 #define __LDREXH __iar_builtin_LDREXH
458 #define __LDREXW __iar_builtin_LDREX
459
460 #define __RBIT __iar_builtin_RBIT
461 #define __REV __iar_builtin_REV
462 #define __REV16 __iar_builtin_REV16
463
__REVSH(int16_t val)464 __IAR_FT int16_t __REVSH(int16_t val)
465 {
466 return (int16_t) __iar_builtin_REVSH(val);
467 }
468
469 #define __ROR __iar_builtin_ROR
470 #define __RRX __iar_builtin_RRX
471
472 #define __SEV __iar_builtin_SEV
473
474 #if !__IAR_M0_FAMILY
475 #define __SSAT __iar_builtin_SSAT
476 #endif
477
478 #define __STREXB __iar_builtin_STREXB
479 #define __STREXH __iar_builtin_STREXH
480 #define __STREXW __iar_builtin_STREX
481
482 #if !__IAR_M0_FAMILY
483 #define __USAT __iar_builtin_USAT
484 #endif
485
486 #define __WFE __iar_builtin_WFE
487 #define __WFI __iar_builtin_WFI
488
489 #if __ARM_MEDIA__
490 #define __SADD8 __iar_builtin_SADD8
491 #define __QADD8 __iar_builtin_QADD8
492 #define __SHADD8 __iar_builtin_SHADD8
493 #define __UADD8 __iar_builtin_UADD8
494 #define __UQADD8 __iar_builtin_UQADD8
495 #define __UHADD8 __iar_builtin_UHADD8
496 #define __SSUB8 __iar_builtin_SSUB8
497 #define __QSUB8 __iar_builtin_QSUB8
498 #define __SHSUB8 __iar_builtin_SHSUB8
499 #define __USUB8 __iar_builtin_USUB8
500 #define __UQSUB8 __iar_builtin_UQSUB8
501 #define __UHSUB8 __iar_builtin_UHSUB8
502 #define __SADD16 __iar_builtin_SADD16
503 #define __QADD16 __iar_builtin_QADD16
504 #define __SHADD16 __iar_builtin_SHADD16
505 #define __UADD16 __iar_builtin_UADD16
506 #define __UQADD16 __iar_builtin_UQADD16
507 #define __UHADD16 __iar_builtin_UHADD16
508 #define __SSUB16 __iar_builtin_SSUB16
509 #define __QSUB16 __iar_builtin_QSUB16
510 #define __SHSUB16 __iar_builtin_SHSUB16
511 #define __USUB16 __iar_builtin_USUB16
512 #define __UQSUB16 __iar_builtin_UQSUB16
513 #define __UHSUB16 __iar_builtin_UHSUB16
514 #define __SASX __iar_builtin_SASX
515 #define __QASX __iar_builtin_QASX
516 #define __SHASX __iar_builtin_SHASX
517 #define __UASX __iar_builtin_UASX
518 #define __UQASX __iar_builtin_UQASX
519 #define __UHASX __iar_builtin_UHASX
520 #define __SSAX __iar_builtin_SSAX
521 #define __QSAX __iar_builtin_QSAX
522 #define __SHSAX __iar_builtin_SHSAX
523 #define __USAX __iar_builtin_USAX
524 #define __UQSAX __iar_builtin_UQSAX
525 #define __UHSAX __iar_builtin_UHSAX
526 #define __USAD8 __iar_builtin_USAD8
527 #define __USADA8 __iar_builtin_USADA8
528 #define __SSAT16 __iar_builtin_SSAT16
529 #define __USAT16 __iar_builtin_USAT16
530 #define __UXTB16 __iar_builtin_UXTB16
531 #define __UXTAB16 __iar_builtin_UXTAB16
532 #define __SXTB16 __iar_builtin_SXTB16
533 #define __SXTAB16 __iar_builtin_SXTAB16
534 #define __SMUAD __iar_builtin_SMUAD
535 #define __SMUADX __iar_builtin_SMUADX
536 #define __SMMLA __iar_builtin_SMMLA
537 #define __SMLAD __iar_builtin_SMLAD
538 #define __SMLADX __iar_builtin_SMLADX
539 #define __SMLALD __iar_builtin_SMLALD
540 #define __SMLALDX __iar_builtin_SMLALDX
541 #define __SMUSD __iar_builtin_SMUSD
542 #define __SMUSDX __iar_builtin_SMUSDX
543 #define __SMLSD __iar_builtin_SMLSD
544 #define __SMLSDX __iar_builtin_SMLSDX
545 #define __SMLSLD __iar_builtin_SMLSLD
546 #define __SMLSLDX __iar_builtin_SMLSLDX
547 #define __SEL __iar_builtin_SEL
548 #define __QADD __iar_builtin_QADD
549 #define __QSUB __iar_builtin_QSUB
550 #define __PKHBT __iar_builtin_PKHBT
551 #define __PKHTB __iar_builtin_PKHTB
552 #endif
553
554 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
555
556 #if __IAR_M0_FAMILY
557 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
558 #define __CLZ __cmsis_iar_clz_not_active
559 #define __SSAT __cmsis_iar_ssat_not_active
560 #define __USAT __cmsis_iar_usat_not_active
561 #define __RBIT __cmsis_iar_rbit_not_active
562 #define __get_APSR __cmsis_iar_get_APSR_not_active
563 #endif
564
565
566 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
567 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
568 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
569 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
570 #endif
571
572 #ifdef __INTRINSICS_INCLUDED
573 #error intrinsics.h is already included previously!
574 #endif
575
576 #include <intrinsics.h>
577
578 #if __IAR_M0_FAMILY
579 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
580 #undef __CLZ
581 #undef __SSAT
582 #undef __USAT
583 #undef __RBIT
584 #undef __get_APSR
585
__CLZ(uint32_t data)586 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
587 {
588 if (data == 0U) { return 32U; }
589
590 uint32_t count = 0U;
591 uint32_t mask = 0x80000000U;
592
593 while ((data & mask) == 0U)
594 {
595 count += 1U;
596 mask = mask >> 1U;
597 }
598 return count;
599 }
600
__RBIT(uint32_t v)601 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
602 {
603 uint8_t sc = 31U;
604 uint32_t r = v;
605 for (v >>= 1U; v; v >>= 1U)
606 {
607 r <<= 1U;
608 r |= v & 1U;
609 sc--;
610 }
611 return (r << sc);
612 }
613
__get_APSR(void)614 __STATIC_INLINE uint32_t __get_APSR(void)
615 {
616 uint32_t res;
617 __asm("MRS %0,APSR" : "=r" (res));
618 return res;
619 }
620
621 #endif
622
623 #if (!(defined (__ARM_FP) && (__ARM_FP >= 1)))
624 #undef __get_FPSCR
625 #undef __set_FPSCR
626 #define __get_FPSCR() (0)
627 #define __set_FPSCR(VALUE) ((void)VALUE)
628 #endif
629
630 #pragma diag_suppress=Pe940
631 #pragma diag_suppress=Pe177
632
633 #define __enable_irq __enable_interrupt
634 #define __disable_irq __disable_interrupt
635 #define __NOP __no_operation
636
637 #define __get_xPSR __get_PSR
638
639 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
640
__LDREXW(uint32_t volatile * ptr)641 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
642 {
643 return __LDREX((unsigned long *)ptr);
644 }
645
__STREXW(uint32_t value,uint32_t volatile * ptr)646 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
647 {
648 return __STREX(value, (unsigned long *)ptr);
649 }
650 #endif
651
652
653 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
654 #if (__CORTEX_M >= 0x03)
655
__RRX(uint32_t value)656 __IAR_FT uint32_t __RRX(uint32_t value)
657 {
658 uint32_t result;
659 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
660 return(result);
661 }
662
__set_BASEPRI_MAX(uint32_t value)663 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
664 {
665 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
666 }
667
__disable_fault_irq()668 __IAR_FT void __disable_fault_irq()
669 {
670 __ASM volatile ("CPSID F" ::: "memory");
671 }
672
__enable_fault_irq()673 __IAR_FT void __enable_fault_irq()
674 {
675 __ASM volatile ("CPSIE F" ::: "memory");
676 }
677
678
679 #endif /* (__CORTEX_M >= 0x03) */
680
__ROR(uint32_t op1,uint32_t op2)681 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
682 {
683 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
684 }
685
686 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
687 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
688 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
689
__get_MSPLIM(void)690 __IAR_FT uint32_t __get_MSPLIM(void)
691 {
692 uint32_t res;
693 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
694 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
695 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
696 // without main extension and secure, there is no stack limit check.
697 res = 0U;
698 #else
699 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
700 #endif
701 return res;
702 }
703
__set_MSPLIM(uint32_t value)704 __IAR_FT void __set_MSPLIM(uint32_t value)
705 {
706 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
707 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
708 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
709 // without main extensions and secure, there is no stack limit check.
710 (void)value;
711 #else
712 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
713 #endif
714 }
715
__get_PSPLIM(void)716 __IAR_FT uint32_t __get_PSPLIM(void)
717 {
718 uint32_t res;
719 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
720 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
721 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
722 // without main extensions and secure, there is no stack limit check.
723 res = 0U;
724 #else
725 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
726 #endif
727 return res;
728 }
729
__set_PSPLIM(uint32_t value)730 __IAR_FT void __set_PSPLIM(uint32_t value)
731 {
732 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
733 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
734 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
735 // without main extensions and secure, there is no stack limit check.
736 (void)value;
737 #else
738 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
739 #endif
740 }
741
__TZ_get_CONTROL_NS(void)742 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
743 {
744 uint32_t res;
745 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
746 return res;
747 }
748
__TZ_set_CONTROL_NS(uint32_t value)749 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
750 {
751 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
752 __iar_builtin_ISB();
753 }
754
__TZ_get_PSP_NS(void)755 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
756 {
757 uint32_t res;
758 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
759 return res;
760 }
761
__TZ_set_PSP_NS(uint32_t value)762 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
763 {
764 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
765 }
766
__TZ_get_MSP_NS(void)767 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
768 {
769 uint32_t res;
770 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
771 return res;
772 }
773
__TZ_set_MSP_NS(uint32_t value)774 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
775 {
776 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
777 }
778
__TZ_get_SP_NS(void)779 __IAR_FT uint32_t __TZ_get_SP_NS(void)
780 {
781 uint32_t res;
782 __asm volatile("MRS %0,SP_NS" : "=r" (res));
783 return res;
784 }
__TZ_set_SP_NS(uint32_t value)785 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
786 {
787 __asm volatile("MSR SP_NS,%0" :: "r" (value));
788 }
789
__TZ_get_PRIMASK_NS(void)790 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
791 {
792 uint32_t res;
793 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
794 return res;
795 }
796
__TZ_set_PRIMASK_NS(uint32_t value)797 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
798 {
799 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
800 }
801
__TZ_get_BASEPRI_NS(void)802 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
803 {
804 uint32_t res;
805 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
806 return res;
807 }
808
__TZ_set_BASEPRI_NS(uint32_t value)809 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
810 {
811 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
812 }
813
__TZ_get_FAULTMASK_NS(void)814 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
815 {
816 uint32_t res;
817 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
818 return res;
819 }
820
__TZ_set_FAULTMASK_NS(uint32_t value)821 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
822 {
823 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
824 }
825
__TZ_get_PSPLIM_NS(void)826 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
827 {
828 uint32_t res;
829 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
830 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
831 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
832 // without main extensions, the non-secure PSPLIM is RAZ/WI
833 res = 0U;
834 #else
835 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
836 #endif
837 return res;
838 }
839
__TZ_set_PSPLIM_NS(uint32_t value)840 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
841 {
842 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
843 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
844 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
845 // without main extensions, the non-secure PSPLIM is RAZ/WI
846 (void)value;
847 #else
848 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
849 #endif
850 }
851
__TZ_get_MSPLIM_NS(void)852 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
853 {
854 uint32_t res;
855 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
856 return res;
857 }
858
__TZ_set_MSPLIM_NS(uint32_t value)859 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
860 {
861 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
862 }
863
864 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */
865
866 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
867
868 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
869
870 #if __IAR_M0_FAMILY
__SSAT(int32_t val,uint32_t sat)871 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
872 {
873 if ((sat >= 1U) && (sat <= 32U))
874 {
875 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
876 const int32_t min = -1 - max ;
877 if (val > max)
878 {
879 return max;
880 }
881 else if (val < min)
882 {
883 return min;
884 }
885 }
886 return val;
887 }
888
__USAT(int32_t val,uint32_t sat)889 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
890 {
891 if (sat <= 31U)
892 {
893 const uint32_t max = ((1U << sat) - 1U);
894 if (val > (int32_t)max)
895 {
896 return max;
897 }
898 else if (val < 0)
899 {
900 return 0U;
901 }
902 }
903 return (uint32_t)val;
904 }
905 #endif
906
907 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
908
__LDRBT(volatile uint8_t * addr)909 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
910 {
911 uint32_t res;
912 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
913 return ((uint8_t)res);
914 }
915
__LDRHT(volatile uint16_t * addr)916 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
917 {
918 uint32_t res;
919 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
920 return ((uint16_t)res);
921 }
922
__LDRT(volatile uint32_t * addr)923 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
924 {
925 uint32_t res;
926 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
927 return res;
928 }
929
__STRBT(uint8_t value,volatile uint8_t * addr)930 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
931 {
932 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
933 }
934
__STRHT(uint16_t value,volatile uint16_t * addr)935 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
936 {
937 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
938 }
939
__STRT(uint32_t value,volatile uint32_t * addr)940 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
941 {
942 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
943 }
944
945 #endif /* (__CORTEX_M >= 0x03) */
946
947 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
948 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
949 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
950
951
__LDAB(volatile uint8_t * ptr)952 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
953 {
954 uint32_t res;
955 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
956 return ((uint8_t)res);
957 }
958
__LDAH(volatile uint16_t * ptr)959 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
960 {
961 uint32_t res;
962 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
963 return ((uint16_t)res);
964 }
965
__LDA(volatile uint32_t * ptr)966 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
967 {
968 uint32_t res;
969 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
970 return res;
971 }
972
__STLB(uint8_t value,volatile uint8_t * ptr)973 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
974 {
975 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
976 }
977
__STLH(uint16_t value,volatile uint16_t * ptr)978 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
979 {
980 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
981 }
982
__STL(uint32_t value,volatile uint32_t * ptr)983 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
984 {
985 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
986 }
987
__LDAEXB(volatile uint8_t * ptr)988 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
989 {
990 uint32_t res;
991 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
992 return ((uint8_t)res);
993 }
994
__LDAEXH(volatile uint16_t * ptr)995 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
996 {
997 uint32_t res;
998 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
999 return ((uint16_t)res);
1000 }
1001
__LDAEX(volatile uint32_t * ptr)1002 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
1003 {
1004 uint32_t res;
1005 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
1006 return res;
1007 }
1008
__STLEXB(uint8_t value,volatile uint8_t * ptr)1009 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
1010 {
1011 uint32_t res;
1012 __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory");
1013 return res;
1014 }
1015
__STLEXH(uint16_t value,volatile uint16_t * ptr)1016 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
1017 {
1018 uint32_t res;
1019 __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory");
1020 return res;
1021 }
1022
__STLEX(uint32_t value,volatile uint32_t * ptr)1023 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
1024 {
1025 uint32_t res;
1026 __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory");
1027 return res;
1028 }
1029
1030 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
1031
1032 #undef __IAR_FT
1033 #undef __IAR_M0_FAMILY
1034 #undef __ICCARM_V8
1035
1036 #pragma diag_default=Pe940
1037 #pragma diag_default=Pe177
1038
1039 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1040
1041 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1042
1043 #endif /* __CMSIS_ICCARM_M_H__ */
1044
