1 /*
2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS-Core(M) Compiler LLVM/Clang Header File
21 */
22
23 #ifndef __CMSIS_CLANG_M_H
24 #define __CMSIS_CLANG_M_H
25
26 #pragma clang system_header /* treat file as system include file */
27
28 #ifndef __CMSIS_CLANG_H
29 #error "This file must not be included directly"
30 #endif
31
32 #if (__ARM_ACLE >= 200)
33 #include <arm_acle.h>
34 #else
35 #error Compiler must support ACLE V2.0
36 #endif /* (__ARM_ACLE >= 200) */
37
38 /* Fallback for __has_builtin */
39 #ifndef __has_builtin
40 #define __has_builtin(x) (0)
41 #endif
42
43
44 /* ######################### Startup and Lowlevel Init ######################## */
45 #ifndef __PROGRAM_START
46 #define __PROGRAM_START _start
47 #endif
48
49 #ifndef __INITIAL_SP
50 #define __INITIAL_SP __stack
51 #endif
52
53 #ifndef __STACK_LIMIT
54 #define __STACK_LIMIT __stack_limit
55 #endif
56
57 #ifndef __VECTOR_TABLE
58 #define __VECTOR_TABLE __Vectors
59 #endif
60
61 #ifndef __VECTOR_TABLE_ATTRIBUTE
62 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
63 #endif
64
65 #if (__ARM_FEATURE_CMSE == 3)
66 #ifndef __STACK_SEAL
67 #define __STACK_SEAL __stack_seal
68 #endif
69
70 #ifndef __TZ_STACK_SEAL_SIZE
71 #define __TZ_STACK_SEAL_SIZE 8U
72 #endif
73
74 #ifndef __TZ_STACK_SEAL_VALUE
75 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
76 #endif
77
78
__TZ_set_STACKSEAL_S(uint32_t * stackTop)79 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
80 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
81 }
82 #endif
83
84
85 #if (__ARM_ARCH_ISA_THUMB >= 2)
86 /**
87 \brief STRT Unprivileged (8 bit)
88 \details Executes a Unprivileged STRT instruction for 8 bit values.
89 \param [in] value Value to store
90 \param [in] ptr Pointer to location
91 */
__STRBT(uint8_t value,volatile uint8_t * ptr)92 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
93 {
94 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
95 }
96
97
98 /**
99 \brief STRT Unprivileged (16 bit)
100 \details Executes a Unprivileged STRT instruction for 16 bit values.
101 \param [in] value Value to store
102 \param [in] ptr Pointer to location
103 */
__STRHT(uint16_t value,volatile uint16_t * ptr)104 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
105 {
106 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
107 }
108
109
110 /**
111 \brief STRT Unprivileged (32 bit)
112 \details Executes a Unprivileged STRT instruction for 32 bit values.
113 \param [in] value Value to store
114 \param [in] ptr Pointer to location
115 */
__STRT(uint32_t value,volatile uint32_t * ptr)116 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
117 {
118 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
119 }
120 #endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
121
122 /* ########################### Core Function Access ########################### */
123 /** \ingroup CMSIS_Core_FunctionInterface
124 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
125 @{
126 */
127
128
129 /**
130 \brief Get Control Register
131 \details Returns the content of the Control Register.
132 \return Control Register value
133 */
__get_CONTROL(void)134 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
135 {
136 uint32_t result;
137
138 __ASM volatile ("MRS %0, control" : "=r" (result) );
139 return (result);
140 }
141
142
143 #if (__ARM_FEATURE_CMSE == 3)
144 /**
145 \brief Get Control Register (non-secure)
146 \details Returns the content of the non-secure Control Register when in secure mode.
147 \return non-secure Control Register value
148 */
__TZ_get_CONTROL_NS(void)149 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
150 {
151 uint32_t result;
152
153 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
154 return (result);
155 }
156 #endif
157
158
159 /**
160 \brief Set Control Register
161 \details Writes the given value to the Control Register.
162 \param [in] control Control Register value to set
163 */
__set_CONTROL(uint32_t control)164 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
165 {
166 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
167 __ISB();
168 }
169
170
171 #if (__ARM_FEATURE_CMSE == 3)
172 /**
173 \brief Set Control Register (non-secure)
174 \details Writes the given value to the non-secure Control Register when in secure state.
175 \param [in] control Control Register value to set
176 */
__TZ_set_CONTROL_NS(uint32_t control)177 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
178 {
179 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
180 __ISB();
181 }
182 #endif
183
184
185 /**
186 \brief Get IPSR Register
187 \details Returns the content of the IPSR Register.
188 \return IPSR Register value
189 */
__get_IPSR(void)190 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
191 {
192 uint32_t result;
193
194 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
195 return (result);
196 }
197
198
199 /**
200 \brief Get APSR Register
201 \details Returns the content of the APSR Register.
202 \return APSR Register value
203 */
__get_APSR(void)204 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
205 {
206 uint32_t result;
207
208 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
209 return (result);
210 }
211
212
213 /**
214 \brief Get xPSR Register
215 \details Returns the content of the xPSR Register.
216 \return xPSR Register value
217 */
__get_xPSR(void)218 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
219 {
220 uint32_t result;
221
222 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
223 return (result);
224 }
225
226
227 /**
228 \brief Get Process Stack Pointer
229 \details Returns the current value of the Process Stack Pointer (PSP).
230 \return PSP Register value
231 */
__get_PSP(void)232 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
233 {
234 uint32_t result;
235
236 __ASM volatile ("MRS %0, psp" : "=r" (result) );
237 return (result);
238 }
239
240
241 #if (__ARM_FEATURE_CMSE == 3)
242 /**
243 \brief Get Process Stack Pointer (non-secure)
244 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
245 \return PSP Register value
246 */
__TZ_get_PSP_NS(void)247 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
248 {
249 uint32_t result;
250
251 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
252 return (result);
253 }
254 #endif
255
256
257 /**
258 \brief Set Process Stack Pointer
259 \details Assigns the given value to the Process Stack Pointer (PSP).
260 \param [in] topOfProcStack Process Stack Pointer value to set
261 */
__set_PSP(uint32_t topOfProcStack)262 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
263 {
264 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
265 }
266
267
268 #if (__ARM_FEATURE_CMSE == 3)
269 /**
270 \brief Set Process Stack Pointer (non-secure)
271 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
272 \param [in] topOfProcStack Process Stack Pointer value to set
273 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)274 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
275 {
276 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
277 }
278 #endif
279
280
281 /**
282 \brief Get Main Stack Pointer
283 \details Returns the current value of the Main Stack Pointer (MSP).
284 \return MSP Register value
285 */
__get_MSP(void)286 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
287 {
288 uint32_t result;
289
290 __ASM volatile ("MRS %0, msp" : "=r" (result) );
291 return (result);
292 }
293
294
295 #if (__ARM_FEATURE_CMSE == 3)
296 /**
297 \brief Get Main Stack Pointer (non-secure)
298 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
299 \return MSP Register value
300 */
__TZ_get_MSP_NS(void)301 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
302 {
303 uint32_t result;
304
305 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
306 return (result);
307 }
308 #endif
309
310
311 /**
312 \brief Set Main Stack Pointer
313 \details Assigns the given value to the Main Stack Pointer (MSP).
314 \param [in] topOfMainStack Main Stack Pointer value to set
315 */
__set_MSP(uint32_t topOfMainStack)316 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
317 {
318 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
319 }
320
321
322 #if (__ARM_FEATURE_CMSE == 3)
323 /**
324 \brief Set Main Stack Pointer (non-secure)
325 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
326 \param [in] topOfMainStack Main Stack Pointer value to set
327 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)328 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
329 {
330 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
331 }
332 #endif
333
334
335 #if (__ARM_FEATURE_CMSE == 3)
336 /**
337 \brief Get Stack Pointer (non-secure)
338 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
339 \return SP Register value
340 */
__TZ_get_SP_NS(void)341 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
342 {
343 uint32_t result;
344
345 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
346 return (result);
347 }
348
349
350 /**
351 \brief Set Stack Pointer (non-secure)
352 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
353 \param [in] topOfStack Stack Pointer value to set
354 */
__TZ_set_SP_NS(uint32_t topOfStack)355 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
356 {
357 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
358 }
359 #endif
360
361
362 /**
363 \brief Get Priority Mask
364 \details Returns the current state of the priority mask bit from the Priority Mask Register.
365 \return Priority Mask value
366 */
__get_PRIMASK(void)367 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
368 {
369 uint32_t result;
370
371 __ASM volatile ("MRS %0, primask" : "=r" (result) );
372 return (result);
373 }
374
375
376 #if (__ARM_FEATURE_CMSE == 3)
377 /**
378 \brief Get Priority Mask (non-secure)
379 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
380 \return Priority Mask value
381 */
__TZ_get_PRIMASK_NS(void)382 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
383 {
384 uint32_t result;
385
386 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
387 return (result);
388 }
389 #endif
390
391
392 /**
393 \brief Set Priority Mask
394 \details Assigns the given value to the Priority Mask Register.
395 \param [in] priMask Priority Mask
396 */
__set_PRIMASK(uint32_t priMask)397 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
398 {
399 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
400 }
401
402
403 #if (__ARM_FEATURE_CMSE == 3)
404 /**
405 \brief Set Priority Mask (non-secure)
406 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
407 \param [in] priMask Priority Mask
408 */
__TZ_set_PRIMASK_NS(uint32_t priMask)409 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
410 {
411 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
412 }
413 #endif
414
415
416 #if (__ARM_ARCH_ISA_THUMB >= 2)
417 /**
418 \brief Get Base Priority
419 \details Returns the current value of the Base Priority register.
420 \return Base Priority register value
421 */
__get_BASEPRI(void)422 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
423 {
424 uint32_t result;
425
426 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
427 return (result);
428 }
429
430
431 #if (__ARM_FEATURE_CMSE == 3)
432 /**
433 \brief Get Base Priority (non-secure)
434 \details Returns the current value of the non-secure Base Priority register when in secure state.
435 \return Base Priority register value
436 */
__TZ_get_BASEPRI_NS(void)437 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
438 {
439 uint32_t result;
440
441 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
442 return (result);
443 }
444 #endif
445
446
447 /**
448 \brief Set Base Priority
449 \details Assigns the given value to the Base Priority register.
450 \param [in] basePri Base Priority value to set
451 */
__set_BASEPRI(uint32_t basePri)452 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
453 {
454 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
455 }
456
457
458 #if (__ARM_FEATURE_CMSE == 3)
459 /**
460 \brief Set Base Priority (non-secure)
461 \details Assigns the given value to the non-secure Base Priority register when in secure state.
462 \param [in] basePri Base Priority value to set
463 */
__TZ_set_BASEPRI_NS(uint32_t basePri)464 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
465 {
466 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
467 }
468 #endif
469
470
471 /**
472 \brief Set Base Priority with condition
473 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
474 or the new value increases the BASEPRI priority level.
475 \param [in] basePri Base Priority value to set
476 */
__set_BASEPRI_MAX(uint32_t basePri)477 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
478 {
479 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
480 }
481
482
483 /**
484 \brief Get Fault Mask
485 \details Returns the current value of the Fault Mask register.
486 \return Fault Mask register value
487 */
__get_FAULTMASK(void)488 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
489 {
490 uint32_t result;
491
492 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
493 return (result);
494 }
495
496
497 #if (__ARM_FEATURE_CMSE == 3)
498 /**
499 \brief Get Fault Mask (non-secure)
500 \details Returns the current value of the non-secure Fault Mask register when in secure state.
501 \return Fault Mask register value
502 */
__TZ_get_FAULTMASK_NS(void)503 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
504 {
505 uint32_t result;
506
507 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
508 return (result);
509 }
510 #endif
511
512
513 /**
514 \brief Set Fault Mask
515 \details Assigns the given value to the Fault Mask register.
516 \param [in] faultMask Fault Mask value to set
517 */
__set_FAULTMASK(uint32_t faultMask)518 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
519 {
520 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
521 }
522
523
524 #if (__ARM_FEATURE_CMSE == 3)
525 /**
526 \brief Set Fault Mask (non-secure)
527 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
528 \param [in] faultMask Fault Mask value to set
529 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)530 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
531 {
532 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
533 }
534 #endif
535
536 #endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
537
538
539 #if (__ARM_ARCH >= 8)
540 /**
541 \brief Get Process Stack Pointer Limit
542 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
543 Stack Pointer Limit register hence zero is returned always in non-secure
544 mode.
545
546 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
547 \return PSPLIM Register value
548 */
__get_PSPLIM(void)549 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
550 {
551 #if (((__ARM_ARCH_8M_MAIN__ < 1) && \
552 (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
553 (__ARM_FEATURE_CMSE < 3) )
554 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
555 return (0U);
556 #else
557 uint32_t result;
558 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
559 return (result);
560 #endif
561 }
562
563 #if (__ARM_FEATURE_CMSE == 3)
564 /**
565 \brief Get Process Stack Pointer Limit (non-secure)
566 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
567 Stack Pointer Limit register hence zero is returned always.
568
569 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
570 \return PSPLIM Register value
571 */
__TZ_get_PSPLIM_NS(void)572 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
573 {
574 #if ((__ARM_ARCH_8M_MAIN__ < 1) && \
575 (__ARM_ARCH_8_1M_MAIN__ < 1) )
576 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
577 return (0U);
578 #else
579 uint32_t result;
580 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
581 return (result);
582 #endif
583 }
584 #endif
585
586
587 /**
588 \brief Set Process Stack Pointer Limit
589 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
590 Stack Pointer Limit register hence the write is silently ignored in non-secure
591 mode.
592
593 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
594 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
595 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)596 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
597 {
598 #if (((__ARM_ARCH_8M_MAIN__ < 1) && \
599 (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
600 (__ARM_FEATURE_CMSE < 3) )
601 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
602 (void)ProcStackPtrLimit;
603 #else
604 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
605 #endif
606 }
607
608
609 #if (__ARM_FEATURE_CMSE == 3)
610 /**
611 \brief Set Process Stack Pointer (non-secure)
612 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
613 Stack Pointer Limit register hence the write is silently ignored.
614
615 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
616 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
617 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)618 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
619 {
620 #if ((__ARM_ARCH_8M_MAIN__ < 1) && \
621 (__ARM_ARCH_8_1M_MAIN__ < 1) )
622 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
623 (void)ProcStackPtrLimit;
624 #else
625 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
626 #endif
627 }
628 #endif
629
630
631 /**
632 \brief Get Main Stack Pointer Limit
633 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
634 Stack Pointer Limit register hence zero is returned always.
635
636 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
637 \return MSPLIM Register value
638 */
__get_MSPLIM(void)639 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
640 {
641 #if (((__ARM_ARCH_8M_MAIN__ < 1) && \
642 (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
643 (__ARM_FEATURE_CMSE < 3) )
644 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
645 return (0U);
646 #else
647 uint32_t result;
648 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
649 return (result);
650 #endif
651 }
652
653
654 #if (__ARM_FEATURE_CMSE == 3)
655 /**
656 \brief Get Main Stack Pointer Limit (non-secure)
657 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
658 Stack Pointer Limit register hence zero is returned always.
659
660 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
661 \return MSPLIM Register value
662 */
__TZ_get_MSPLIM_NS(void)663 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
664 {
665 #if ((__ARM_ARCH_8M_MAIN__ < 1) && \
666 (__ARM_ARCH_8_1M_MAIN__ < 1) )
667 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
668 return (0U);
669 #else
670 uint32_t result;
671 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
672 return (result);
673 #endif
674 }
675 #endif
676
677
678 /**
679 \brief Set Main Stack Pointer Limit
680 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
681 Stack Pointer Limit register hence the write is silently ignored.
682
683 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
684 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
685 */
__set_MSPLIM(uint32_t MainStackPtrLimit)686 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
687 {
688 #if (((__ARM_ARCH_8M_MAIN__ < 1) && \
689 (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
690 (__ARM_FEATURE_CMSE < 3) )
691 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
692 (void)MainStackPtrLimit;
693 #else
694 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
695 #endif
696 }
697
698
699 #if (__ARM_FEATURE_CMSE == 3)
700 /**
701 \brief Set Main Stack Pointer Limit (non-secure)
702 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
703 Stack Pointer Limit register hence the write is silently ignored.
704
705 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
706 \param [in] MainStackPtrLimit Main Stack Pointer value to set
707 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)708 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
709 {
710 #if ((__ARM_ARCH_8M_MAIN__ < 1) && \
711 (__ARM_ARCH_8_1M_MAIN__ < 1) )
712 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
713 (void)MainStackPtrLimit;
714 #else
715 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
716 #endif
717 }
718 #endif
719
720 #endif /* (__ARM_ARCH >= 8) */
721
722 /* ################### Compiler specific Intrinsics ########################### */
723 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
724 Access to dedicated SIMD instructions
725 @{
726 */
727 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
728 #define __SADD8 __sadd8
729 #define __QADD8 __qadd8
730 #define __SHADD8 __shadd8
731 #define __UADD8 __uadd8
732 #define __UQADD8 __uqadd8
733 #define __UHADD8 __uhadd8
734 #define __SSUB8 __ssub8
735 #define __QSUB8 __qsub8
736 #define __SHSUB8 __shsub8
737 #define __USUB8 __usub8
738 #define __UQSUB8 __uqsub8
739 #define __UHSUB8 __uhsub8
740 #define __SADD16 __sadd16
741 #define __QADD16 __qadd16
742 #define __SHADD16 __shadd16
743 #define __UADD16 __uadd16
744 #define __UQADD16 __uqadd16
745 #define __UHADD16 __uhadd16
746 #define __SSUB16 __ssub16
747 #define __QSUB16 __qsub16
748 #define __SHSUB16 __shsub16
749 #define __USUB16 __usub16
750 #define __UQSUB16 __uqsub16
751 #define __UHSUB16 __uhsub16
752 #define __SASX __sasx
753 #define __QASX __qasx
754 #define __SHASX __shasx
755 #define __UASX __uasx
756 #define __UQASX __uqasx
757 #define __UHASX __uhasx
758 #define __SSAX __ssax
759 #define __QSAX __qsax
760 #define __SHSAX __shsax
761 #define __USAX __usax
762 #define __UQSAX __uqsax
763 #define __UHSAX __uhsax
764 #define __USAD8 __usad8
765 #define __USADA8 __usada8
766 #define __SSAT16 __ssat16
767 #define __USAT16 __usat16
768 #define __UXTB16 __uxtb16
769 #define __UXTAB16 __uxtab16
770 #define __SXTB16 __sxtb16
771 #define __SXTAB16 __sxtab16
772 #define __SMUAD __smuad
773 #define __SMUADX __smuadx
774 #define __SMLAD __smlad
775 #define __SMLADX __smladx
776 #define __SMLALD __smlald
777 #define __SMLALDX __smlaldx
778 #define __SMUSD __smusd
779 #define __SMUSDX __smusdx
780 #define __SMLSD __smlsd
781 #define __SMLSDX __smlsdx
782 #define __SMLSLD __smlsld
783 #define __SMLSLDX __smlsldx
784 #define __SEL __sel
785 #define __QADD __qadd
786 #define __QSUB __qsub
787
788 #define __PKHBT(ARG1,ARG2,ARG3) \
789 __extension__ \
790 ({ \
791 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
792 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
793 __RES; \
794 })
795
796 #define __PKHTB(ARG1,ARG2,ARG3) \
797 __extension__ \
798 ({ \
799 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
800 if (ARG3 == 0) \
801 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
802 else \
803 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
804 __RES; \
805 })
806
807 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
808
809 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
810
__SMMLA(int32_t op1,int32_t op2,int32_t op3)811 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
812 {
813 int32_t result;
814
815 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
816 return (result);
817 }
818
819 #endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
820 /** @} end of group CMSIS_SIMD_intrinsics */
821 /** @} end of CMSIS_Core_RegAccFunctions */
822
823
824 #endif /* __CMSIS_CLANG_M_H */
825
