1 /**************************************************************************//**
2 * @file cmsis_clang.h
3 * @brief CMSIS compiler LLVM/Clang header file
4 * @version V6.0.0
5 * @date 27. July 2024
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_CLANG_H
26 #define __CMSIS_CLANG_H
27
28 #pragma clang system_header /* treat file as system include file */
29
30 #if (__ARM_ACLE >= 200)
31 #include <arm_acle.h>
32 #else
33 #error Compiler must support ACLE V2.0
34 #endif /* (__ARM_ACLE >= 200) */
35
36 /* Fallback for __has_builtin */
37 #ifndef __has_builtin
38 #define __has_builtin(x) (0)
39 #endif
40
41 /* CMSIS compiler specific defines */
42 #ifndef __ASM
43 #define __ASM __asm
44 #endif
45 #ifndef __INLINE
46 #define __INLINE inline
47 #endif
48 #ifndef __STATIC_INLINE
49 #define __STATIC_INLINE static inline
50 #endif
51 #ifndef __STATIC_FORCEINLINE
52 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
53 #endif
54 #ifndef __NO_RETURN
55 #define __NO_RETURN __attribute__((__noreturn__))
56 #endif
57 #ifndef CMSIS_DEPRECATED
58 #define CMSIS_DEPRECATED __attribute__((deprecated))
59 #endif
60 #ifndef __USED
61 #define __USED __attribute__((used))
62 #endif
63 #ifndef __WEAK
64 #define __WEAK __attribute__((weak))
65 #endif
66 #ifndef __PACKED
67 #define __PACKED __attribute__((packed, aligned(1)))
68 #endif
69 #ifndef __PACKED_STRUCT
70 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
71 #endif
72 #ifndef __PACKED_UNION
73 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
74 #endif
75 #ifndef __UNALIGNED_UINT16_WRITE
76 #pragma clang diagnostic push
77 #pragma clang diagnostic ignored "-Wpacked"
78 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
79 #pragma clang diagnostic pop
80 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
81 #endif
82 #ifndef __UNALIGNED_UINT16_READ
83 #pragma clang diagnostic push
84 #pragma clang diagnostic ignored "-Wpacked"
85 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
86 #pragma clang diagnostic pop
87 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
88 #endif
89 #ifndef __UNALIGNED_UINT32_WRITE
90 #pragma clang diagnostic push
91 #pragma clang diagnostic ignored "-Wpacked"
92 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
93 #pragma clang diagnostic pop
94 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
95 #endif
96 #ifndef __UNALIGNED_UINT32_READ
97 #pragma clang diagnostic push
98 #pragma clang diagnostic ignored "-Wpacked"
99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
100 #pragma clang diagnostic pop
101 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
102 #endif
103 #ifndef __ALIGNED
104 #define __ALIGNED(x) __attribute__((aligned(x)))
105 #endif
106 #ifndef __RESTRICT
107 #define __RESTRICT __restrict
108 #endif
109 #ifndef __COMPILER_BARRIER
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
111 #endif
112 #ifndef __NO_INIT
113 #define __NO_INIT __attribute__ ((section (".noinit")))
114 #endif
115 #ifndef __ALIAS
116 #define __ALIAS(x) __attribute__ ((alias(x)))
117 #endif
118
119 /* ########################## Core Instruction Access ######################### */
120 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
121 Access to dedicated instructions
122 @{
123 */
124
125 /* Define macros for porting to both thumb1 and thumb2.
126 * For thumb1, use low register (r0-r7), specified by constraint "l"
127 * Otherwise, use general registers, specified by constraint "r" */
128 #if defined (__thumb__) && !defined (__thumb2__)
129 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
130 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
131 #define __CMSIS_GCC_USE_REG(r) "l" (r)
132 #else
133 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
134 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
135 #define __CMSIS_GCC_USE_REG(r) "r" (r)
136 #endif
137
138 /**
139 \brief No Operation
140 \details No Operation does nothing. This instruction can be used for code alignment purposes.
141 */
142 #define __NOP() __nop()
143
144
145 /**
146 \brief Wait For Interrupt
147 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
148 */
149 #define __WFI() __wfi()
150
151
152 /**
153 \brief Wait For Event
154 \details Wait For Event is a hint instruction that permits the processor to enter
155 a low-power state until one of a number of events occurs.
156 */
157 #define __WFE() __wfe()
158
159
160 /**
161 \brief Send Event
162 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
163 */
164 #define __SEV() __sev()
165
166
167 /**
168 \brief Instruction Synchronization Barrier
169 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
170 so that all instructions following the ISB are fetched from cache or memory,
171 after the instruction has been completed.
172 */
173 #define __ISB() __isb(0xF)
174
175
176 /**
177 \brief Data Synchronization Barrier
178 \details Acts as a special kind of Data Memory Barrier.
179 It completes when all explicit memory accesses before this instruction complete.
180 */
181 #define __DSB() __dsb(0xF)
182
183
184 /**
185 \brief Data Memory Barrier
186 \details Ensures the apparent order of the explicit memory operations before
187 and after the instruction, without ensuring their completion.
188 */
189 #define __DMB() __dmb(0xF)
190
191
192 /**
193 \brief Reverse byte order (32 bit)
194 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
195 \param [in] value Value to reverse
196 \return Reversed value
197 */
198 #define __REV(value) __rev(value)
199
200
201 /**
202 \brief Reverse byte order (16 bit)
203 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
204 \param [in] value Value to reverse
205 \return Reversed value
206 */
207 #define __REV16(value) __rev16(value)
208
209
210 /**
211 \brief Reverse byte order (16 bit)
212 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
213 \param [in] value Value to reverse
214 \return Reversed value
215 */
216 #define __REVSH(value) __revsh(value)
217
218
219 /**
220 \brief Rotate Right in unsigned value (32 bit)
221 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
222 \param [in] op1 Value to rotate
223 \param [in] op2 Number of Bits to rotate
224 \return Rotated value
225 */
226 #define __ROR(op1, op2) __ror(op1, op2)
227
228
229 /**
230 \brief Breakpoint
231 \details Causes the processor to enter Debug state.
232 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
233 \param [in] value is ignored by the processor.
234 If required, a debugger can use it to store additional information about the breakpoint.
235 */
236 #define __BKPT(value) __ASM volatile ("bkpt "#value)
237
238
239 /**
240 \brief Reverse bit order of value
241 \details Reverses the bit order of the given value.
242 \param [in] value Value to reverse
243 \return Reversed value
244 */
245 #define __RBIT(value) __rbit(value)
246
247
248 /**
249 \brief Count leading zeros
250 \details Counts the number of leading zeros of a data value.
251 \param [in] value Value to count the leading zeros
252 \return number of leading zeros in value
253 */
254 #define __CLZ(value) __clz(value)
255
256
257 #if ((__ARM_FEATURE_SAT >= 1) && \
258 (__ARM_ARCH_ISA_THUMB >= 2) )
259 /* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */
260 /**
261 \brief Signed Saturate
262 \details Saturates a signed value.
263 \param [in] value Value to be saturated
264 \param [in] sat Bit position to saturate to (1..32)
265 \return Saturated value
266 */
267 #define __SSAT(value, sat) __ssat(value, sat)
268
269
270 /**
271 \brief Unsigned Saturate
272 \details Saturates an unsigned value.
273 \param [in] value Value to be saturated
274 \param [in] sat Bit position to saturate to (0..31)
275 \return Saturated value
276 */
277 #define __USAT(value, sat) __usat(value, sat)
278
279 #else /* (__ARM_FEATURE_SAT >= 1) */
280 /**
281 \brief Signed Saturate
282 \details Saturates a signed value.
283 \param [in] value Value to be saturated
284 \param [in] sat Bit position to saturate to (1..32)
285 \return Saturated value
286 */
__SSAT(int32_t val,uint32_t sat)287 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
288 {
289 if ((sat >= 1U) && (sat <= 32U))
290 {
291 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
292 const int32_t min = -1 - max ;
293 if (val > max)
294 {
295 return (max);
296 }
297 else if (val < min)
298 {
299 return (min);
300 }
301 }
302 return (val);
303 }
304
305
306 /**
307 \brief Unsigned Saturate
308 \details Saturates an unsigned value.
309 \param [in] value Value to be saturated
310 \param [in] sat Bit position to saturate to (0..31)
311 \return Saturated value
312 */
__USAT(int32_t val,uint32_t sat)313 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
314 {
315 if (sat <= 31U)
316 {
317 const uint32_t max = ((1U << sat) - 1U);
318 if (val > (int32_t)max)
319 {
320 return (max);
321 }
322 else if (val < 0)
323 {
324 return (0U);
325 }
326 }
327 return ((uint32_t)val);
328 }
329 #endif /* (__ARM_FEATURE_SAT >= 1) */
330
331
332 #if (__ARM_FEATURE_LDREX >= 1)
333 /**
334 \brief Remove the exclusive lock
335 \details Removes the exclusive lock which is created by LDREX.
336 */
337 #define __CLREX __builtin_arm_clrex
338
339
340 /**
341 \brief LDR Exclusive (8 bit)
342 \details Executes a exclusive LDR instruction for 8 bit value.
343 \param [in] ptr Pointer to data
344 \return value of type uint8_t at (*ptr)
345 */
346 #define __LDREXB (uint8_t)__builtin_arm_ldrex
347
348
349 /**
350 \brief STR Exclusive (8 bit)
351 \details Executes a exclusive STR instruction for 8 bit values.
352 \param [in] value Value to store
353 \param [in] ptr Pointer to location
354 \return 0 Function succeeded
355 \return 1 Function failed
356 */
357 #define __STREXB (uint32_t)__builtin_arm_strex
358 #endif /* (__ARM_FEATURE_LDREX >= 1) */
359
360
361 #if (__ARM_FEATURE_LDREX >= 2)
362 /**
363 \brief LDR Exclusive (16 bit)
364 \details Executes a exclusive LDR instruction for 16 bit values.
365 \param [in] ptr Pointer to data
366 \return value of type uint16_t at (*ptr)
367 */
368 #define __LDREXH (uint16_t)__builtin_arm_ldrex
369
370
371 /**
372 \brief STR Exclusive (16 bit)
373 \details Executes a exclusive STR instruction for 16 bit values.
374 \param [in] value Value to store
375 \param [in] ptr Pointer to location
376 \return 0 Function succeeded
377 \return 1 Function failed
378 */
379 #define __STREXH (uint32_t)__builtin_arm_strex
380 #endif /* (__ARM_FEATURE_LDREX >= 2) */
381
382
383 #if (__ARM_FEATURE_LDREX >= 4)
384 /**
385 \brief LDR Exclusive (32 bit)
386 \details Executes a exclusive LDR instruction for 32 bit values.
387 \param [in] ptr Pointer to data
388 \return value of type uint32_t at (*ptr)
389 */
390 #define __LDREXW (uint32_t)__builtin_arm_ldrex
391
392
393 /**
394 \brief STR Exclusive (32 bit)
395 \details Executes a exclusive STR instruction for 32 bit values.
396 \param [in] value Value to store
397 \param [in] ptr Pointer to location
398 \return 0 Function succeeded
399 \return 1 Function failed
400 */
401 #define __STREXW (uint32_t)__builtin_arm_strex
402 #endif /* (__ARM_FEATURE_LDREX >= 4) */
403
404
405 #if (__ARM_ARCH_ISA_THUMB >= 2)
406 /**
407 \brief Rotate Right with Extend (32 bit)
408 \details Moves each bit of a bitstring right by one bit.
409 The carry input is shifted in at the left end of the bitstring.
410 \param [in] value Value to rotate
411 \return Rotated value
412 */
__RRX(uint32_t value)413 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
414 {
415 uint32_t result;
416
417 __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
418 return (result);
419 }
420
421
422 /**
423 \brief LDRT Unprivileged (8 bit)
424 \details Executes a Unprivileged LDRT instruction for 8 bit value.
425 \param [in] ptr Pointer to data
426 \return value of type uint8_t at (*ptr)
427 */
__LDRBT(volatile uint8_t * ptr)428 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
429 {
430 uint32_t result;
431
432 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
433 return ((uint8_t)result); /* Add explicit type cast here */
434 }
435
436
437 /**
438 \brief LDRT Unprivileged (16 bit)
439 \details Executes a Unprivileged LDRT instruction for 16 bit values.
440 \param [in] ptr Pointer to data
441 \return value of type uint16_t at (*ptr)
442 */
__LDRHT(volatile uint16_t * ptr)443 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
444 {
445 uint32_t result;
446
447 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
448 return ((uint16_t)result); /* Add explicit type cast here */
449 }
450
451
452 /**
453 \brief LDRT Unprivileged (32 bit)
454 \details Executes a Unprivileged LDRT instruction for 32 bit values.
455 \param [in] ptr Pointer to data
456 \return value of type uint32_t at (*ptr)
457 */
__LDRT(volatile uint32_t * ptr)458 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
459 {
460 uint32_t result;
461
462 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
463 return (result);
464 }
465 #endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
466
467
468 #if (__ARM_ARCH >= 8)
469 /**
470 \brief Load-Acquire (8 bit)
471 \details Executes a LDAB instruction for 8 bit value.
472 \param [in] ptr Pointer to data
473 \return value of type uint8_t at (*ptr)
474 */
__LDAB(volatile uint8_t * ptr)475 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
476 {
477 uint32_t result;
478
479 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
480 return ((uint8_t)result); /* Add explicit type cast here */
481 }
482
483
484 /**
485 \brief Load-Acquire (16 bit)
486 \details Executes a LDAH instruction for 16 bit values.
487 \param [in] ptr Pointer to data
488 \return value of type uint16_t at (*ptr)
489 */
__LDAH(volatile uint16_t * ptr)490 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
491 {
492 uint32_t result;
493
494 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
495 return ((uint16_t)result); /* Add explicit type cast here */
496 }
497
498
499 /**
500 \brief Load-Acquire (32 bit)
501 \details Executes a LDA instruction for 32 bit values.
502 \param [in] ptr Pointer to data
503 \return value of type uint32_t at (*ptr)
504 */
__LDA(volatile uint32_t * ptr)505 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
506 {
507 uint32_t result;
508
509 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
510 return (result);
511 }
512
513
514 /**
515 \brief Store-Release (8 bit)
516 \details Executes a STLB instruction for 8 bit values.
517 \param [in] value Value to store
518 \param [in] ptr Pointer to location
519 */
__STLB(uint8_t value,volatile uint8_t * ptr)520 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
521 {
522 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
523 }
524
525
526 /**
527 \brief Store-Release (16 bit)
528 \details Executes a STLH instruction for 16 bit values.
529 \param [in] value Value to store
530 \param [in] ptr Pointer to location
531 */
__STLH(uint16_t value,volatile uint16_t * ptr)532 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
533 {
534 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
535 }
536
537
538 /**
539 \brief Store-Release (32 bit)
540 \details Executes a STL instruction for 32 bit values.
541 \param [in] value Value to store
542 \param [in] ptr Pointer to location
543 */
__STL(uint32_t value,volatile uint32_t * ptr)544 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
545 {
546 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
547 }
548
549
550 /**
551 \brief Load-Acquire Exclusive (8 bit)
552 \details Executes a LDAB exclusive instruction for 8 bit value.
553 \param [in] ptr Pointer to data
554 \return value of type uint8_t at (*ptr)
555 */
556 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
557
558
559 /**
560 \brief Load-Acquire Exclusive (16 bit)
561 \details Executes a LDAH exclusive instruction for 16 bit values.
562 \param [in] ptr Pointer to data
563 \return value of type uint16_t at (*ptr)
564 */
565 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
566
567
568 /**
569 \brief Load-Acquire Exclusive (32 bit)
570 \details Executes a LDA exclusive instruction for 32 bit values.
571 \param [in] ptr Pointer to data
572 \return value of type uint32_t at (*ptr)
573 */
574 #define __LDAEX (uint32_t)__builtin_arm_ldaex
575
576
577 /**
578 \brief Store-Release Exclusive (8 bit)
579 \details Executes a STLB exclusive instruction for 8 bit values.
580 \param [in] value Value to store
581 \param [in] ptr Pointer to location
582 \return 0 Function succeeded
583 \return 1 Function failed
584 */
585 #define __STLEXB (uint32_t)__builtin_arm_stlex
586
587
588 /**
589 \brief Store-Release Exclusive (16 bit)
590 \details Executes a STLH exclusive instruction for 16 bit values.
591 \param [in] value Value to store
592 \param [in] ptr Pointer to location
593 \return 0 Function succeeded
594 \return 1 Function failed
595 */
596 #define __STLEXH (uint32_t)__builtin_arm_stlex
597
598
599 /**
600 \brief Store-Release Exclusive (32 bit)
601 \details Executes a STL exclusive instruction for 32 bit values.
602 \param [in] value Value to store
603 \param [in] ptr Pointer to location
604 \return 0 Function succeeded
605 \return 1 Function failed
606 */
607 #define __STLEX (uint32_t)__builtin_arm_stlex
608
609 #endif /* (__ARM_ARCH >= 8) */
610
611 /** @}*/ /* end of group CMSIS_Core_InstructionInterface */
612
613
614 /* ########################### Core Function Access ########################### */
615 /** \ingroup CMSIS_Core_FunctionInterface
616 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
617 @{
618 */
619
620 /**
621 \brief Enable IRQ Interrupts
622 \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
623 Can only be executed in Privileged modes.
624 */
__enable_irq(void)625 __STATIC_FORCEINLINE void __enable_irq(void)
626 {
627 __ASM volatile ("cpsie i" : : : "memory");
628 }
629
630
631 /**
632 \brief Disable IRQ Interrupts
633 \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
634 Can only be executed in Privileged modes.
635 */
__disable_irq(void)636 __STATIC_FORCEINLINE void __disable_irq(void)
637 {
638 __ASM volatile ("cpsid i" : : : "memory");
639 }
640
641 #if (__ARM_ARCH_ISA_THUMB >= 2)
642 /**
643 \brief Enable FIQ
644 \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
645 Can only be executed in Privileged modes.
646 */
__enable_fault_irq(void)647 __STATIC_FORCEINLINE void __enable_fault_irq(void)
648 {
649 __ASM volatile ("cpsie f" : : : "memory");
650 }
651
652
653 /**
654 \brief Disable FIQ
655 \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
656 Can only be executed in Privileged modes.
657 */
__disable_fault_irq(void)658 __STATIC_FORCEINLINE void __disable_fault_irq(void)
659 {
660 __ASM volatile ("cpsid f" : : : "memory");
661 }
662 #endif
663
664
665
666 /**
667 \brief Get FPSCR
668 \details Returns the current value of the Floating Point Status/Control register.
669 \return Floating Point Status/Control register value
670 */
__get_FPSCR(void)671 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
672 {
673 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
674 return (__builtin_arm_get_fpscr());
675 #else
676 return (0U);
677 #endif
678 }
679
680
681 /**
682 \brief Set FPSCR
683 \details Assigns the given value to the Floating Point Status/Control register.
684 \param [in] fpscr Floating Point Status/Control value to set
685 */
__set_FPSCR(uint32_t fpscr)686 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
687 {
688 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
689 __builtin_arm_set_fpscr(fpscr);
690 #else
691 (void)fpscr;
692 #endif
693 }
694
695 /** @} end of CMSIS_Core_RegAccFunctions */
696
697 // Include the profile specific settings:
698 #if __ARM_ARCH_PROFILE == 'A'
699 #include "./a-profile/cmsis_clang_a.h"
700 #elif __ARM_ARCH_PROFILE == 'R'
701 #include "./r-profile/cmsis_clang_r.h"
702 #elif __ARM_ARCH_PROFILE == 'M'
703 #include "./m-profile/cmsis_clang_m.h"
704 #else
705 #error "Unknown Arm architecture profile"
706 #endif
707
708 #endif /* __CMSIS_CLANG_H */
709
