1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WLxx_LL_DAC_H
21 #define STM32WLxx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
58
59 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
60 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
61
62 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
63 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
64 DHR12Rx channel 1 (shifted left of 20 bits) */
65 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
66 DHR12Rx channel 1 (shifted left of 24 bits) */
67 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
68 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
69 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
70 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
71 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
72
73 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
74 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
75 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
76 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET)
77
78
79 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
80 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
81 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
82 to position 0 */
83 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
84 to position 0 */
85
86 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
87 channel 1 or 2 versus DHR12Rx channel 1
88 (shifted left of 28 bits) */
89 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
90 channel 1 or 2 versus DHR12Rx channel 1
91 (shifted left of 20 bits) */
92 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
93 channel 1 or 2 versus DHR12Rx channel 1
94 (shifted left of 24 bits) */
95 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
96 channel 1 or 2 versus DORx channel 1
97 (shifted left of 5 bits) */
98 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
99 channel 1 or 2 versus SHSRx channel 1
100 (shifted left of 6 bits) */
101
102 /* Miscellaneous data */
103 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
104 bits (voltage range determined by analog voltage
105 references Vref+ and Vref-, refer to reference manual) */
106
107 /**
108 * @}
109 */
110
111
112 /* Private macros ------------------------------------------------------------*/
113 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
114 * @{
115 */
116
117 /**
118 * @brief Driver macro reserved for internal use: set a pointer to
119 * a register from a register basis from which an offset
120 * is applied.
121 * @param __REG__ Register basis from which the offset is applied.
122 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
123 * @retval Pointer to register address
124 */
125 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
126 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
127
128 /**
129 * @}
130 */
131
132
133 /* Exported types ------------------------------------------------------------*/
134 #if defined(USE_FULL_LL_DRIVER)
135 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
136 * @{
137 */
138
139 /**
140 * @brief Structure definition of some features of DAC instance.
141 */
142 typedef struct
143 {
144 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
145 internal (SW start) or from external peripheral
146 (timer event, external interrupt line).
147 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
148
149 This feature can be modified afterwards using unitary
150 function @ref LL_DAC_SetTriggerSource(). */
151
152 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
153 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
154
155 This feature can be modified afterwards using unitary
156 function @ref LL_DAC_SetWaveAutoGeneration(). */
157
158 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
159 If waveform automatic generation mode is set to noise, this parameter
160 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
161 If waveform automatic generation mode is set to triangle,
162 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
163 @note If waveform automatic generation mode is disabled,
164 this parameter is discarded.
165
166 This feature can be modified afterwards using unitary
167 function @ref LL_DAC_SetWaveNoiseLFSR(),
168 @ref LL_DAC_SetWaveTriangleAmplitude()
169 depending on the wave automatic generation selected. */
170
171 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
172 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
173
174 This feature can be modified afterwards using unitary
175 function @ref LL_DAC_SetOutputBuffer(). */
176
177 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
178 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
179
180 This feature can be modified afterwards using unitary
181 function @ref LL_DAC_SetOutputConnection(). */
182
183 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
184 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
185
186 This feature can be modified afterwards using unitary
187 function @ref LL_DAC_SetOutputMode(). */
188 } LL_DAC_InitTypeDef;
189
190 /**
191 * @}
192 */
193 #endif /* USE_FULL_LL_DRIVER */
194
195 /* Exported constants --------------------------------------------------------*/
196 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
197 * @{
198 */
199
200 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
201 * @brief Flags defines which can be used with LL_DAC_ReadReg function
202 * @{
203 */
204 /* DAC channel 1 flags */
205 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
206 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
207 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
208 /**
209 * @}
210 */
211
212 /** @defgroup DAC_LL_EC_IT DAC interruptions
213 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
214 * @{
215 */
216 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
217 /**
218 * @}
219 */
220
221 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
222 * @{
223 */
224 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
225 /**
226 * @}
227 */
228
229 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
230 * @{
231 */
232 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
233 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
234 /**
235 * @}
236 */
237
238 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
239 * @{
240 */
241 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC channel conversion trigger internal (SW start) */
242 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
244 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */
245 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */
246 #define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM3 TRGO. */
247 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
248 /**
249 * @}
250 */
251
252 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
253 * @{
254 */
255 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
256 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
257 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
258 /**
259 * @}
260 */
261
262 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
263 * @{
264 */
265 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
266 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
267 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
277 /**
278 * @}
279 */
280
281 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
282 * @{
283 */
284 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
285 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
286 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
295 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
296 /**
297 * @}
298 */
299
300 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
301 * @{
302 */
303 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
304 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
305 /**
306 * @}
307 */
308
309 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
310 * @{
311 */
312 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
313 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
314 /**
315 * @}
316 */
317
318 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
319 * @{
320 */
321 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
322 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
323 /**
324 * @}
325 */
326
327 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
328 * @{
329 */
330 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
331 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
332 /**
333 * @}
334 */
335
336 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
337 * @{
338 */
339 /* List of DAC registers intended to be used (most commonly) with */
340 /* DMA transfer. */
341 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
342 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
343 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
344 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
345 /**
346 * @}
347 */
348
349 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
350 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
351 * not timeout values.
352 * For details on delays values, refer to descriptions in source code
353 * above each literal definition.
354 * @{
355 */
356
357 /* Delay for DAC channel voltage settling time from DAC channel startup */
358 /* (transition from disable to enable). */
359 /* Note: DAC channel startup time depends on board application environment: */
360 /* impedance connected to DAC channel output. */
361 /* The delay below is specified under conditions: */
362 /* - voltage maximum transition (lowest to highest value) */
363 /* - until voltage reaches final value +-1LSB */
364 /* - DAC channel output buffer enabled */
365 /* - load impedance of 5kOhm (min), 50pF (max) */
366 /* Literal set to maximum value (refer to device datasheet, */
367 /* parameter "tWAKEUP"). */
368 /* Unit: us */
369 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
370
371 /* Delay for DAC channel voltage settling time. */
372 /* Note: DAC channel startup time depends on board application environment: */
373 /* impedance connected to DAC channel output. */
374 /* The delay below is specified under conditions: */
375 /* - voltage maximum transition (lowest to highest value) */
376 /* - until voltage reaches final value +-1LSB */
377 /* - DAC channel output buffer enabled */
378 /* - load impedance of 5kOhm min, 50pF max */
379 /* Literal set to maximum value (refer to device datasheet, */
380 /* parameter "tSETTLING"). */
381 /* Unit: us */
382 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
383
384 /**
385 * @}
386 */
387
388 /**
389 * @}
390 */
391
392 /* Exported macro ------------------------------------------------------------*/
393 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
394 * @{
395 */
396
397 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
398 * @{
399 */
400
401 /**
402 * @brief Write a value in DAC register
403 * @param __INSTANCE__ DAC Instance
404 * @param __REG__ Register to be written
405 * @param __VALUE__ Value to be written in the register
406 * @retval None
407 */
408 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
409
410 /**
411 * @brief Read a value in DAC register
412 * @param __INSTANCE__ DAC Instance
413 * @param __REG__ Register to be read
414 * @retval Register value
415 */
416 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
417
418 /**
419 * @}
420 */
421
422 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
423 * @{
424 */
425
426 /**
427 * @brief Helper macro to get DAC channel number in decimal format
428 * from literals LL_DAC_CHANNEL_x.
429 * Example:
430 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
431 * will return decimal number "1".
432 * @note The input can be a value from functions where a channel
433 * number is returned.
434 * @param __CHANNEL__ This parameter can be one of the following values:
435 * @arg @ref LL_DAC_CHANNEL_1
436 * @retval 1
437 */
438 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
439 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
440
441 /**
442 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
443 * from number in decimal format.
444 * Example:
445 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
446 * will return a data equivalent to "LL_DAC_CHANNEL_1".
447 * @note If the input parameter does not correspond to a DAC channel,
448 * this macro returns value '0'.
449 * @param __DECIMAL_NB__ 1...2
450 * @retval Returned value can be one of the following values:
451 * @arg @ref LL_DAC_CHANNEL_1
452 */
453 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
454 (((__DECIMAL_NB__) == 1UL) \
455 ? ( \
456 LL_DAC_CHANNEL_1 \
457 ) \
458 : \
459 ( \
460 0UL \
461 ) \
462 )
463
464 /**
465 * @brief Helper macro to define the DAC conversion data full-scale digital
466 * value corresponding to the selected DAC resolution.
467 * @note DAC conversion data full-scale corresponds to voltage range
468 * determined by analog voltage references Vref+ and Vref-
469 * (refer to reference manual).
470 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
471 * @arg @ref LL_DAC_RESOLUTION_12B
472 * @arg @ref LL_DAC_RESOLUTION_8B
473 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
474 */
475 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
476 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
477
478 /**
479 * @brief Helper macro to calculate the DAC conversion data (unit: digital
480 * value) corresponding to a voltage (unit: mVolt).
481 * @note This helper macro is intended to provide input data in voltage
482 * rather than digital value,
483 * to be used with LL DAC functions such as
484 * @ref LL_DAC_ConvertData12RightAligned().
485 * @note Analog reference voltage (Vref+) must be either known from
486 * user board environment or can be calculated using ADC measurement
487 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
488 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
489 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
490 * (unit: mVolt).
491 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
492 * @arg @ref LL_DAC_RESOLUTION_12B
493 * @arg @ref LL_DAC_RESOLUTION_8B
494 * @retval DAC conversion data (unit: digital value)
495 */
496 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
497 __DAC_VOLTAGE__,\
498 __DAC_RESOLUTION__) \
499 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
500 / (__VREFANALOG_VOLTAGE__) \
501 )
502
503 /**
504 * @}
505 */
506
507 /**
508 * @}
509 */
510
511
512 /* Exported functions --------------------------------------------------------*/
513 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
514 * @{
515 */
516
517 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
518 * @{
519 */
520
521 /**
522 * @brief Set the operating mode for the selected DAC channel:
523 * calibration or normal operating mode.
524 * @rmtoll CR CEN1 LL_DAC_SetMode
525 * @param DACx DAC instance
526 * @param DAC_Channel This parameter can be one of the following values:
527 * @arg @ref LL_DAC_CHANNEL_1
528 * @param ChannelMode This parameter can be one of the following values:
529 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
530 * @arg @ref LL_DAC_MODE_CALIBRATION
531 * @retval None
532 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)533 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
534 {
535 MODIFY_REG(DACx->CR,
536 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
537 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
538 }
539
540 /**
541 * @brief Get the operating mode for the selected DAC channel:
542 * calibration or normal operating mode.
543 * @rmtoll CR CEN1 LL_DAC_GetMode
544 * @param DACx DAC instance
545 * @param DAC_Channel This parameter can be one of the following values:
546 * @arg @ref LL_DAC_CHANNEL_1
547 * @retval Returned value can be one of the following values:
548 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
549 * @arg @ref LL_DAC_MODE_CALIBRATION
550 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)551 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
552 {
553 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
554 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
555 );
556 }
557
558 /**
559 * @brief Set the offset trimming value for the selected DAC channel.
560 * Trimming has an impact when output buffer is enabled
561 * and is intended to replace factory calibration default values.
562 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue
563 * @param DACx DAC instance
564 * @param DAC_Channel This parameter can be one of the following values:
565 * @arg @ref LL_DAC_CHANNEL_1
566 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
567 * @retval None
568 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)569 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
570 {
571 MODIFY_REG(DACx->CCR,
572 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
573 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
574 }
575
576 /**
577 * @brief Get the offset trimming value for the selected DAC channel.
578 * Trimming has an impact when output buffer is enabled
579 * and is intended to replace factory calibration default values.
580 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue
581 * @param DACx DAC instance
582 * @param DAC_Channel This parameter can be one of the following values:
583 * @arg @ref LL_DAC_CHANNEL_1
584 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
585 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)586 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
587 {
588 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
589 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
590 );
591 }
592
593 /**
594 * @brief Set the conversion trigger source for the selected DAC channel.
595 * @note For conversion trigger source to be effective, DAC trigger
596 * must be enabled using function @ref LL_DAC_EnableTrigger().
597 * @note To set conversion trigger source, DAC channel must be disabled.
598 * Otherwise, the setting is discarded.
599 * @note Availability of parameters of trigger sources from timer
600 * depends on timers availability on the selected device.
601 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource
602 * @param DACx DAC instance
603 * @param DAC_Channel This parameter can be one of the following values:
604 * @arg @ref LL_DAC_CHANNEL_1
605 * @param TriggerSource This parameter can be one of the following values:
606 * @arg @ref LL_DAC_TRIG_SOFTWARE
607 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
608 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
609 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
610 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
611 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
612 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
613 * @retval None
614 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)615 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
616 {
617 MODIFY_REG(DACx->CR,
618 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
619 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
620 }
621
622 /**
623 * @brief Get the conversion trigger source for the selected DAC channel.
624 * @note For conversion trigger source to be effective, DAC trigger
625 * must be enabled using function @ref LL_DAC_EnableTrigger().
626 * @note Availability of parameters of trigger sources from timer
627 * depends on timers availability on the selected device.
628 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource
629 * @param DACx DAC instance
630 * @param DAC_Channel This parameter can be one of the following values:
631 * @arg @ref LL_DAC_CHANNEL_1
632 * @retval Returned value can be one of the following values:
633 * @arg @ref LL_DAC_TRIG_SOFTWARE
634 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
635 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
636 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
637 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
638 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
639 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
640 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)641 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
642 {
643 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
644 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
645 );
646 }
647
648 /**
649 * @brief Set the waveform automatic generation mode
650 * for the selected DAC channel.
651 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration
652 * @param DACx DAC instance
653 * @param DAC_Channel This parameter can be one of the following values:
654 * @arg @ref LL_DAC_CHANNEL_1
655 * @param WaveAutoGeneration This parameter can be one of the following values:
656 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
657 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
658 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
659 * @retval None
660 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)661 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
662 {
663 MODIFY_REG(DACx->CR,
664 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
665 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
666 }
667
668 /**
669 * @brief Get the waveform automatic generation mode
670 * for the selected DAC channel.
671 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration
672 * @param DACx DAC instance
673 * @param DAC_Channel This parameter can be one of the following values:
674 * @arg @ref LL_DAC_CHANNEL_1
675 * @retval Returned value can be one of the following values:
676 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
677 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
678 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
679 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)680 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
681 {
682 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
683 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
684 );
685 }
686
687 /**
688 * @brief Set the noise waveform generation for the selected DAC channel:
689 * Noise mode and parameters LFSR (linear feedback shift register).
690 * @note For wave generation to be effective, DAC channel
691 * wave generation mode must be enabled using
692 * function @ref LL_DAC_SetWaveAutoGeneration().
693 * @note This setting can be set when the selected DAC channel is disabled
694 * (otherwise, the setting operation is ignored).
695 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR
696 * @param DACx DAC instance
697 * @param DAC_Channel This parameter can be one of the following values:
698 * @arg @ref LL_DAC_CHANNEL_1
699 * @param NoiseLFSRMask This parameter can be one of the following values:
700 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
701 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
702 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
703 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
704 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
706 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
707 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
708 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
709 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
710 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
711 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
712 * @retval None
713 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)714 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
715 {
716 MODIFY_REG(DACx->CR,
717 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
718 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
719 }
720
721 /**
722 * @brief Get the noise waveform generation for the selected DAC channel:
723 * Noise mode and parameters LFSR (linear feedback shift register).
724 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR
725 * @param DACx DAC instance
726 * @param DAC_Channel This parameter can be one of the following values:
727 * @arg @ref LL_DAC_CHANNEL_1
728 * @retval Returned value can be one of the following values:
729 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
730 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
731 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
732 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
733 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
734 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
735 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
736 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
737 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
738 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
739 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
740 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
741 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)742 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
743 {
744 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
745 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
746 );
747 }
748
749 /**
750 * @brief Set the triangle waveform generation for the selected DAC channel:
751 * triangle mode and amplitude.
752 * @note For wave generation to be effective, DAC channel
753 * wave generation mode must be enabled using
754 * function @ref LL_DAC_SetWaveAutoGeneration().
755 * @note This setting can be set when the selected DAC channel is disabled
756 * (otherwise, the setting operation is ignored).
757 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
758 * @param DACx DAC instance
759 * @param DAC_Channel This parameter can be one of the following values:
760 * @arg @ref LL_DAC_CHANNEL_1
761 * @param TriangleAmplitude This parameter can be one of the following values:
762 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
763 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
764 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
765 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
766 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
767 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
768 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
769 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
770 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
771 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
772 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
773 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
774 * @retval None
775 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)776 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
777 uint32_t TriangleAmplitude)
778 {
779 MODIFY_REG(DACx->CR,
780 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
781 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
782 }
783
784 /**
785 * @brief Get the triangle waveform generation for the selected DAC channel:
786 * triangle mode and amplitude.
787 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
788 * @param DACx DAC instance
789 * @param DAC_Channel This parameter can be one of the following values:
790 * @arg @ref LL_DAC_CHANNEL_1
791 * @retval Returned value can be one of the following values:
792 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
793 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
794 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
795 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
796 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
797 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
798 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
799 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
800 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
801 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
802 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
803 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
804 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)805 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
806 {
807 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
808 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
809 );
810 }
811
812 /**
813 * @brief Set the output for the selected DAC channel.
814 * @note This function set several features:
815 * - mode normal or sample-and-hold
816 * - buffer
817 * - connection to GPIO or internal path.
818 * These features can also be set individually using
819 * dedicated functions:
820 * - @ref LL_DAC_SetOutputBuffer()
821 * - @ref LL_DAC_SetOutputMode()
822 * - @ref LL_DAC_SetOutputConnection()
823 * @note On this STM32 series, output connection depends on output mode
824 * (normal or sample and hold) and output buffer state.
825 * - if output connection is set to internal path and output buffer
826 * is enabled (whatever output mode):
827 * output connection is also connected to GPIO pin
828 * (both connections to GPIO pin and internal path).
829 * - if output connection is set to GPIO pin, output buffer
830 * is disabled, output mode set to sample and hold:
831 * output connection is also connected to internal path
832 * (both connections to GPIO pin and internal path).
833 * @note Mode sample-and-hold requires an external capacitor
834 * to be connected between DAC channel output and ground.
835 * Capacitor value depends on load on DAC channel output and
836 * sample-and-hold timings configured.
837 * As indication, capacitor typical value is 100nF
838 * (refer to device datasheet, parameter "CSH").
839 * @rmtoll CR MODE1 LL_DAC_ConfigOutput
840 * @param DACx DAC instance
841 * @param DAC_Channel This parameter can be one of the following values:
842 * @arg @ref LL_DAC_CHANNEL_1
843 * @param OutputMode This parameter can be one of the following values:
844 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
845 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
846 * @param OutputBuffer This parameter can be one of the following values:
847 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
848 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
849 * @param OutputConnection This parameter can be one of the following values:
850 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
851 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
852 * @retval None
853 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)854 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
855 uint32_t OutputBuffer, uint32_t OutputConnection)
856 {
857 MODIFY_REG(DACx->MCR,
858 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
859 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
860 }
861
862 /**
863 * @brief Set the output mode normal or sample-and-hold
864 * for the selected DAC channel.
865 * @note Mode sample-and-hold requires an external capacitor
866 * to be connected between DAC channel output and ground.
867 * Capacitor value depends on load on DAC channel output and
868 * sample-and-hold timings configured.
869 * As indication, capacitor typical value is 100nF
870 * (refer to device datasheet, parameter "CSH").
871 * @rmtoll CR MODE1 LL_DAC_SetOutputMode
872 * @param DACx DAC instance
873 * @param DAC_Channel This parameter can be one of the following values:
874 * @arg @ref LL_DAC_CHANNEL_1
875 * @param OutputMode This parameter can be one of the following values:
876 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
877 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
878 * @retval None
879 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)880 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
881 {
882 MODIFY_REG(DACx->MCR,
883 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
884 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
885 }
886
887 /**
888 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
889 * @rmtoll CR MODE1 LL_DAC_GetOutputMode
890 * @param DACx DAC instance
891 * @param DAC_Channel This parameter can be one of the following values:
892 * @arg @ref LL_DAC_CHANNEL_1
893 * @retval Returned value can be one of the following values:
894 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
895 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
896 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)897 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
898 {
899 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
900 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
901 );
902 }
903
904 /**
905 * @brief Set the output buffer for the selected DAC channel.
906 * @note On this STM32 series, when buffer is enabled, its offset can be
907 * trimmed: factory calibration default values can be
908 * replaced by user trimming values, using function
909 * @ref LL_DAC_SetTrimmingValue().
910 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer
911 * @param DACx DAC instance
912 * @param DAC_Channel This parameter can be one of the following values:
913 * @arg @ref LL_DAC_CHANNEL_1
914 * @param OutputBuffer This parameter can be one of the following values:
915 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
916 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
917 * @retval None
918 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)919 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
920 {
921 MODIFY_REG(DACx->MCR,
922 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
923 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
924 }
925
926 /**
927 * @brief Get the output buffer state for the selected DAC channel.
928 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer
929 * @param DACx DAC instance
930 * @param DAC_Channel This parameter can be one of the following values:
931 * @arg @ref LL_DAC_CHANNEL_1
932 * @retval Returned value can be one of the following values:
933 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
934 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
935 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)936 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
937 {
938 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
939 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
940 );
941 }
942
943 /**
944 * @brief Set the output connection for the selected DAC channel.
945 * @note On this STM32 series, output connection depends on output mode (normal or
946 * sample and hold) and output buffer state.
947 * - if output connection is set to internal path and output buffer
948 * is enabled (whatever output mode):
949 * output connection is also connected to GPIO pin
950 * (both connections to GPIO pin and internal path).
951 * - if output connection is set to GPIO pin, output buffer
952 * is disabled, output mode set to sample and hold:
953 * output connection is also connected to internal path
954 * (both connections to GPIO pin and internal path).
955 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection
956 * @param DACx DAC instance
957 * @param DAC_Channel This parameter can be one of the following values:
958 * @arg @ref LL_DAC_CHANNEL_1
959 * @param OutputConnection This parameter can be one of the following values:
960 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
961 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
962 * @retval None
963 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)964 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
965 {
966 MODIFY_REG(DACx->MCR,
967 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
968 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
969 }
970
971 /**
972 * @brief Get the output connection for the selected DAC channel.
973 * @note On this STM32 series, output connection depends on output mode (normal or
974 * sample and hold) and output buffer state.
975 * - if output connection is set to internal path and output buffer
976 * is enabled (whatever output mode):
977 * output connection is also connected to GPIO pin
978 * (both connections to GPIO pin and internal path).
979 * - if output connection is set to GPIO pin, output buffer
980 * is disabled, output mode set to sample and hold:
981 * output connection is also connected to internal path
982 * (both connections to GPIO pin and internal path).
983 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection
984 * @param DACx DAC instance
985 * @param DAC_Channel This parameter can be one of the following values:
986 * @arg @ref LL_DAC_CHANNEL_1
987 * @retval Returned value can be one of the following values:
988 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
989 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
990 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)991 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
992 {
993 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
994 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
995 );
996 }
997
998 /**
999 * @brief Set the sample-and-hold timing for the selected DAC channel:
1000 * sample time
1001 * @note Sample time must be set when DAC channel is disabled
1002 * or during DAC operation when DAC channel flag BWSTx is reset,
1003 * otherwise the setting is ignored.
1004 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1005 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime
1006 * @param DACx DAC instance
1007 * @param DAC_Channel This parameter can be one of the following values:
1008 * @arg @ref LL_DAC_CHANNEL_1
1009 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1010 * @retval None
1011 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1012 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1013 {
1014 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1015 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1016
1017 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1018 }
1019
1020 /**
1021 * @brief Get the sample-and-hold timing for the selected DAC channel:
1022 * sample time
1023 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime
1024 * @param DACx DAC instance
1025 * @param DAC_Channel This parameter can be one of the following values:
1026 * @arg @ref LL_DAC_CHANNEL_1
1027 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1028 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1029 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1030 {
1031 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1032 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1033
1034 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1035 }
1036
1037 /**
1038 * @brief Set the sample-and-hold timing for the selected DAC channel:
1039 * hold time
1040 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime
1041 * @param DACx DAC instance
1042 * @param DAC_Channel This parameter can be one of the following values:
1043 * @arg @ref LL_DAC_CHANNEL_1
1044 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1045 * @retval None
1046 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1047 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1048 {
1049 MODIFY_REG(DACx->SHHR,
1050 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1051 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1052 }
1053
1054 /**
1055 * @brief Get the sample-and-hold timing for the selected DAC channel:
1056 * hold time
1057 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime
1058 * @param DACx DAC instance
1059 * @param DAC_Channel This parameter can be one of the following values:
1060 * @arg @ref LL_DAC_CHANNEL_1
1061 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1062 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1063 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1064 {
1065 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1066 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1067 );
1068 }
1069
1070 /**
1071 * @brief Set the sample-and-hold timing for the selected DAC channel:
1072 * refresh time
1073 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime
1074 * @param DACx DAC instance
1075 * @param DAC_Channel This parameter can be one of the following values:
1076 * @arg @ref LL_DAC_CHANNEL_1
1077 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1078 * @retval None
1079 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1080 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1081 {
1082 MODIFY_REG(DACx->SHRR,
1083 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1084 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1085 }
1086
1087 /**
1088 * @brief Get the sample-and-hold timing for the selected DAC channel:
1089 * refresh time
1090 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime
1091 * @param DACx DAC instance
1092 * @param DAC_Channel This parameter can be one of the following values:
1093 * @arg @ref LL_DAC_CHANNEL_1
1094 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1095 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1096 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1097 {
1098 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1099 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1100 );
1101 }
1102
1103 /**
1104 * @}
1105 */
1106
1107 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1108 * @{
1109 */
1110
1111 /**
1112 * @brief Enable DAC DMA transfer request of the selected channel.
1113 * @note To configure DMA source address (peripheral address),
1114 * use function @ref LL_DAC_DMA_GetRegAddr().
1115 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq
1116 * @param DACx DAC instance
1117 * @param DAC_Channel This parameter can be one of the following values:
1118 * @arg @ref LL_DAC_CHANNEL_1
1119 * @retval None
1120 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1121 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1122 {
1123 SET_BIT(DACx->CR,
1124 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1125 }
1126
1127 /**
1128 * @brief Disable DAC DMA transfer request of the selected channel.
1129 * @note To configure DMA source address (peripheral address),
1130 * use function @ref LL_DAC_DMA_GetRegAddr().
1131 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq
1132 * @param DACx DAC instance
1133 * @param DAC_Channel This parameter can be one of the following values:
1134 * @arg @ref LL_DAC_CHANNEL_1
1135 * @retval None
1136 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1137 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1138 {
1139 CLEAR_BIT(DACx->CR,
1140 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1141 }
1142
1143 /**
1144 * @brief Get DAC DMA transfer request state of the selected channel.
1145 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1146 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled
1147 * @param DACx DAC instance
1148 * @param DAC_Channel This parameter can be one of the following values:
1149 * @arg @ref LL_DAC_CHANNEL_1
1150 * @retval State of bit (1 or 0).
1151 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1152 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1153 {
1154 return ((READ_BIT(DACx->CR,
1155 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1156 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1157 }
1158
1159 /**
1160 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1161 * DAC register address from DAC instance and a list of DAC registers
1162 * intended to be used (most commonly) with DMA transfer.
1163 * @note These DAC registers are data holding registers:
1164 * when DAC conversion is requested, DAC generates a DMA transfer
1165 * request to have data available in DAC data holding registers.
1166 * @note This macro is intended to be used with LL DMA driver, refer to
1167 * function "LL_DMA_ConfigAddresses()".
1168 * Example:
1169 * LL_DMA_ConfigAddresses(DMA1,
1170 * LL_DMA_CHANNEL_1,
1171 * (uint32_t)&< array or variable >,
1172 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1173 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1174 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1175 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1176 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1177 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
1178 * @param DACx DAC instance
1179 * @param DAC_Channel This parameter can be one of the following values:
1180 * @arg @ref LL_DAC_CHANNEL_1
1181 * @param Register This parameter can be one of the following values:
1182 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1183 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1184 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1185 * @retval DAC register address
1186 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1187 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1188 {
1189 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1190 /* DAC channel selected. */
1191 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1192 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1193 }
1194 /**
1195 * @}
1196 */
1197
1198 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1199 * @{
1200 */
1201
1202 /**
1203 * @brief Enable DAC selected channel.
1204 * @rmtoll CR EN1 LL_DAC_Enable
1205 * @note After enable from off state, DAC channel requires a delay
1206 * for output voltage to reach accuracy +/- 1 LSB.
1207 * Refer to device datasheet, parameter "tWAKEUP".
1208 * @param DACx DAC instance
1209 * @param DAC_Channel This parameter can be one of the following values:
1210 * @arg @ref LL_DAC_CHANNEL_1
1211 * @retval None
1212 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1213 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1214 {
1215 SET_BIT(DACx->CR,
1216 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1217 }
1218
1219 /**
1220 * @brief Disable DAC selected channel.
1221 * @rmtoll CR EN1 LL_DAC_Disable
1222 * @param DACx DAC instance
1223 * @param DAC_Channel This parameter can be one of the following values:
1224 * @arg @ref LL_DAC_CHANNEL_1
1225 * @retval None
1226 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1227 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1228 {
1229 CLEAR_BIT(DACx->CR,
1230 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1231 }
1232
1233 /**
1234 * @brief Get DAC enable state of the selected channel.
1235 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1236 * @rmtoll CR EN1 LL_DAC_IsEnabled
1237 * @param DACx DAC instance
1238 * @param DAC_Channel This parameter can be one of the following values:
1239 * @arg @ref LL_DAC_CHANNEL_1
1240 * @retval State of bit (1 or 0).
1241 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1242 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1243 {
1244 return ((READ_BIT(DACx->CR,
1245 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1246 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1247 }
1248
1249 /**
1250 * @brief Enable DAC trigger of the selected channel.
1251 * @note - If DAC trigger is disabled, DAC conversion is performed
1252 * automatically once the data holding register is updated,
1253 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1254 * @ref LL_DAC_ConvertData12RightAligned(), ...
1255 * - If DAC trigger is enabled, DAC conversion is performed
1256 * only when a hardware of software trigger event is occurring.
1257 * Select trigger source using
1258 * function @ref LL_DAC_SetTriggerSource().
1259 * @rmtoll CR TEN1 LL_DAC_EnableTrigger
1260 * @param DACx DAC instance
1261 * @param DAC_Channel This parameter can be one of the following values:
1262 * @arg @ref LL_DAC_CHANNEL_1
1263 * @retval None
1264 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1265 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1266 {
1267 SET_BIT(DACx->CR,
1268 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1269 }
1270
1271 /**
1272 * @brief Disable DAC trigger of the selected channel.
1273 * @rmtoll CR TEN1 LL_DAC_DisableTrigger
1274 * @param DACx DAC instance
1275 * @param DAC_Channel This parameter can be one of the following values:
1276 * @arg @ref LL_DAC_CHANNEL_1
1277 * @retval None
1278 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1279 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1280 {
1281 CLEAR_BIT(DACx->CR,
1282 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1283 }
1284
1285 /**
1286 * @brief Get DAC trigger state of the selected channel.
1287 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1288 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled
1289 * @param DACx DAC instance
1290 * @param DAC_Channel This parameter can be one of the following values:
1291 * @arg @ref LL_DAC_CHANNEL_1
1292 * @retval State of bit (1 or 0).
1293 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1294 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1295 {
1296 return ((READ_BIT(DACx->CR,
1297 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1298 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1299 }
1300
1301 /**
1302 * @brief Trig DAC conversion by software for the selected DAC channel.
1303 * @note Preliminarily, DAC trigger must be set to software trigger
1304 * using function
1305 * @ref LL_DAC_Init()
1306 * @ref LL_DAC_SetTriggerSource()
1307 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1308 * and DAC trigger must be enabled using
1309 * function @ref LL_DAC_EnableTrigger().
1310 * @note For devices featuring DAC with 2 channels: this function
1311 * can perform a SW start of both DAC channels simultaneously.
1312 * Two channels can be selected as parameter.
1313 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1314 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
1315 * @param DACx DAC instance
1316 * @param DAC_Channel This parameter can a combination of the following values:
1317 * @arg @ref LL_DAC_CHANNEL_1
1318 * @retval None
1319 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1320 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1321 {
1322 SET_BIT(DACx->SWTRIGR,
1323 (DAC_Channel & DAC_SWTR_CHX_MASK));
1324 }
1325
1326 /**
1327 * @brief Set the data to be loaded in the data holding register
1328 * in format 12 bits left alignment (LSB aligned on bit 0),
1329 * for the selected DAC channel.
1330 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
1331 * @param DACx DAC instance
1332 * @param DAC_Channel This parameter can be one of the following values:
1333 * @arg @ref LL_DAC_CHANNEL_1
1334 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1335 * @retval None
1336 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1337 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1338 {
1339 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1340 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1341
1342 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1343 }
1344
1345 /**
1346 * @brief Set the data to be loaded in the data holding register
1347 * in format 12 bits left alignment (MSB aligned on bit 15),
1348 * for the selected DAC channel.
1349 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
1350 * @param DACx DAC instance
1351 * @param DAC_Channel This parameter can be one of the following values:
1352 * @arg @ref LL_DAC_CHANNEL_1
1353 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1354 * @retval None
1355 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1356 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1357 {
1358 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1359 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1360
1361 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1362 }
1363
1364 /**
1365 * @brief Set the data to be loaded in the data holding register
1366 * in format 8 bits left alignment (LSB aligned on bit 0),
1367 * for the selected DAC channel.
1368 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
1369 * @param DACx DAC instance
1370 * @param DAC_Channel This parameter can be one of the following values:
1371 * @arg @ref LL_DAC_CHANNEL_1
1372 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1373 * @retval None
1374 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1375 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1376 {
1377 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1378 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1379
1380 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1381 }
1382
1383 /**
1384 * @brief Retrieve output data currently generated for the selected DAC channel.
1385 * @note Whatever alignment and resolution settings
1386 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1387 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1388 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1389 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData
1390 * @param DACx DAC instance
1391 * @param DAC_Channel This parameter can be one of the following values:
1392 * @arg @ref LL_DAC_CHANNEL_1
1393 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1394 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1395 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1396 {
1397 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1398 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1399
1400 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1401 }
1402
1403 /**
1404 * @}
1405 */
1406
1407 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1408 * @{
1409 */
1410
1411 /**
1412 * @brief Get DAC calibration offset flag for DAC channel 1
1413 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1414 * @param DACx DAC instance
1415 * @retval State of bit (1 or 0).
1416 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1417 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1418 {
1419 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1420 }
1421
1422 /**
1423 * @brief Get DAC busy writing sample time flag for DAC channel 1
1424 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1425 * @param DACx DAC instance
1426 * @retval State of bit (1 or 0).
1427 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1428 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1429 {
1430 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1431 }
1432
1433 /**
1434 * @brief Get DAC underrun flag for DAC channel 1
1435 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1436 * @param DACx DAC instance
1437 * @retval State of bit (1 or 0).
1438 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1439 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1440 {
1441 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1442 }
1443
1444 /**
1445 * @brief Clear DAC underrun flag for DAC channel 1
1446 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1447 * @param DACx DAC instance
1448 * @retval None
1449 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1450 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1451 {
1452 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1453 }
1454
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup DAC_LL_EF_IT_Management IT management
1460 * @{
1461 */
1462
1463 /**
1464 * @brief Enable DMA underrun interrupt for DAC channel 1
1465 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1466 * @param DACx DAC instance
1467 * @retval None
1468 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1469 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1470 {
1471 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1472 }
1473
1474 /**
1475 * @brief Disable DMA underrun interrupt for DAC channel 1
1476 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1477 * @param DACx DAC instance
1478 * @retval None
1479 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1480 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1481 {
1482 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1483 }
1484
1485 /**
1486 * @brief Get DMA underrun interrupt for DAC channel 1
1487 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1488 * @param DACx DAC instance
1489 * @retval State of bit (1 or 0).
1490 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1491 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1492 {
1493 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1494 }
1495
1496 /**
1497 * @}
1498 */
1499
1500 #if defined(USE_FULL_LL_DRIVER)
1501 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1502 * @{
1503 */
1504
1505 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1506 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1507 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1508
1509 /**
1510 * @}
1511 */
1512 #endif /* USE_FULL_LL_DRIVER */
1513
1514 /**
1515 * @}
1516 */
1517
1518 /**
1519 * @}
1520 */
1521
1522 #endif /* DAC */
1523
1524 /**
1525 * @}
1526 */
1527
1528 #ifdef __cplusplus
1529 }
1530 #endif
1531
1532 #endif /* STM32WLxx_LL_DAC_H */
1533
