1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32WLxx_HAL_GTZC_H 20 #define STM32WLxx_HAL_GTZC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32wlxx_hal_def.h" 28 29 #if defined(GTZC_TZSC) 30 31 /** @addtogroup STM32WLxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup GTZC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup GTZC_Exported_Types GTZC Exported Types 41 * @{ 42 */ 43 /** 44 * @brief GTZC TZSC MPCWM structure 45 */ 46 typedef struct 47 { 48 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 49 GTZC_MPCWM_AreaId */ 50 uint32_t Length; /*!< length of the unprivileged area starting from selected 51 memory base address. It must be aligned on 2kB for Flash 52 areas and 1kB for Sram ones. */ 53 } MPCWM_ConfigTypeDef; 54 /** 55 * @} 56 */ 57 58 59 /* Private constants --------------------------------------------------------*/ 60 /** @defgroup GTZC_Private_Constants GTZC Private Constants 61 * @{ 62 */ 63 /** 64 * @brief GTZC structure definitions for IP identifier parameter (PeriphId) 65 * used in HAL_GTZC_TZSC_ConfigPeriphAttributes and 66 * HAL_GTZC_TZSC_GetConfigPeriphAttributes functions and also in all 67 * HAL_GTZC_TZIC related functions bitmap: 68 * bits[31:28] Field "register". Define the register an IP belongs to. 69 * Each bit is dedicated to a single register. 70 * bit[5] Field "all Ips". If this bit is set then the PeriphId 71 * targets all Ips within register. 72 * bits[4:0] Field "bit position". Define the bit position within 73 * the register dedicated to the IP, value from 0 to 31. 74 */ 75 #define GTZC_PERIPH_REG_Pos (28U) 76 #define GTZC_PERIPH_REG_Msk (0xFUL << GTZC_PERIPH_REG_Pos) /*0 xF0000000 */ 77 #define GTZC_PERIPH_REG1 (0x0UL << GTZC_PERIPH_REG_Pos) 78 #define GTZC_PERIPH_ALLPERIPH_Pos (5U) 79 #define GTZC_PERIPH_ALLPERIPH_Msk (0x1UL << GTZC_PERIPH_ALLPERIPH_Pos) /* 0x00000020 */ 80 #define GTZC_PERIPH_BITPOS_Pos (0U) 81 #define GTZC_PERIPH_BITPOS_Msk (0x1FUL << GTZC_PERIPH_BITPOS_Pos) /* 0x0000001F */ 82 83 /** 84 * @brief GTZC TZSC MPCWM Watermark granularity depending on area 85 */ 86 #define GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET 11U 87 #define GTZC_TZSC_MPCWM_GRANULARITY_FLASH (1UL << GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET) /* 2 kB */ 88 #define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET 10U 89 #define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1 (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET) /* 1 kB */ 90 #define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET 10U 91 #define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2 (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET) /* 1 kB */ 92 93 /** 94 * @} 95 */ 96 97 98 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 99 * @{ 100 */ 101 102 /** @defgroup GTZC_TZSC_Peripheral_Attribute GTZC TZSC Peripheral Attribute 103 * bitmap: bit0 : Sec Attr (0 = Ns, 1 = Sec) 104 * bit1 : PrivAttr (0 = NonPriv, 1 = Priv) 105 * @{ 106 */ 107 #define GTZC_TZSC_ATTRIBUTE_NSEC 0x00U 108 #define GTZC_TZSC_ATTRIBUTE_SEC 0x01U 109 #define GTZC_TZSC_ATTRIBUTE_NPRIV 0x00U 110 #define GTZC_TZSC_ATTRIBUTE_PRIV 0x02U 111 /** 112 * @} 113 */ 114 115 /** @defgroup GTZC_Peripheral_Identification GTZC Peripheral Identification 116 * user-oriented definition for each IP identifier parameter (PeriphId) 117 * used in HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes 118 * functions and also in all HAL_GTZC_TZIC relative functions. 119 * @note user can also select all IPs using specific define 120 * @note that two maximum values are also defined here: 121 * - max number of securable AHB/APB peripherals or masters (used in 122 * TZSC sub-block) 123 * - max number of securable and security-aware AHB/APB peripherals 124 * or masters (used in TZIC sub-block) 125 * @{ 126 */ 127 #define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZIC_Pos) 128 #define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZSC_Pos) 129 #define GTZC_PERIPH_AES (GTZC_PERIPH_REG1 | GTZC_CFGR1_AES_Pos) 130 #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG1 | GTZC_CFGR1_RNG_Pos) 131 #define GTZC_PERIPH_SUBGHZSPI (GTZC_PERIPH_REG1 | GTZC_CFGR1_SUBGHZSPI_Pos) 132 #define GTZC_PERIPH_PWR (GTZC_PERIPH_REG1 | GTZC_CFGR1_PWR_Pos) 133 #define GTZC_PERIPH_FLASHIF (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASHIF_Pos) 134 #define GTZC_PERIPH_DMA1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA1_Pos) 135 #define GTZC_PERIPH_DMA2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA2_Pos) 136 #define GTZC_PERIPH_DMAMUX (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMAMUX_Pos) 137 #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASH_Pos) 138 #define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM1_Pos) 139 #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM2_Pos) 140 #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG1 | GTZC_CFGR1_PKA_Pos) 141 #define GTZC_PERIPH_TZIC_MAX GTZC_PERIPH_PKA 142 #define GTZC_PERIPH_ALL GTZC_PERIPH_ALLPERIPH_Msk 143 144 145 /* Note that two maximum values are also defined here: 146 * - max number of securable peripherals 147 * (used in TZSC sub-block) 148 * - max number of securable and security-aware peripherals or masters 149 * (used in TZIC sub-block) 150 */ 151 #define GTZC_TZSC_PERIPH_NUMBER 4U 152 #define GTZC_TZIC_PERIPH_NUMBER (GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PKA + 1U)) 153 154 /** 155 * @} 156 */ 157 158 /** @defgroup GTZC_TZSC_Lock GTZC TZSC Lock 159 * @{ 160 */ 161 #define GTZC_TZSC_LOCK_OFF (0U) 162 #define GTZC_TZSC_LOCK_ON (1U) 163 /** 164 * @} 165 */ 166 167 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 168 * @{ 169 */ 170 #define GTZC_TZSC_MPCWM_AREAID_UNPRIV (0U) 171 #define GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE (1U) 172 /** 173 * @} 174 */ 175 176 177 /** @defgroup GTZC_TZIC_ILA_Pending GTZC TZIC ILA Pending 178 * @{ 179 */ 180 #define GTZC_TZIC_NO_ILA_EVENT (0U) 181 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 182 /** 183 * @} 184 */ 185 186 /** 187 * @} 188 */ 189 190 /* Exported macro ------------------------------------------------------------*/ 191 /* Exported functions --------------------------------------------------------*/ 192 /** @addtogroup GTZC_Exported_Functions 193 * @{ 194 */ 195 196 /** @addtogroup GTZC_Exported_Functions_Group1 197 * @{ 198 */ 199 /* TZSC Initialization and Configuration functions ****************************/ 200 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t PeriphAttributes); 201 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, uint32_t *PeriphAttributes); 202 /** 203 * @} 204 */ 205 206 /** @addtogroup GTZC_Exported_Functions_Group2 207 * @{ 208 */ 209 /* MPCWM Initialization and Configuration functions ***************************/ 210 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc); 211 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc); 212 /** 213 * @} 214 */ 215 216 /** @addtogroup GTZC_Exported_Functions_Group3 217 * @{ 218 */ 219 /* TZSC and TZSC-MPCWM Lock functions *****************************************/ 220 uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSCx); 221 #if defined(CORE_CM0PLUS) 222 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx); 223 /** 224 * @} 225 */ 226 227 /** @addtogroup GTZC_Exported_Functions_Group4 228 * @{ 229 */ 230 /* TZIC Initialization and Configuration functions ****************************/ 231 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 232 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 233 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *Flag); 234 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 235 /** 236 * @} 237 */ 238 239 /** @addtogroup GTZC_Exported_Functions_Group5 240 * @{ 241 */ 242 void HAL_GTZC_IRQHandler(void); 243 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 244 #endif /* CORE_CM0PLUS */ 245 /** 246 * @} 247 */ 248 249 /** 250 * @} 251 */ 252 253 254 /* Private macro ------------------------------------------------------------*/ 255 /** @defgroup GTZC_Private_Macros GTZC Private Macros 256 * @{ 257 */ 258 /** 259 * @brief GTZC private macros usable to retrieve information to access register 260 * for a specific PeriphId 261 */ 262 #define GTZC_GET_REG_INDEX(__PERIPHERAL__) (((__PERIPHERAL__) & GTZC_PERIPH_REG_Msk) >> GTZC_PERIPH_REG_Pos) 263 #define GTZC_GET_PERIPH_POS(__PERIPHERAL__) ((__PERIPHERAL__) & GTZC_PERIPH_BITPOS_Msk) 264 265 /** 266 * @brief GTZC private macro to get array index of a specific PeriphId 267 * in case of GTZC_PERIPH_ALL usage in the two following functions: 268 * HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes 269 */ 270 #define GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) ((GTZC_GET_REG_INDEX(__PERIPHERAL__) * 32U) + GTZC_GET_PERIPH_POS(__PERIPHERAL__)) 271 272 273 /** 274 * @brief GTZC private macros to check function input parameters 275 */ 276 #define IS_GTZC_ATTRIBUTE(__ATTRIBUTES__) (((__ATTRIBUTES__) & ~(GTZC_TZSC_ATTRIBUTE_SEC | GTZC_TZSC_ATTRIBUTE_PRIV)) == 0x00u) 277 278 #define IS_GTZC_TZSC_PERIPHERAL(__PERIPHERAL__) (((__PERIPHERAL__) == GTZC_PERIPH_AES) || ((__PERIPHERAL__) == GTZC_PERIPH_RNG) || \ 279 ((__PERIPHERAL__) == GTZC_PERIPH_SUBGHZSPI) || ((__PERIPHERAL__) == GTZC_PERIPH_PKA) ||\ 280 ((__PERIPHERAL__) == GTZC_PERIPH_ALL)) 281 282 #define IS_GTZC_TZIC_PERIPHERAL(__PERIPHERAL__) (((((__PERIPHERAL__) & ~(GTZC_PERIPH_REG_Pos | GTZC_PERIPH_BITPOS_Msk)) == 0x00u) && \ 283 ((GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) <= GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_TZIC_MAX)))) || \ 284 ((__PERIPHERAL__) == GTZC_PERIPH_ALLPERIPH_Msk)) 285 286 #define IS_GTZC_MPCWM_MEMORY_BASEADDRESS(__BASE_ADDRESS__) (((__BASE_ADDRESS__) == FLASH_BASE) || \ 287 ((__BASE_ADDRESS__) == SRAM1_BASE) || \ 288 ((__BASE_ADDRESS__) == SRAM2_BASE)) 289 290 #define IS_GTZC_MPCWM_FLASH_AREAID(__AREAID__) (((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) || \ 291 ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE)) 292 293 #define IS_GTZC_MPCWM_SRAM1_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) 294 295 #define IS_GTZC_MPCWM_SRAM2_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) 296 297 #define IS_GTZC_MPCWM_FLASH_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_FLASH) == 0x00u) && \ 298 ((__LENGTH__) <= FLASH_SIZE)) 299 300 #define IS_GTZC_MPCWM_SRAM1_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM1) == 0x00u) && \ 301 ((__LENGTH__) <= SRAM1_SIZE)) 302 303 #define IS_GTZC_MPCWM_SRAM2_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM2) == 0x00u) && \ 304 ((__LENGTH__) <= SRAM2_SIZE)) 305 306 /** 307 * @} 308 */ 309 310 /** 311 * @} 312 */ 313 314 /** 315 * @} 316 */ 317 #endif /* GTZC_TZSC */ 318 319 #ifdef __cplusplus 320 } 321 #endif 322 323 #endif /* STM32WLxx_HAL_GTZC_H */ 324
