1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_DMAMUX_H
21 #define STM32WBxx_LL_DMAMUX_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMAMUX1)
35
36 /** @defgroup DMAMUX_LL DMAMUX
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
44 * @{
45 */
46 /* Define used to get DMAMUX CCR register size */
47 #define DMAMUX_CCR_SIZE 0x00000004UL
48
49 /* Define used to get DMAMUX RGCR register size */
50 #define DMAMUX_RGCR_SIZE 0x00000004UL
51 /**
52 * @}
53 */
54
55 /* Private macros ------------------------------------------------------------*/
56 /* Exported types ------------------------------------------------------------*/
57 /* Exported constants --------------------------------------------------------*/
58 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
59 * @{
60 */
61 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
62 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
63 * @{
64 */
65 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
66 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
67 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
68 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
69 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
70 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
71 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
72 #if defined(DMA2)
73 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
74 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
75 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
76 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
77 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
78 #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
79 #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
80 #endif /* DMA2 */
81 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
82 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
83 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
84 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
85 /**
86 * @}
87 */
88
89 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
90 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
91 * @{
92 */
93 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
94 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
95 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
96 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
97 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
98 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
99 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
100 #if defined(DMA2)
101 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
102 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
103 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
104 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
105 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
106 #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
107 #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
108 #endif /* DMA2 */
109 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
110 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
111 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
112 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
113 /**
114 * @}
115 */
116
117 /** @defgroup DMAMUX_LL_EC_IT IT Defines
118 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
119 * @{
120 */
121 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
122 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
123 /**
124 * @}
125 */
126
127 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
128 * @{
129 */
130 #define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */
131 #define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */
132 #define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */
133 #define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */
134 #define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */
135 #define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */
136 #define LL_DMAMUX_REQ_SPI1_RX 0x00000006U /*!< DMAMUX SPI1 RX request */
137 #define LL_DMAMUX_REQ_SPI1_TX 0x00000007U /*!< DMAMUX SPI1 TX request */
138 #if defined(SPI2)
139 #define LL_DMAMUX_REQ_SPI2_RX 0x00000008U /*!< DMAMUX SPI2 RX request */
140 #define LL_DMAMUX_REQ_SPI2_TX 0x00000009U /*!< DMAMUX SPI2 TX request */
141 #endif /* SPI2 */
142 #define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */
143 #define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */
144 #if defined(I2C3)
145 #define LL_DMAMUX_REQ_I2C3_RX 0x0000000CU /*!< DMAMUX I2C3 RX request */
146 #define LL_DMAMUX_REQ_I2C3_TX 0x0000000DU /*!< DMAMUX I2C3 TX request */
147 #endif /* I2C3 */
148 #define LL_DMAMUX_REQ_USART1_RX 0x0000000EU /*!< DMAMUX USART1 RX request */
149 #define LL_DMAMUX_REQ_USART1_TX 0x0000000FU /*!< DMAMUX USART1 TX request */
150 #if defined(LPUART1)
151 #define LL_DMAMUX_REQ_LPUART1_RX 0x00000010U /*!< DMAMUX LPUART1 RX request */
152 #define LL_DMAMUX_REQ_LPUART1_TX 0x00000011U /*!< DMAMUX LPUART1 TX request */
153 #endif /* LPUART1 */
154 #if defined(SAI1)
155 #define LL_DMAMUX_REQ_SAI1_A 0x00000012U /*!< DMAMUX SAI1 A request */
156 #define LL_DMAMUX_REQ_SAI1_B 0x00000013U /*!< DMAMUX SAI1 B request */
157 #endif /* SAI1 */
158 #if defined(QUADSPI)
159 #define LL_DMAMUX_REQ_QUADSPI 0x00000014U /*!< DMAMUX QUADSPI request */
160 #endif /* QUADSPI */
161 #define LL_DMAMUX_REQ_TIM1_CH1 0x00000015U /*!< DMAMUX TIM1 CH1 request */
162 #define LL_DMAMUX_REQ_TIM1_CH2 0x00000016U /*!< DMAMUX TIM1 CH2 request */
163 #define LL_DMAMUX_REQ_TIM1_CH3 0x00000017U /*!< DMAMUX TIM1 CH3 request */
164 #define LL_DMAMUX_REQ_TIM1_CH4 0x00000018U /*!< DMAMUX TIM1 CH4 request */
165 #define LL_DMAMUX_REQ_TIM1_UP 0x00000019U /*!< DMAMUX TIM1 UP request */
166 #define LL_DMAMUX_REQ_TIM1_TRIG 0x0000001AU /*!< DMAMUX TIM1 TRIG request */
167 #define LL_DMAMUX_REQ_TIM1_COM 0x0000001BU /*!< DMAMUX TIM1 COM request */
168 #define LL_DMAMUX_REQ_TIM2_CH1 0x0000001CU /*!< DMAMUX TIM2 CH1 request */
169 #define LL_DMAMUX_REQ_TIM2_CH2 0x0000001DU /*!< DMAMUX TIM2 CH2 request */
170 #define LL_DMAMUX_REQ_TIM2_CH3 0x0000001EU /*!< DMAMUX TIM2 CH3 request */
171 #define LL_DMAMUX_REQ_TIM2_CH4 0x0000001FU /*!< DMAMUX TIM2 CH4 request */
172 #define LL_DMAMUX_REQ_TIM2_UP 0x00000020U /*!< DMAMUX TIM2 UP request */
173 #define LL_DMAMUX_REQ_TIM16_CH1 0x00000021U /*!< DMAMUX TIM16 CH1 request */
174 #define LL_DMAMUX_REQ_TIM16_UP 0x00000022U /*!< DMAMUX TIM16 UP request */
175 #define LL_DMAMUX_REQ_TIM17_CH1 0x00000023U /*!< DMAMUX TIM17 CH1 request */
176 #define LL_DMAMUX_REQ_TIM17_UP 0x00000024U /*!< DMAMUX TIM17 UP request */
177 #if defined(AES1)
178 #define LL_DMAMUX_REQ_AES1_IN 0x00000025U /*!< DMAMUX AES1_IN request */
179 #define LL_DMAMUX_REQ_AES1_OUT 0x00000026U /*!< DMAMUX AES1_OUT request */
180 #endif /* AES1 */
181 #define LL_DMAMUX_REQ_AES2_IN 0x00000027U /*!< DMAMUX AES2_IN request */
182 #define LL_DMAMUX_REQ_AES2_OUT 0x00000028U /*!< DMAMUX AES2_OUT request */
183 /**
184 * @}
185 */
186
187 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
188 * @{
189 */
190 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
191 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
192 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
193 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
194 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
195 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
196 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
197 #if defined(DMA2)
198 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */
199 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */
200 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */
201 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
202 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
203 #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */
204 #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */
205 #endif /* DMA2 */
206 /**
207 * @}
208 */
209
210 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
211 * @{
212 */
213 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
214 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
215 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
216 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
217 /**
218 * @}
219 */
220
221 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
222 * @{
223 */
224 #define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */
225 #define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
226 #define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
227 #define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
228 #define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
229 #define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
230 #define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
231 #define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
232 #define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
233 #define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
234 #define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
235 #define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
236 #define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
237 #define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */
238 #define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */
239 #define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
240 #define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */
241 #define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
242 #define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from LPTIM1 Output */
243 #define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
244 /**
245 * @}
246 */
247
248 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
249 * @{
250 */
251 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
252 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
253 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
254 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
255 /**
256 * @}
257 */
258
259 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
260 * @{
261 */
262 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
263 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
264 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
265 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
266 /**
267 * @}
268 */
269
270 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
271 * @{
272 */
273 #define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */
274 #define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
275 #define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
276 #define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
277 #define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
278 #define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
279 #define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
280 #define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
281 #define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
282 #define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
283 #define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
284 #define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
285 #define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
286 #define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
287 #define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
288 #define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
289 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */
290 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
291 #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from LPTIM1 Output */
292 #define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
293 /**
294 * @}
295 */
296
297 /**
298 * @}
299 */
300
301 /* Exported macro ------------------------------------------------------------*/
302 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
303 * @{
304 */
305
306 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
307 * @{
308 */
309 /**
310 * @brief Write a value in DMAMUX register
311 * @param __INSTANCE__ DMAMUX Instance
312 * @param __REG__ Register to be written
313 * @param __VALUE__ Value to be written in the register
314 * @retval None
315 */
316 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
317
318 /**
319 * @brief Read a value in DMAMUX register
320 * @param __INSTANCE__ DMAMUX Instance
321 * @param __REG__ Register to be read
322 * @retval Register value
323 */
324 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
325 /**
326 * @}
327 */
328
329 /**
330 * @}
331 */
332
333 /* Exported functions --------------------------------------------------------*/
334 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
335 * @{
336 */
337
338 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
339 * @{
340 */
341 /**
342 * @brief Set DMAMUX request ID for DMAMUX Channel x.
343 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
344 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
345 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
346 * @param DMAMUXx DMAMUXx Instance
347 * @param Channel This parameter can be one of the following values:
348 * @arg @ref LL_DMAMUX_CHANNEL_0
349 * @arg @ref LL_DMAMUX_CHANNEL_1
350 * @arg @ref LL_DMAMUX_CHANNEL_2
351 * @arg @ref LL_DMAMUX_CHANNEL_3
352 * @arg @ref LL_DMAMUX_CHANNEL_4
353 * @arg @ref LL_DMAMUX_CHANNEL_5
354 * @arg @ref LL_DMAMUX_CHANNEL_6
355 *
356 * @arg All the next values are only available on chip which support DMA2:
357 * @arg @ref LL_DMAMUX_CHANNEL_7
358 * @arg @ref LL_DMAMUX_CHANNEL_8
359 * @arg @ref LL_DMAMUX_CHANNEL_9
360 * @arg @ref LL_DMAMUX_CHANNEL_10
361 * @arg @ref LL_DMAMUX_CHANNEL_11
362 * @arg @ref LL_DMAMUX_CHANNEL_12
363 * @arg @ref LL_DMAMUX_CHANNEL_13
364 * @param Request This parameter can be one of the following values:
365 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
366 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
367 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
368 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
369 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
370 * @arg @ref LL_DMAMUX_REQ_ADC1
371 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
372 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
373 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
374 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
375 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
376 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
377 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
378 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
379 * @arg @ref LL_DMAMUX_REQ_USART1_RX
380 * @arg @ref LL_DMAMUX_REQ_USART1_TX
381 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
382 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
383 * @arg @ref LL_DMAMUX_REQ_SAI1_A
384 * @arg @ref LL_DMAMUX_REQ_SAI1_B
385 * @arg @ref LL_DMAMUX_REQ_QUADSPI
386 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
387 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
388 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
389 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
390 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
391 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
392 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
393 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
394 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
395 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
396 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
397 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
398 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
399 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
400 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
401 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
402 * @arg @ref LL_DMAMUX_REQ_AES1_IN
403 * @arg @ref LL_DMAMUX_REQ_AES1_OUT
404 * @arg @ref LL_DMAMUX_REQ_AES2_IN
405 * @arg @ref LL_DMAMUX_REQ_AES2_OUT
406 * @retval None
407 */
LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Request)408 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
409 {
410 (void)(DMAMUXx);
411 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
412 }
413
414 /**
415 * @brief Get DMAMUX request ID for DMAMUX Channel x.
416 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
417 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
418 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
419 * @param DMAMUXx DMAMUXx Instance
420 * @param Channel This parameter can be one of the following values:
421 * @arg @ref LL_DMAMUX_CHANNEL_0
422 * @arg @ref LL_DMAMUX_CHANNEL_1
423 * @arg @ref LL_DMAMUX_CHANNEL_2
424 * @arg @ref LL_DMAMUX_CHANNEL_3
425 * @arg @ref LL_DMAMUX_CHANNEL_4
426 * @arg @ref LL_DMAMUX_CHANNEL_5
427 * @arg @ref LL_DMAMUX_CHANNEL_6
428 *
429 * @arg All the next values are only available on chip which support DMA2:
430 * @arg @ref LL_DMAMUX_CHANNEL_7
431 * @arg @ref LL_DMAMUX_CHANNEL_8
432 * @arg @ref LL_DMAMUX_CHANNEL_9
433 * @arg @ref LL_DMAMUX_CHANNEL_10
434 * @arg @ref LL_DMAMUX_CHANNEL_11
435 * @arg @ref LL_DMAMUX_CHANNEL_12
436 * @arg @ref LL_DMAMUX_CHANNEL_13
437 * @retval Returned value can be one of the following values:
438 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
439 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
440 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
441 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
442 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
443 * @arg @ref LL_DMAMUX_REQ_ADC1
444 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
445 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
446 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
447 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
448 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
449 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
450 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
451 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
452 * @arg @ref LL_DMAMUX_REQ_USART1_RX
453 * @arg @ref LL_DMAMUX_REQ_USART1_TX
454 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
455 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
456 * @arg @ref LL_DMAMUX_REQ_SAI1_A
457 * @arg @ref LL_DMAMUX_REQ_SAI1_B
458 * @arg @ref LL_DMAMUX_REQ_QUADSPI
459 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
460 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
461 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
462 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
463 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
464 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
465 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
466 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
467 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
468 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
469 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
470 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
471 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
472 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
473 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
474 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
475 * @arg @ref LL_DMAMUX_REQ_AES1_IN
476 * @arg @ref LL_DMAMUX_REQ_AES1_OUT
477 * @arg @ref LL_DMAMUX_REQ_AES2_IN
478 * @arg @ref LL_DMAMUX_REQ_AES2_OUT
479 */
LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)480 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
481 {
482 (void)(DMAMUXx);
483 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
484 }
485
486 /**
487 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
488 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
489 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
490 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
491 * @param DMAMUXx DMAMUXx Instance
492 * @param Channel This parameter can be one of the following values:
493 * @arg @ref LL_DMAMUX_CHANNEL_0
494 * @arg @ref LL_DMAMUX_CHANNEL_1
495 * @arg @ref LL_DMAMUX_CHANNEL_2
496 * @arg @ref LL_DMAMUX_CHANNEL_3
497 * @arg @ref LL_DMAMUX_CHANNEL_4
498 * @arg @ref LL_DMAMUX_CHANNEL_5
499 * @arg @ref LL_DMAMUX_CHANNEL_6
500 *
501 * @arg All the next values are only available on chip which support DMA2:
502 * @arg @ref LL_DMAMUX_CHANNEL_7
503 * @arg @ref LL_DMAMUX_CHANNEL_8
504 * @arg @ref LL_DMAMUX_CHANNEL_9
505 * @arg @ref LL_DMAMUX_CHANNEL_10
506 * @arg @ref LL_DMAMUX_CHANNEL_11
507 * @arg @ref LL_DMAMUX_CHANNEL_12
508 * @arg @ref LL_DMAMUX_CHANNEL_13
509 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
510 * @retval None
511 */
LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t RequestNb)512 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
513 {
514 (void)(DMAMUXx);
515 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
516 }
517
518 /**
519 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
520 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
521 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
522 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
523 * @param DMAMUXx DMAMUXx Instance
524 * @param Channel This parameter can be one of the following values:
525 * @arg @ref LL_DMAMUX_CHANNEL_0
526 * @arg @ref LL_DMAMUX_CHANNEL_1
527 * @arg @ref LL_DMAMUX_CHANNEL_2
528 * @arg @ref LL_DMAMUX_CHANNEL_3
529 * @arg @ref LL_DMAMUX_CHANNEL_4
530 * @arg @ref LL_DMAMUX_CHANNEL_5
531 * @arg @ref LL_DMAMUX_CHANNEL_6
532 *
533 * @arg All the next values are only available on chip which support DMA2:
534 * @arg @ref LL_DMAMUX_CHANNEL_7
535 * @arg @ref LL_DMAMUX_CHANNEL_8
536 * @arg @ref LL_DMAMUX_CHANNEL_9
537 * @arg @ref LL_DMAMUX_CHANNEL_10
538 * @arg @ref LL_DMAMUX_CHANNEL_11
539 * @arg @ref LL_DMAMUX_CHANNEL_12
540 * @arg @ref LL_DMAMUX_CHANNEL_13
541 * @retval Between Min_Data = 1 and Max_Data = 32
542 */
LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)543 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
544 {
545 (void)(DMAMUXx);
546 return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
547 }
548
549 /**
550 * @brief Set the polarity of the signal on which the DMA request is synchronized.
551 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
552 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
553 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
554 * @param DMAMUXx DMAMUXx Instance
555 * @param Channel This parameter can be one of the following values:
556 * @arg @ref LL_DMAMUX_CHANNEL_0
557 * @arg @ref LL_DMAMUX_CHANNEL_1
558 * @arg @ref LL_DMAMUX_CHANNEL_2
559 * @arg @ref LL_DMAMUX_CHANNEL_3
560 * @arg @ref LL_DMAMUX_CHANNEL_4
561 * @arg @ref LL_DMAMUX_CHANNEL_5
562 * @arg @ref LL_DMAMUX_CHANNEL_6
563 *
564 * @arg All the next values are only available on chip which support DMA2:
565 * @arg @ref LL_DMAMUX_CHANNEL_7
566 * @arg @ref LL_DMAMUX_CHANNEL_8
567 * @arg @ref LL_DMAMUX_CHANNEL_9
568 * @arg @ref LL_DMAMUX_CHANNEL_10
569 * @arg @ref LL_DMAMUX_CHANNEL_11
570 * @arg @ref LL_DMAMUX_CHANNEL_12
571 * @arg @ref LL_DMAMUX_CHANNEL_13
572 * @param Polarity This parameter can be one of the following values:
573 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
574 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
575 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
576 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
577 * @retval None
578 */
LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Polarity)579 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
580 {
581 (void)(DMAMUXx);
582 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
583 }
584
585 /**
586 * @brief Get the polarity of the signal on which the DMA request is synchronized.
587 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
588 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
589 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
590 * @param DMAMUXx DMAMUXx Instance
591 * @param Channel This parameter can be one of the following values:
592 * @arg @ref LL_DMAMUX_CHANNEL_0
593 * @arg @ref LL_DMAMUX_CHANNEL_1
594 * @arg @ref LL_DMAMUX_CHANNEL_2
595 * @arg @ref LL_DMAMUX_CHANNEL_3
596 * @arg @ref LL_DMAMUX_CHANNEL_4
597 * @arg @ref LL_DMAMUX_CHANNEL_5
598 * @arg @ref LL_DMAMUX_CHANNEL_6
599 *
600 * @arg All the next values are only available on chip which support DMA2:
601 * @arg @ref LL_DMAMUX_CHANNEL_7
602 * @arg @ref LL_DMAMUX_CHANNEL_8
603 * @arg @ref LL_DMAMUX_CHANNEL_9
604 * @arg @ref LL_DMAMUX_CHANNEL_10
605 * @arg @ref LL_DMAMUX_CHANNEL_11
606 * @arg @ref LL_DMAMUX_CHANNEL_12
607 * @arg @ref LL_DMAMUX_CHANNEL_13
608 * @retval Returned value can be one of the following values:
609 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
610 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
611 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
612 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
613 */
LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)614 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
615 {
616 (void)(DMAMUXx);
617 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
618 }
619
620 /**
621 * @brief Enable the Event Generation on DMAMUX channel x.
622 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
623 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
624 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
625 * @param DMAMUXx DMAMUXx Instance
626 * @param Channel This parameter can be one of the following values:
627 * @arg @ref LL_DMAMUX_CHANNEL_0
628 * @arg @ref LL_DMAMUX_CHANNEL_1
629 * @arg @ref LL_DMAMUX_CHANNEL_2
630 * @arg @ref LL_DMAMUX_CHANNEL_3
631 * @arg @ref LL_DMAMUX_CHANNEL_4
632 * @arg @ref LL_DMAMUX_CHANNEL_5
633 * @arg @ref LL_DMAMUX_CHANNEL_6
634 *
635 * @arg All the next values are only available on chip which support DMA2:
636 * @arg @ref LL_DMAMUX_CHANNEL_7
637 * @arg @ref LL_DMAMUX_CHANNEL_8
638 * @arg @ref LL_DMAMUX_CHANNEL_9
639 * @arg @ref LL_DMAMUX_CHANNEL_10
640 * @arg @ref LL_DMAMUX_CHANNEL_11
641 * @arg @ref LL_DMAMUX_CHANNEL_12
642 * @arg @ref LL_DMAMUX_CHANNEL_13
643 * @retval None
644 */
LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)645 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
646 {
647 (void)(DMAMUXx);
648 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
649 }
650
651 /**
652 * @brief Disable the Event Generation on DMAMUX channel x.
653 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
654 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
655 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
656 * @param DMAMUXx DMAMUXx Instance
657 * @param Channel This parameter can be one of the following values:
658 * @arg @ref LL_DMAMUX_CHANNEL_0
659 * @arg @ref LL_DMAMUX_CHANNEL_1
660 * @arg @ref LL_DMAMUX_CHANNEL_2
661 * @arg @ref LL_DMAMUX_CHANNEL_3
662 * @arg @ref LL_DMAMUX_CHANNEL_4
663 * @arg @ref LL_DMAMUX_CHANNEL_5
664 * @arg @ref LL_DMAMUX_CHANNEL_6
665 *
666 * @arg All the next values are only available on chip which support DMA2:
667 * @arg @ref LL_DMAMUX_CHANNEL_7
668 * @arg @ref LL_DMAMUX_CHANNEL_8
669 * @arg @ref LL_DMAMUX_CHANNEL_9
670 * @arg @ref LL_DMAMUX_CHANNEL_10
671 * @arg @ref LL_DMAMUX_CHANNEL_11
672 * @arg @ref LL_DMAMUX_CHANNEL_12
673 * @arg @ref LL_DMAMUX_CHANNEL_13
674 * @retval None
675 */
LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)676 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
677 {
678 (void)(DMAMUXx);
679 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
680 }
681
682 /**
683 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
684 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
685 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
686 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
687 * @param DMAMUXx DMAMUXx Instance
688 * @param Channel This parameter can be one of the following values:
689 * @arg @ref LL_DMAMUX_CHANNEL_0
690 * @arg @ref LL_DMAMUX_CHANNEL_1
691 * @arg @ref LL_DMAMUX_CHANNEL_2
692 * @arg @ref LL_DMAMUX_CHANNEL_3
693 * @arg @ref LL_DMAMUX_CHANNEL_4
694 * @arg @ref LL_DMAMUX_CHANNEL_5
695 * @arg @ref LL_DMAMUX_CHANNEL_6
696 *
697 * @arg All the next values are only available on chip which support DMA2:
698 * @arg @ref LL_DMAMUX_CHANNEL_7
699 * @arg @ref LL_DMAMUX_CHANNEL_8
700 * @arg @ref LL_DMAMUX_CHANNEL_9
701 * @arg @ref LL_DMAMUX_CHANNEL_10
702 * @arg @ref LL_DMAMUX_CHANNEL_11
703 * @arg @ref LL_DMAMUX_CHANNEL_12
704 * @arg @ref LL_DMAMUX_CHANNEL_13
705 * @retval State of bit (1 or 0).
706 */
LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)707 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
708 {
709 (void)(DMAMUXx);
710 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
711 }
712
713 /**
714 * @brief Enable the synchronization mode.
715 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
716 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
717 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
718 * @param DMAMUXx DMAMUXx Instance
719 * @param Channel This parameter can be one of the following values:
720 * @arg @ref LL_DMAMUX_CHANNEL_0
721 * @arg @ref LL_DMAMUX_CHANNEL_1
722 * @arg @ref LL_DMAMUX_CHANNEL_2
723 * @arg @ref LL_DMAMUX_CHANNEL_3
724 * @arg @ref LL_DMAMUX_CHANNEL_4
725 * @arg @ref LL_DMAMUX_CHANNEL_5
726 * @arg @ref LL_DMAMUX_CHANNEL_6
727 *
728 * @arg All the next values are only available on chip which support DMA2:
729 * @arg @ref LL_DMAMUX_CHANNEL_7
730 * @arg @ref LL_DMAMUX_CHANNEL_8
731 * @arg @ref LL_DMAMUX_CHANNEL_9
732 * @arg @ref LL_DMAMUX_CHANNEL_10
733 * @arg @ref LL_DMAMUX_CHANNEL_11
734 * @arg @ref LL_DMAMUX_CHANNEL_12
735 * @arg @ref LL_DMAMUX_CHANNEL_13
736 * @retval None
737 */
LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)738 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
739 {
740 (void)(DMAMUXx);
741 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
742 }
743
744 /**
745 * @brief Disable the synchronization mode.
746 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
747 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
748 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
749 * @param DMAMUXx DMAMUXx Instance
750 * @param Channel This parameter can be one of the following values:
751 * @arg @ref LL_DMAMUX_CHANNEL_0
752 * @arg @ref LL_DMAMUX_CHANNEL_1
753 * @arg @ref LL_DMAMUX_CHANNEL_2
754 * @arg @ref LL_DMAMUX_CHANNEL_3
755 * @arg @ref LL_DMAMUX_CHANNEL_4
756 * @arg @ref LL_DMAMUX_CHANNEL_5
757 * @arg @ref LL_DMAMUX_CHANNEL_6
758 *
759 * @arg All the next values are only available on chip which support DMA2:
760 * @arg @ref LL_DMAMUX_CHANNEL_7
761 * @arg @ref LL_DMAMUX_CHANNEL_8
762 * @arg @ref LL_DMAMUX_CHANNEL_9
763 * @arg @ref LL_DMAMUX_CHANNEL_10
764 * @arg @ref LL_DMAMUX_CHANNEL_11
765 * @arg @ref LL_DMAMUX_CHANNEL_12
766 * @arg @ref LL_DMAMUX_CHANNEL_13
767 * @retval None
768 */
LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)769 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
770 {
771 (void)(DMAMUXx);
772 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
773 }
774
775 /**
776 * @brief Check if the synchronization mode is enabled or disabled.
777 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
778 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
779 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
780 * @param DMAMUXx DMAMUXx Instance
781 * @param Channel This parameter can be one of the following values:
782 * @arg @ref LL_DMAMUX_CHANNEL_0
783 * @arg @ref LL_DMAMUX_CHANNEL_1
784 * @arg @ref LL_DMAMUX_CHANNEL_2
785 * @arg @ref LL_DMAMUX_CHANNEL_3
786 * @arg @ref LL_DMAMUX_CHANNEL_4
787 * @arg @ref LL_DMAMUX_CHANNEL_5
788 * @arg @ref LL_DMAMUX_CHANNEL_6
789 *
790 * @arg All the next values are only available on chip which support DMA2:
791 * @arg @ref LL_DMAMUX_CHANNEL_7
792 * @arg @ref LL_DMAMUX_CHANNEL_8
793 * @arg @ref LL_DMAMUX_CHANNEL_9
794 * @arg @ref LL_DMAMUX_CHANNEL_10
795 * @arg @ref LL_DMAMUX_CHANNEL_11
796 * @arg @ref LL_DMAMUX_CHANNEL_12
797 * @arg @ref LL_DMAMUX_CHANNEL_13
798 * @retval State of bit (1 or 0).
799 */
LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)800 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
801 {
802 (void)(DMAMUXx);
803 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
804 }
805
806 /**
807 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
808 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
809 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
810 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
811 * @param DMAMUXx DMAMUXx Instance
812 * @param Channel This parameter can be one of the following values:
813 * @arg @ref LL_DMAMUX_CHANNEL_0
814 * @arg @ref LL_DMAMUX_CHANNEL_1
815 * @arg @ref LL_DMAMUX_CHANNEL_2
816 * @arg @ref LL_DMAMUX_CHANNEL_3
817 * @arg @ref LL_DMAMUX_CHANNEL_4
818 * @arg @ref LL_DMAMUX_CHANNEL_5
819 * @arg @ref LL_DMAMUX_CHANNEL_6
820 *
821 * @arg All the next values are only available on chip which support DMA2:
822 * @arg @ref LL_DMAMUX_CHANNEL_7
823 * @arg @ref LL_DMAMUX_CHANNEL_8
824 * @arg @ref LL_DMAMUX_CHANNEL_9
825 * @arg @ref LL_DMAMUX_CHANNEL_10
826 * @arg @ref LL_DMAMUX_CHANNEL_11
827 * @arg @ref LL_DMAMUX_CHANNEL_12
828 * @arg @ref LL_DMAMUX_CHANNEL_13
829 * @param SyncID This parameter can be one of the following values:
830 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
831 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
832 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
833 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
834 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
835 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
836 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
837 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
838 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
839 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
840 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
841 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
842 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
843 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
844 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
845 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
846 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
847 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
848 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
849 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
850 * @retval None
851 */
LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t SyncID)852 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
853 {
854 (void)(DMAMUXx);
855 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
856 }
857
858 /**
859 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
860 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
861 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
862 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
863 * @param DMAMUXx DMAMUXx Instance
864 * @param Channel This parameter can be one of the following values:
865 * @arg @ref LL_DMAMUX_CHANNEL_0
866 * @arg @ref LL_DMAMUX_CHANNEL_1
867 * @arg @ref LL_DMAMUX_CHANNEL_2
868 * @arg @ref LL_DMAMUX_CHANNEL_3
869 * @arg @ref LL_DMAMUX_CHANNEL_4
870 * @arg @ref LL_DMAMUX_CHANNEL_5
871 * @arg @ref LL_DMAMUX_CHANNEL_6
872 *
873 * @arg All the next values are only available on chip which support DMA2:
874 * @arg @ref LL_DMAMUX_CHANNEL_7
875 * @arg @ref LL_DMAMUX_CHANNEL_8
876 * @arg @ref LL_DMAMUX_CHANNEL_9
877 * @arg @ref LL_DMAMUX_CHANNEL_10
878 * @arg @ref LL_DMAMUX_CHANNEL_11
879 * @arg @ref LL_DMAMUX_CHANNEL_12
880 * @arg @ref LL_DMAMUX_CHANNEL_13
881 * @retval Returned value can be one of the following values:
882 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
883 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
884 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
885 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
886 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
887 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
888 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
889 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
890 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
891 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
892 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
893 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
894 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
895 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
896 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
897 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
898 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
899 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
900 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
901 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
902 */
LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)903 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
904 {
905 (void)(DMAMUXx);
906 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
907 }
908
909 /**
910 * @brief Enable the Request Generator.
911 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
912 * @param DMAMUXx DMAMUXx Instance
913 * @param RequestGenChannel This parameter can be one of the following values:
914 * @arg @ref LL_DMAMUX_REQ_GEN_0
915 * @arg @ref LL_DMAMUX_REQ_GEN_1
916 * @arg @ref LL_DMAMUX_REQ_GEN_2
917 * @arg @ref LL_DMAMUX_REQ_GEN_3
918 * @retval None
919 */
LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)920 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
921 {
922 (void)(DMAMUXx);
923 SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
924 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
925 }
926
927 /**
928 * @brief Disable the Request Generator.
929 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
930 * @param DMAMUXx DMAMUXx Instance
931 * @param RequestGenChannel This parameter can be one of the following values:
932 * @arg @ref LL_DMAMUX_REQ_GEN_0
933 * @arg @ref LL_DMAMUX_REQ_GEN_1
934 * @arg @ref LL_DMAMUX_REQ_GEN_2
935 * @arg @ref LL_DMAMUX_REQ_GEN_3
936 * @retval None
937 */
LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)938 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
939 {
940 (void)(DMAMUXx);
941 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
942 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
943 }
944
945 /**
946 * @brief Check if the Request Generator is enabled or disabled.
947 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
948 * @param DMAMUXx DMAMUXx Instance
949 * @param RequestGenChannel This parameter can be one of the following values:
950 * @arg @ref LL_DMAMUX_REQ_GEN_0
951 * @arg @ref LL_DMAMUX_REQ_GEN_1
952 * @arg @ref LL_DMAMUX_REQ_GEN_2
953 * @arg @ref LL_DMAMUX_REQ_GEN_3
954 * @retval State of bit (1 or 0).
955 */
LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)956 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
957 {
958 (void)(DMAMUXx);
959 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
960 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
961 }
962
963 /**
964 * @brief Set the polarity of the signal on which the DMA request is generated.
965 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
966 * @param DMAMUXx DMAMUXx Instance
967 * @param RequestGenChannel This parameter can be one of the following values:
968 * @arg @ref LL_DMAMUX_REQ_GEN_0
969 * @arg @ref LL_DMAMUX_REQ_GEN_1
970 * @arg @ref LL_DMAMUX_REQ_GEN_2
971 * @arg @ref LL_DMAMUX_REQ_GEN_3
972 * @param Polarity This parameter can be one of the following values:
973 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
974 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
975 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
976 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
977 * @retval None
978 */
LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t Polarity)979 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
980 uint32_t Polarity)
981 {
982 (void)(DMAMUXx);
983 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
984 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
985 }
986
987 /**
988 * @brief Get the polarity of the signal on which the DMA request is generated.
989 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
990 * @param DMAMUXx DMAMUXx Instance
991 * @param RequestGenChannel This parameter can be one of the following values:
992 * @arg @ref LL_DMAMUX_REQ_GEN_0
993 * @arg @ref LL_DMAMUX_REQ_GEN_1
994 * @arg @ref LL_DMAMUX_REQ_GEN_2
995 * @arg @ref LL_DMAMUX_REQ_GEN_3
996 * @retval Returned value can be one of the following values:
997 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
998 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
999 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1000 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1001 */
LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1002 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1003 {
1004 (void)(DMAMUXx);
1005 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
1006 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
1007 }
1008
1009 /**
1010 * @brief Set the number of DMA request that will be autorized after a generation event.
1011 * @note This field can only be written when Generator is disabled.
1012 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1013 * @param DMAMUXx DMAMUXx Instance
1014 * @param RequestGenChannel This parameter can be one of the following values:
1015 * @arg @ref LL_DMAMUX_REQ_GEN_0
1016 * @arg @ref LL_DMAMUX_REQ_GEN_1
1017 * @arg @ref LL_DMAMUX_REQ_GEN_2
1018 * @arg @ref LL_DMAMUX_REQ_GEN_3
1019 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1020 * @retval None
1021 */
LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestNb)1022 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1023 uint32_t RequestNb)
1024 {
1025 (void)(DMAMUXx);
1026 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1027 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1028 }
1029
1030 /**
1031 * @brief Get the number of DMA request that will be autorized after a generation event.
1032 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1033 * @param DMAMUXx DMAMUXx Instance
1034 * @param RequestGenChannel This parameter can be one of the following values:
1035 * @arg @ref LL_DMAMUX_REQ_GEN_0
1036 * @arg @ref LL_DMAMUX_REQ_GEN_1
1037 * @arg @ref LL_DMAMUX_REQ_GEN_2
1038 * @arg @ref LL_DMAMUX_REQ_GEN_3
1039 * @retval Between Min_Data = 1 and Max_Data = 32
1040 */
LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1041 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1042 {
1043 (void)(DMAMUXx);
1044 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
1045 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1046 }
1047
1048 /**
1049 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1050 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1051 * @param DMAMUXx DMAMUXx Instance
1052 * @param RequestGenChannel This parameter can be one of the following values:
1053 * @arg @ref LL_DMAMUX_REQ_GEN_0
1054 * @arg @ref LL_DMAMUX_REQ_GEN_1
1055 * @arg @ref LL_DMAMUX_REQ_GEN_2
1056 * @arg @ref LL_DMAMUX_REQ_GEN_3
1057 * @param RequestSignalID This parameter can be one of the following values:
1058 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1059 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1060 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1061 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1062 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1063 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1064 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1065 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1066 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1067 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1068 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1069 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1070 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1071 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1072 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1073 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1074 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1075 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1076 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1077 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1078 * @retval None
1079 */
LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestSignalID)1080 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1081 uint32_t RequestSignalID)
1082 {
1083 (void)(DMAMUXx);
1084 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1085 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1086 }
1087
1088 /**
1089 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1090 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1091 * @param DMAMUXx DMAMUXx Instance
1092 * @param RequestGenChannel This parameter can be one of the following values:
1093 * @arg @ref LL_DMAMUX_REQ_GEN_0
1094 * @arg @ref LL_DMAMUX_REQ_GEN_1
1095 * @arg @ref LL_DMAMUX_REQ_GEN_2
1096 * @arg @ref LL_DMAMUX_REQ_GEN_3
1097 * @retval Returned value can be one of the following values:
1098 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1099 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1100 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1101 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1102 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1103 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1104 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1105 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1106 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1107 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1108 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1109 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1110 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1111 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1112 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1113 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1114 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1115 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1116 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1117 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1118 */
LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1119 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1120 {
1121 (void)(DMAMUXx);
1122 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
1123 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
1124 }
1125
1126 /**
1127 * @}
1128 */
1129
1130 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1131 * @{
1132 */
1133
1134 /**
1135 * @brief Get Synchronization Event Overrun Flag Channel 0.
1136 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1137 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1138 * @retval State of bit (1 or 0).
1139 */
LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1140 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1141 {
1142 (void)(DMAMUXx);
1143 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1144 }
1145
1146 /**
1147 * @brief Get Synchronization Event Overrun Flag Channel 1.
1148 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1149 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1150 * @retval State of bit (1 or 0).
1151 */
LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1152 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1153 {
1154 (void)(DMAMUXx);
1155 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1156 }
1157
1158 /**
1159 * @brief Get Synchronization Event Overrun Flag Channel 2.
1160 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1161 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1162 * @retval State of bit (1 or 0).
1163 */
LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1164 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1165 {
1166 (void)(DMAMUXx);
1167 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1168 }
1169
1170 /**
1171 * @brief Get Synchronization Event Overrun Flag Channel 3.
1172 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1173 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1174 * @retval State of bit (1 or 0).
1175 */
LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1176 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1177 {
1178 (void)(DMAMUXx);
1179 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1180 }
1181
1182 /**
1183 * @brief Get Synchronization Event Overrun Flag Channel 4.
1184 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1185 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1186 * @retval State of bit (1 or 0).
1187 */
LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1188 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1189 {
1190 (void)(DMAMUXx);
1191 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1192 }
1193
1194 /**
1195 * @brief Get Synchronization Event Overrun Flag Channel 5.
1196 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1197 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1198 * @retval State of bit (1 or 0).
1199 */
LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1200 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1201 {
1202 (void)(DMAMUXx);
1203 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1204 }
1205
1206 /**
1207 * @brief Get Synchronization Event Overrun Flag Channel 6.
1208 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1209 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1210 * @retval State of bit (1 or 0).
1211 */
LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1212 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1213 {
1214 (void)(DMAMUXx);
1215 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1216 }
1217
1218 #if defined(DMAMUX1_Channel7)
1219 /**
1220 * @brief Get Synchronization Event Overrun Flag Channel 7.
1221 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1222 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1223 * @retval State of bit (1 or 0).
1224 */
LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1225 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1226 {
1227 (void)(DMAMUXx);
1228 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1229 }
1230
1231 #endif /* DMAMUX1_Channel7 */
1232 #if defined(DMAMUX1_Channel8)
1233 /**
1234 * @brief Get Synchronization Event Overrun Flag Channel 8.
1235 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1236 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1237 * @retval State of bit (1 or 0).
1238 */
LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1239 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1240 {
1241 (void)(DMAMUXx);
1242 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1243 }
1244
1245 #endif /* DMAMUX1_Channel8 */
1246 #if defined(DMAMUX1_Channel9)
1247 /**
1248 * @brief Get Synchronization Event Overrun Flag Channel 9.
1249 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1250 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1251 * @retval State of bit (1 or 0).
1252 */
LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1253 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1254 {
1255 (void)(DMAMUXx);
1256 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1257 }
1258
1259 #endif /* DMAMUX1_Channel9 */
1260 #if defined(DMAMUX1_Channel10)
1261 /**
1262 * @brief Get Synchronization Event Overrun Flag Channel 10.
1263 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1264 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1265 * @retval State of bit (1 or 0).
1266 */
LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1267 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1268 {
1269 (void)(DMAMUXx);
1270 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1271 }
1272
1273 #endif /* DMAMUX1_Channel10 */
1274 #if defined(DMAMUX1_Channel11)
1275 /**
1276 * @brief Get Synchronization Event Overrun Flag Channel 11.
1277 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1278 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1279 * @retval State of bit (1 or 0).
1280 */
LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1281 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1282 {
1283 (void)(DMAMUXx);
1284 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1285 }
1286
1287 #endif /* DMAMUX1_Channel11 */
1288 #if defined(DMAMUX1_Channel12)
1289 /**
1290 * @brief Get Synchronization Event Overrun Flag Channel 12.
1291 * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
1292 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1293 * @retval State of bit (1 or 0).
1294 */
LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef * DMAMUXx)1295 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1296 {
1297 (void)(DMAMUXx);
1298 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
1299 }
1300
1301 #endif /* DMAMUX1_Channel12 */
1302 #if defined(DMAMUX1_Channel13)
1303 /**
1304 * @brief Get Synchronization Event Overrun Flag Channel 13.
1305 * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
1306 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1307 * @retval State of bit (1 or 0).
1308 */
LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef * DMAMUXx)1309 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1310 {
1311 (void)(DMAMUXx);
1312 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
1313 }
1314
1315 #endif /* DMAMUX1_Channel13 */
1316 /**
1317 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1318 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1319 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1320 * @retval State of bit (1 or 0).
1321 */
LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1322 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1323 {
1324 (void)(DMAMUXx);
1325 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1326 }
1327
1328 /**
1329 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1330 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1331 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1332 * @retval State of bit (1 or 0).
1333 */
LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1334 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1335 {
1336 (void)(DMAMUXx);
1337 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1338 }
1339
1340 /**
1341 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1342 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1343 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1344 * @retval State of bit (1 or 0).
1345 */
LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1346 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1347 {
1348 (void)(DMAMUXx);
1349 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1350 }
1351
1352 /**
1353 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1354 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1355 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1356 * @retval State of bit (1 or 0).
1357 */
LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1358 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1359 {
1360 (void)(DMAMUXx);
1361 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1362 }
1363
1364 /**
1365 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1366 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1367 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1368 * @retval None
1369 */
LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1370 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1371 {
1372 (void)(DMAMUXx);
1373 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
1374 }
1375
1376 /**
1377 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1378 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1379 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1380 * @retval None
1381 */
LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1382 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1383 {
1384 (void)(DMAMUXx);
1385 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
1386 }
1387
1388 /**
1389 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1390 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1391 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1392 * @retval None
1393 */
LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1394 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1395 {
1396 (void)(DMAMUXx);
1397 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
1398 }
1399
1400 /**
1401 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1402 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1403 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1404 * @retval None
1405 */
LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1406 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1407 {
1408 (void)(DMAMUXx);
1409 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
1410 }
1411
1412 /**
1413 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1414 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1415 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1416 * @retval None
1417 */
LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1418 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1419 {
1420 (void)(DMAMUXx);
1421 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
1422 }
1423
1424 /**
1425 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1426 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1427 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1428 * @retval None
1429 */
LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1430 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1431 {
1432 (void)(DMAMUXx);
1433 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
1434 }
1435
1436 /**
1437 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1438 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1439 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1440 * @retval None
1441 */
LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1442 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1443 {
1444 (void)(DMAMUXx);
1445 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
1446 }
1447
1448 #if defined(DMAMUX1_Channel7)
1449 /**
1450 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1451 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1452 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1453 * @retval None
1454 */
LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1455 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1456 {
1457 (void)(DMAMUXx);
1458 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
1459 }
1460
1461 #endif /* DMAMUX1_Channel7 */
1462 #if defined(DMAMUX1_Channel8)
1463 /**
1464 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1465 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1466 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1467 * @retval None
1468 */
LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1469 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1470 {
1471 (void)(DMAMUXx);
1472 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
1473 }
1474
1475 #endif /* DMAMUX1_Channel8 */
1476 #if defined(DMAMUX1_Channel9)
1477 /**
1478 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1479 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1480 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1481 * @retval None
1482 */
LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1483 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1484 {
1485 (void)(DMAMUXx);
1486 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
1487 }
1488
1489 #endif /* DMAMUX1_Channel9 */
1490 #if defined(DMAMUX1_Channel10)
1491 /**
1492 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1493 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1494 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1495 * @retval None
1496 */
LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1497 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1498 {
1499 (void)(DMAMUXx);
1500 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
1501 }
1502
1503 #endif /* DMAMUX1_Channel10 */
1504 #if defined(DMAMUX1_Channel11)
1505 /**
1506 * @brief Clear Synchronization Event Overrun Flag Channel 11.
1507 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
1508 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1509 * @retval None
1510 */
LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1511 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1512 {
1513 (void)(DMAMUXx);
1514 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
1515 }
1516
1517 #endif /* DMAMUX1_Channel11 */
1518 #if defined(DMAMUX1_Channel12)
1519 /**
1520 * @brief Clear Synchronization Event Overrun Flag Channel 12.
1521 * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
1522 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1523 * @retval None
1524 */
LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef * DMAMUXx)1525 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1526 {
1527 (void)(DMAMUXx);
1528 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
1529 }
1530
1531 #endif /* DMAMUX1_Channel12 */
1532 #if defined(DMAMUX1_Channel13)
1533 /**
1534 * @brief Clear Synchronization Event Overrun Flag Channel 13.
1535 * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
1536 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1537 * @retval None
1538 */
LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef * DMAMUXx)1539 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1540 {
1541 (void)(DMAMUXx);
1542 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
1543 }
1544
1545 #endif /* DMAMUX1_Channel13 */
1546 /**
1547 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
1548 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
1549 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1550 * @retval None
1551 */
LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1552 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1553 {
1554 (void)(DMAMUXx);
1555 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
1556 }
1557
1558 /**
1559 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
1560 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
1561 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1562 * @retval None
1563 */
LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1564 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1565 {
1566 (void)(DMAMUXx);
1567 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
1568 }
1569
1570 /**
1571 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
1572 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
1573 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1574 * @retval None
1575 */
LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1576 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1577 {
1578 (void)(DMAMUXx);
1579 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
1580 }
1581
1582 /**
1583 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
1584 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
1585 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1586 * @retval None
1587 */
LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1588 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1589 {
1590 (void)(DMAMUXx);
1591 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
1592 }
1593
1594 /**
1595 * @}
1596 */
1597
1598 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
1599 * @{
1600 */
1601
1602 /**
1603 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1604 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1605 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
1606 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
1607 * @param DMAMUXx DMAMUXx Instance
1608 * @param Channel This parameter can be one of the following values:
1609 * @arg @ref LL_DMAMUX_CHANNEL_0
1610 * @arg @ref LL_DMAMUX_CHANNEL_1
1611 * @arg @ref LL_DMAMUX_CHANNEL_2
1612 * @arg @ref LL_DMAMUX_CHANNEL_3
1613 * @arg @ref LL_DMAMUX_CHANNEL_4
1614 * @arg @ref LL_DMAMUX_CHANNEL_5
1615 * @arg @ref LL_DMAMUX_CHANNEL_6
1616 *
1617 * @arg All the next values are only available on chip which support DMA2:
1618 * @arg @ref LL_DMAMUX_CHANNEL_7
1619 * @arg @ref LL_DMAMUX_CHANNEL_8
1620 * @arg @ref LL_DMAMUX_CHANNEL_9
1621 * @arg @ref LL_DMAMUX_CHANNEL_10
1622 * @arg @ref LL_DMAMUX_CHANNEL_11
1623 * @arg @ref LL_DMAMUX_CHANNEL_12
1624 * @arg @ref LL_DMAMUX_CHANNEL_13
1625 * @retval None
1626 */
LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1627 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1628 {
1629 (void)(DMAMUXx);
1630 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1631 }
1632
1633 /**
1634 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1635 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1636 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
1637 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
1638 * @param DMAMUXx DMAMUXx Instance
1639 * @param Channel This parameter can be one of the following values:
1640 * @arg @ref LL_DMAMUX_CHANNEL_0
1641 * @arg @ref LL_DMAMUX_CHANNEL_1
1642 * @arg @ref LL_DMAMUX_CHANNEL_2
1643 * @arg @ref LL_DMAMUX_CHANNEL_3
1644 * @arg @ref LL_DMAMUX_CHANNEL_4
1645 * @arg @ref LL_DMAMUX_CHANNEL_5
1646 * @arg @ref LL_DMAMUX_CHANNEL_6
1647 *
1648 * @arg All the next values are only available on chip which support DMA2:
1649 * @arg @ref LL_DMAMUX_CHANNEL_7
1650 * @arg @ref LL_DMAMUX_CHANNEL_8
1651 * @arg @ref LL_DMAMUX_CHANNEL_9
1652 * @arg @ref LL_DMAMUX_CHANNEL_10
1653 * @arg @ref LL_DMAMUX_CHANNEL_11
1654 * @arg @ref LL_DMAMUX_CHANNEL_12
1655 * @arg @ref LL_DMAMUX_CHANNEL_13
1656 * @retval None
1657 */
LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1658 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1659 {
1660 (void)(DMAMUXx);
1661 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1662 }
1663
1664 /**
1665 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1666 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1667 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
1668 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
1669 * @param DMAMUXx DMAMUXx Instance
1670 * @param Channel This parameter can be one of the following values:
1671 * @arg @ref LL_DMAMUX_CHANNEL_0
1672 * @arg @ref LL_DMAMUX_CHANNEL_1
1673 * @arg @ref LL_DMAMUX_CHANNEL_2
1674 * @arg @ref LL_DMAMUX_CHANNEL_3
1675 * @arg @ref LL_DMAMUX_CHANNEL_4
1676 * @arg @ref LL_DMAMUX_CHANNEL_5
1677 * @arg @ref LL_DMAMUX_CHANNEL_6
1678 *
1679 * @arg All the next values are only available on chip which support DMA2:
1680 * @arg @ref LL_DMAMUX_CHANNEL_7
1681 * @arg @ref LL_DMAMUX_CHANNEL_8
1682 * @arg @ref LL_DMAMUX_CHANNEL_9
1683 * @arg @ref LL_DMAMUX_CHANNEL_10
1684 * @arg @ref LL_DMAMUX_CHANNEL_11
1685 * @arg @ref LL_DMAMUX_CHANNEL_12
1686 * @arg @ref LL_DMAMUX_CHANNEL_13
1687 * @retval State of bit (1 or 0).
1688 */
LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1689 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1690 {
1691 (void)(DMAMUXx);
1692 return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
1693 }
1694
1695 /**
1696 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1697 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
1698 * @param DMAMUXx DMAMUXx Instance
1699 * @param RequestGenChannel This parameter can be one of the following values:
1700 * @arg @ref LL_DMAMUX_REQ_GEN_0
1701 * @arg @ref LL_DMAMUX_REQ_GEN_1
1702 * @arg @ref LL_DMAMUX_REQ_GEN_2
1703 * @arg @ref LL_DMAMUX_REQ_GEN_3
1704 * @retval None
1705 */
LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1706 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1707 {
1708 (void)(DMAMUXx);
1709 SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1710 }
1711
1712 /**
1713 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1714 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
1715 * @param DMAMUXx DMAMUXx Instance
1716 * @param RequestGenChannel This parameter can be one of the following values:
1717 * @arg @ref LL_DMAMUX_REQ_GEN_0
1718 * @arg @ref LL_DMAMUX_REQ_GEN_1
1719 * @arg @ref LL_DMAMUX_REQ_GEN_2
1720 * @arg @ref LL_DMAMUX_REQ_GEN_3
1721 * @retval None
1722 */
LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1723 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1724 {
1725 (void)(DMAMUXx);
1726 CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1727 }
1728
1729 /**
1730 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1731 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
1732 * @param DMAMUXx DMAMUXx Instance
1733 * @param RequestGenChannel This parameter can be one of the following values:
1734 * @arg @ref LL_DMAMUX_REQ_GEN_0
1735 * @arg @ref LL_DMAMUX_REQ_GEN_1
1736 * @arg @ref LL_DMAMUX_REQ_GEN_2
1737 * @arg @ref LL_DMAMUX_REQ_GEN_3
1738 * @retval State of bit (1 or 0).
1739 */
LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1740 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1741 {
1742 (void)(DMAMUXx);
1743 return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
1744 }
1745
1746 /**
1747 * @}
1748 */
1749
1750 /**
1751 * @}
1752 */
1753
1754 /**
1755 * @}
1756 */
1757
1758 #endif /* DMAMUX1 */
1759
1760 /**
1761 * @}
1762 */
1763
1764 #ifdef __cplusplus
1765 }
1766 #endif
1767
1768 #endif /* STM32WBxx_LL_DMAMUX_H */
1769
