1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WBAxx_LL_TIM_H
21 #define __STM32WBAxx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x04U, /* 7: TIMx_CH4N */
55 0x38U, /* 8: TIMx_CH5 */
56 0x38U /* 9: TIMx_CH6 */
57
58 };
59
60 static const uint8_t SHIFT_TAB_OCxx[] =
61 {
62 0U, /* 0: OC1M, OC1FE, OC1PE */
63 0U, /* 1: - NA */
64 8U, /* 2: OC2M, OC2FE, OC2PE */
65 0U, /* 3: - NA */
66 0U, /* 4: OC3M, OC3FE, OC3PE */
67 0U, /* 5: - NA */
68 8U, /* 6: OC4M, OC4FE, OC4PE */
69 0U, /* 7: - NA */
70 0U, /* 8: OC5M, OC5FE, OC5PE */
71 8U /* 9: OC6M, OC6FE, OC6PE */
72 };
73
74 static const uint8_t SHIFT_TAB_ICxx[] =
75 {
76 0U, /* 0: CC1S, IC1PSC, IC1F */
77 0U, /* 1: - NA */
78 8U, /* 2: CC2S, IC2PSC, IC2F */
79 0U, /* 3: - NA */
80 0U, /* 4: CC3S, IC3PSC, IC3F */
81 0U, /* 5: - NA */
82 8U, /* 6: CC4S, IC4PSC, IC4F */
83 0U, /* 7: - NA */
84 0U, /* 8: - NA */
85 0U /* 9: - NA */
86 };
87
88 static const uint8_t SHIFT_TAB_CCxP[] =
89 {
90 0U, /* 0: CC1P */
91 2U, /* 1: CC1NP */
92 4U, /* 2: CC2P */
93 6U, /* 3: CC2NP */
94 8U, /* 4: CC3P */
95 10U, /* 5: CC3NP */
96 12U, /* 6: CC4P */
97 14U, /* 7: CC4NP */
98 16U, /* 8: CC5P */
99 20U /* 9: CC6P */
100 };
101
102 static const uint8_t SHIFT_TAB_OISx[] =
103 {
104 0U, /* 0: OIS1 */
105 1U, /* 1: OIS1N */
106 2U, /* 2: OIS2 */
107 3U, /* 3: OIS2N */
108 4U, /* 4: OIS3 */
109 5U, /* 5: OIS3N */
110 6U, /* 6: OIS4 */
111 7U, /* 7: OIS4N */
112 8U, /* 8: OIS5 */
113 10U /* 9: OIS6 */
114 };
115 /**
116 * @}
117 */
118
119 /* Private constants ---------------------------------------------------------*/
120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
121 * @{
122 */
123
124 /* Defines used for the bit position in the register and perform offsets */
125 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
126
127 /* Generic bit definitions for TIMx_AF1 register */
128 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
129 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
130
131
132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
133 #define DT_DELAY_1 ((uint8_t)0x7F)
134 #define DT_DELAY_2 ((uint8_t)0x3F)
135 #define DT_DELAY_3 ((uint8_t)0x1F)
136 #define DT_DELAY_4 ((uint8_t)0x1F)
137
138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
139 #define DT_RANGE_1 ((uint8_t)0x00)
140 #define DT_RANGE_2 ((uint8_t)0x80)
141 #define DT_RANGE_3 ((uint8_t)0xC0)
142 #define DT_RANGE_4 ((uint8_t)0xE0)
143
144 /** Legacy definitions for compatibility purpose
145 @cond 0
146 */
147 /**
148 @endcond
149 */
150
151 #define OCREF_CLEAR_SELECT_POS (28U)
152 #define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */
153 /**
154 * @}
155 */
156
157 /* Private macros ------------------------------------------------------------*/
158 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
159 * @{
160 */
161 /** @brief Convert channel id into channel index.
162 * @param __CHANNEL__ This parameter can be one of the following values:
163 * @arg @ref LL_TIM_CHANNEL_CH1
164 * @arg @ref LL_TIM_CHANNEL_CH1N
165 * @arg @ref LL_TIM_CHANNEL_CH2
166 * @arg @ref LL_TIM_CHANNEL_CH2N
167 * @arg @ref LL_TIM_CHANNEL_CH3
168 * @arg @ref LL_TIM_CHANNEL_CH3N
169 * @arg @ref LL_TIM_CHANNEL_CH4
170 * @arg @ref LL_TIM_CHANNEL_CH4N
171 * @arg @ref LL_TIM_CHANNEL_CH5
172 * @arg @ref LL_TIM_CHANNEL_CH6
173 * @retval none
174 */
175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
176 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
185
186 /** @brief Calculate the deadtime sampling period(in ps).
187 * @param __TIMCLK__ timer input clock frequency (in Hz).
188 * @param __CKD__ This parameter can be one of the following values:
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
192 * @retval none
193 */
194 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
195 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
196 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
197 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
198 /**
199 * @}
200 */
201
202
203 /* Exported types ------------------------------------------------------------*/
204 #if defined(USE_FULL_LL_DRIVER)
205 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
206 * @{
207 */
208
209 /**
210 * @brief TIM Time Base configuration structure definition.
211 */
212 typedef struct
213 {
214 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
215 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
216
217 This feature can be modified afterwards using unitary function
218 @ref LL_TIM_SetPrescaler().*/
219
220 uint32_t CounterMode; /*!< Specifies the counter mode.
221 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetCounterMode().*/
225
226 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
227 Auto-Reload Register at the next update event.
228 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
229 Some timer instances may support 32 bits counters. In that case this parameter must
230 be a number between 0x0000 and 0xFFFFFFFF.
231
232 This feature can be modified afterwards using unitary function
233 @ref LL_TIM_SetAutoReload().*/
234
235 uint32_t ClockDivision; /*!< Specifies the clock division.
236 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetClockDivision().*/
240
241 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
242 reaches zero, an update event is generated and counting restarts
243 from the RCR value (N).
244 This means in PWM mode that (N+1) corresponds to:
245 - the number of PWM periods in edge-aligned mode
246 - the number of half PWM period in center-aligned mode
247 GP timers: this parameter must be a number between Min_Data = 0x00 and
248 Max_Data = 0xFF.
249 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
250 Max_Data = 0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 @ref LL_TIM_SetRepetitionCounter().*/
254 } LL_TIM_InitTypeDef;
255
256 /**
257 * @brief TIM Output Compare configuration structure definition.
258 */
259 typedef struct
260 {
261 uint32_t OCMode; /*!< Specifies the output mode.
262 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetMode().*/
266
267 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
268 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
269
270 This feature can be modified afterwards using unitary functions
271 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
272
273 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
274 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
275
276 This feature can be modified afterwards using unitary functions
277 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
278
279 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
280 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
281
282 This feature can be modified afterwards using unitary function
283 LL_TIM_OC_SetCompareCHx (x=1..6).*/
284
285 uint32_t OCPolarity; /*!< Specifies the output polarity.
286 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
287
288 This feature can be modified afterwards using unitary function
289 @ref LL_TIM_OC_SetPolarity().*/
290
291 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
292 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_OC_SetPolarity().*/
296
297
298 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
299 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
300
301 This feature can be modified afterwards using unitary function
302 @ref LL_TIM_OC_SetIdleState().*/
303
304 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetIdleState().*/
309 } LL_TIM_OC_InitTypeDef;
310
311 /**
312 * @brief TIM Input Capture configuration structure definition.
313 */
314
315 typedef struct
316 {
317
318 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
319 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
320
321 This feature can be modified afterwards using unitary function
322 @ref LL_TIM_IC_SetPolarity().*/
323
324 uint32_t ICActiveInput; /*!< Specifies the input.
325 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
326
327 This feature can be modified afterwards using unitary function
328 @ref LL_TIM_IC_SetActiveInput().*/
329
330 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
331 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetPrescaler().*/
335
336 uint32_t ICFilter; /*!< Specifies the input capture filter.
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetFilter().*/
341 } LL_TIM_IC_InitTypeDef;
342
343
344 /**
345 * @brief TIM Encoder interface configuration structure definition.
346 */
347 typedef struct
348 {
349 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
350 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_SetEncoderMode().*/
354
355 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
356 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetPolarity().*/
360
361 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
362 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetActiveInput().*/
366
367 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
368 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetPrescaler().*/
372
373 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
374 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetFilter().*/
378
379 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
380 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetPolarity().*/
384
385 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
386 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetActiveInput().*/
390
391 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
392 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetPrescaler().*/
396
397 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
398 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetFilter().*/
402
403 } LL_TIM_ENCODER_InitTypeDef;
404
405 /**
406 * @brief TIM Hall sensor interface configuration structure definition.
407 */
408 typedef struct
409 {
410
411 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
412 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
413
414 This feature can be modified afterwards using unitary function
415 @ref LL_TIM_IC_SetPolarity().*/
416
417 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
418 Prescaler must be set to get a maximum counter period longer than the
419 time interval between 2 consecutive changes on the Hall inputs.
420 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
421
422 This feature can be modified afterwards using unitary function
423 @ref LL_TIM_IC_SetPrescaler().*/
424
425 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
426 This parameter can be a value of
427 @ref TIM_LL_EC_IC_FILTER.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_IC_SetFilter().*/
431
432 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
433 A positive pulse (TRGO event) is generated with a programmable delay every time
434 a change occurs on the Hall inputs.
435 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
436
437 This feature can be modified afterwards using unitary function
438 @ref LL_TIM_OC_SetCompareCH2().*/
439 } LL_TIM_HALLSENSOR_InitTypeDef;
440
441 /**
442 * @brief BDTR (Break and Dead Time) structure definition
443 */
444 typedef struct
445 {
446 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
447 This parameter can be a value of @ref TIM_LL_EC_OSSR
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_SetOffStates()
451
452 @note This bit-field cannot be modified as long as LOCK level 2 has been
453 programmed. */
454
455 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
456 This parameter can be a value of @ref TIM_LL_EC_OSSI
457
458 This feature can be modified afterwards using unitary function
459 @ref LL_TIM_SetOffStates()
460
461 @note This bit-field cannot be modified as long as LOCK level 2 has been
462 programmed. */
463
464 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
465 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
466
467 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
468 register has been written, their content is frozen until the next reset.*/
469
470 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
471 switching-on of the outputs.
472 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
473
474 This feature can be modified afterwards using unitary function
475 @ref LL_TIM_OC_SetDeadTime()
476
477 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
478 programmed. */
479
480 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
482
483 This feature can be modified afterwards using unitary functions
484 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been
487 programmed. */
488
489 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
490 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
491
492 This feature can be modified afterwards using unitary function
493 @ref LL_TIM_ConfigBRK()
494
495 @note This bit-field can not be modified as long as LOCK level 1 has been
496 programmed. */
497
498 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
499 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
500
501 This feature can be modified afterwards using unitary function
502 @ref LL_TIM_ConfigBRK()
503
504 @note This bit-field can not be modified as long as LOCK level 1 has been
505 programmed. */
506
507 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
508 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
509
510 This feature can be modified afterwards using unitary functions
511 @ref LL_TIM_ConfigBRK()
512
513 @note Bidirectional break input is only supported by advanced timers instances.
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
523
524 @note This bit-field can not be modified as long as LOCK level 1 has been
525 programmed. */
526
527 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
528 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
529
530 This feature can be modified afterwards using unitary function
531 @ref LL_TIM_ConfigBRK2()
532
533 @note This bit-field can not be modified as long as LOCK level 1 has been
534 programmed. */
535
536 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
537 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
538
539 This feature can be modified afterwards using unitary function
540 @ref LL_TIM_ConfigBRK2()
541
542 @note This bit-field can not be modified as long as LOCK level 1 has been
543 programmed. */
544
545 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
546 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
547
548 This feature can be modified afterwards using unitary functions
549 @ref LL_TIM_ConfigBRK2()
550
551 @note Bidirectional break input is only supported by advanced timers instances.
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
557 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
561
562 @note This bit-field can not be modified as long as LOCK level 1 has been
563 programmed. */
564 } LL_TIM_BDTR_InitTypeDef;
565
566 /**
567 * @}
568 */
569 #endif /* USE_FULL_LL_DRIVER */
570
571 /* Exported constants --------------------------------------------------------*/
572 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
573 * @{
574 */
575
576 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
577 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
578 * @{
579 */
580 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
581 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
582 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
583 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
584 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
585 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
586 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
587 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
588 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
589 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
590 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
591 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
592 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
593 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
594 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
595 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
596 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
597 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
598 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
599 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
600 /**
601 * @}
602 */
603
604 #if defined(USE_FULL_LL_DRIVER)
605 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
606 * @{
607 */
608 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
609 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
615 * @{
616 */
617 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
618 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
624 * @{
625 */
626 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
627 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
628 /**
629 * @}
630 */
631 #endif /* USE_FULL_LL_DRIVER */
632
633 /** @defgroup TIM_LL_EC_IT IT Defines
634 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
635 * @{
636 */
637 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
638 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
639 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
640 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
641 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
642 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
643 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
644 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
645 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
646 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
647 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
648 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
654 * @{
655 */
656 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
657 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
663 * @{
664 */
665 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
666 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
672 * @{
673 */
674 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
675 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
676 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
677 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
678 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
684 * @{
685 */
686 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
687 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
688 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
694 * @{
695 */
696 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
697 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
703 * @{
704 */
705 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
706 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
712 * @{
713 */
714 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
715 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
716 /**
717 * @}
718 */
719
720 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
721 * @{
722 */
723 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
724 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
725 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
726 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_CHANNEL Channel
732 * @{
733 */
734 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
735 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
736 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
737 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
738 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
739 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
740 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
741 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
742 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
743 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
744 /**
745 * @}
746 */
747
748 #if defined(USE_FULL_LL_DRIVER)
749 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
750 * @{
751 */
752 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
753 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
754 /**
755 * @}
756 */
757 #endif /* USE_FULL_LL_DRIVER */
758
759 /** Legacy definitions for compatibility purpose
760 @cond 0
761 */
762 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
763 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
764 /**
765 @endcond
766 */
767
768 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
769 * @{
770 */
771 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
772 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
773 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
774 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
775 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
776 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
777 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
778 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
779 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
780 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
781 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
782 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
783 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
784 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
785 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
786 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
792 * @{
793 */
794 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
795 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
801 * @{
802 */
803 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
804 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
805 /**
806 * @}
807 */
808
809 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
810 * @{
811 */
812 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
813 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
814 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
815 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
821 * @{
822 */
823 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
824 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
825 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
826 /**
827 * @}
828 */
829
830 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
831 * @{
832 */
833 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
834 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
835 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
836 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
837 /**
838 * @}
839 */
840
841 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
842 * @{
843 */
844 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
845 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
846 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
847 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
848 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
849 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
850 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
851 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
852 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
853 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
854 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
855 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
856 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
857 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
858 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
859 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
860 /**
861 * @}
862 */
863
864 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
865 * @{
866 */
867 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
868 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
869 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
870 /**
871 * @}
872 */
873
874 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
875 * @{
876 */
877 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
878 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
879 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
880 /**
881 * @}
882 */
883
884 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
885 * @{
886 */
887 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
888 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
889 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
890 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
891 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
892 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
893 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
894 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
895 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
896 /**
897 * @}
898 */
899
900 /** @defgroup TIM_LL_EC_TRGO Trigger Output
901 * @{
902 */
903 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
904 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
905 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
906 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
907 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
908 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
909 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
910 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
911 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
912 /**
913 * @}
914 */
915
916 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
917 * @{
918 */
919 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
920 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
921 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
922 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
923 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
924 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
926 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
927 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
928 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
929 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
930 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
931 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
932 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
933 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
934 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
935 /**
936 * @}
937 */
938
939 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
940 * @{
941 */
942 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
943 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
944 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
945 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
946 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
947 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
948 the counter are controlled. */
949 /**
950 * @}
951 */
952
953 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
954 * @{
955 */
956 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
957 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
958 /**
959 * @}
960 */
961
962 /** @defgroup TIM_LL_EC_TS Trigger Selection
963 * @{
964 */
965 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
966 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
967 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
968 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
969 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
970 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
971 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
972 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
973 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
974 /**
975 * @}
976 */
977
978 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
979 * @{
980 */
981 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
982 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
983 /**
984 * @}
985 */
986
987 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
988 * @{
989 */
990 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
991 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
992 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
993 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
994 /**
995 * @}
996 */
997
998 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
999 * @{
1000 */
1001 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1002 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1003 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1004 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1005 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1006 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1007 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1008 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1009 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1010 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1011 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1012 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1013 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1014 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1015 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1016 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1017 /**
1018 * @}
1019 */
1020
1021 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1022 * @{
1023 */
1024 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1025 #if defined(COMP1) && defined(COMP2)
1026 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1027 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1028 #endif /* COMP1 && COMP2 */
1029 #define LL_TIM_TIM1_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1030 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1031 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1032 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1038 * @{
1039 */
1040 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1041 #if defined(COMP1) && defined(COMP2)
1042 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1043 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1044 #endif /* COMP1 && COMP2 */
1045 #define LL_TIM_TIM2_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1046 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1047 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1053 * @{
1054 */
1055 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1056 #if defined(COMP1) && defined(COMP2)
1057 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1058 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1059 #endif /* COMP1 && COMP2 */
1060 #define LL_TIM_TIM3_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1061 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1062 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
1063 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC1 analog watchdog 2 */
1064 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
1065 /**
1066 * @}
1067 */
1068
1069 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1070 * @{
1071 */
1072 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1073 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1079 * @{
1080 */
1081 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1082 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1083 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1084 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1085 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1086 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1087 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1088 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1089 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1090 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1091 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1092 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1093 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1094 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1095 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1096 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1102 * @{
1103 */
1104 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1105 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1106 /**
1107 * @}
1108 */
1109
1110 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1111 * @{
1112 */
1113 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1114 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1115 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1116 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1117 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1118 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1119 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1120 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1121 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1122 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1123 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1124 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1125 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1126 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1127 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1128 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1129 /**
1130 * @}
1131 */
1132
1133 /** @defgroup TIM_LL_EC_OSSI OSSI
1134 * @{
1135 */
1136 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1137 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1138 /**
1139 * @}
1140 */
1141
1142 /** @defgroup TIM_LL_EC_OSSR OSSR
1143 * @{
1144 */
1145 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1146 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1152 * @{
1153 */
1154 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1155 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1156 /**
1157 * @}
1158 */
1159
1160 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1161 * @{
1162 */
1163 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1164 #if defined(COMP1) && defined(COMP2)
1165 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1166 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1167 #endif /* COMP1 && COMP2 */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1173 * @{
1174 */
1175 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1176 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1182 * @{
1183 */
1184 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1185 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1191 * @{
1192 */
1193 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1194 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1195 /**
1196 * @}
1197 */
1198
1199 /** Legacy definitions for compatibility purpose
1200 @cond 0
1201 */
1202 #define LL_TIM_ReArmBRK(_PARAM_)
1203 #define LL_TIM_ReArmBRK2(_PARAM_)
1204 /**
1205 @endcond
1206 */
1207
1208 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1209 * @{
1210 */
1211 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1212 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1213 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1214 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1215 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1216 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1217 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1218 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1219 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1220 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1221 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1222 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1223 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1224 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1225 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1226 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1227 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1228 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1229 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1230 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1231 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1232 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1233 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1234 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1235 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1236 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1237 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst */
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1243 * @{
1244 */
1245 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1246 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1247 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1248 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1249 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1250 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1251 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1252 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1253 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1254 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1255 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1256 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1257 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1258 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1259 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1260 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1261 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1262 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1263 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1264 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1265 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1266 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1267 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1268 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1269 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1270 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1276 * @{
1277 */
1278 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1279 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1280 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1281 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1282 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1283 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1284 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1285 /**
1286 * @}
1287 */
1288 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1289 * @{
1290 */
1291 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL /*!< TIM1 TI1 is connected to GPIO */
1292 #if defined(COMP1) && defined(COMP2)
1293 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 TI1 is connected to COMP1 output */
1294 #define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 TI1 is connected to COMP2 output */
1295 #endif /* COMP1 && COMP2 */
1296 /**
1297 * @}
1298 */
1299
1300 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1301 * @{
1302 */
1303 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2 TI1 is connected to GPIO */
1304 #if defined(COMP1) && defined(COMP2)
1305 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 TI1 is connected to COMP1 output */
1306 #define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 TI1 is connected to COMP2 output */
1307 #endif /* COMP1 && COMP2 */
1308 /**
1309 * @}
1310 */
1311
1312 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM16 External Input Ch2 Remap
1313 * @{
1314 */
1315 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2 TI2 is connected to GPIO */
1316 #if defined(COMP1) && defined(COMP2)
1317 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 TI2 is connected to COMP1 output */
1318 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 TI2 is connected to COMP2 output */
1319 #endif /* COMP1 && COMP2 */
1320 /**
1321 * @}
1322 */
1323
1324 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1325 * @{
1326 */
1327 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2 TI4 is connected to COMP1 output */
1328 #if defined(COMP1) && defined(COMP2)
1329 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 TI4 is connected to COMP1 output */
1330 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 TI4 is connected to COMP2 output */
1331 #endif /* COMP1 && COMP2 */
1332 /**
1333 * @}
1334 */
1335
1336 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1337 * @{
1338 */
1339 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3 TI1 is connected to GPIO */
1340 #if defined(COMP1) && defined(COMP2)
1341 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 TI1 is connected to COMP1 output */
1342 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 TI1 is connected to COMP2 output */
1343 #endif /* COMP1 && COMP2 */
1344 /**
1345 * @}
1346 */
1347
1348 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
1349 * @{
1350 */
1351 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3 TI2 is connected to GPIO */
1352 #if defined(COMP1) && defined(COMP2)
1353 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 TI2 is connected to COMP1 output */
1354 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 TI2 is connected to COMP2 output */
1355 #endif /* COMP1 && COMP2 */
1356 /**
1357 * @}
1358 */
1359
1360 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1361 * @{
1362 */
1363 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16 TI1 is connected to GPIO */
1364 #define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to MCO */
1365 #define LL_TIM_TIM16_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSE DIV32 */
1366 #define LL_TIM_TIM16_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM16 TI1 is connected to RTC */
1367 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to LSE */
1368 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to LSI */
1369 #define LL_TIM_TIM16_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSI/256 */
1370 /**
1371 * @}
1372 */
1373
1374 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1375 * @{
1376 */
1377 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17 TI1 is connected to GPIO */
1378 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to MCO */
1379 #define LL_TIM_TIM17_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSE DIV32 */
1380 #define LL_TIM_TIM17_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM17 TI1 is connected to RTC */
1381 #define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to LSE */
1382 #define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to LSI */
1383 #define LL_TIM_TIM17_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSI/256 */
1384 /**
1385 * @}
1386 */
1387
1388 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1389 * @{
1390 */
1391 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
1392 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1393 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1394 /**
1395 * @}
1396 */
1397
1398 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1399 * @{
1400 */
1401 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1402 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1403 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1404 /**
1405 * @}
1406 */
1407
1408 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1409 * @{
1410 */
1411 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1412 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1413 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1414 /**
1415 * @}
1416 */
1417
1418 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1419 * @{
1420 */
1421 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1422 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1423 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1424 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1425 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1426 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1427 /**
1428 * @}
1429 */
1430
1431 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1432 * @{
1433 */
1434 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1435 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1436 /**
1437 * @}
1438 */
1439 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1440 * @{
1441 */
1442 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1443 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1444 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1445 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1446 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1447 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1448 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1449 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1450 /**
1451 * @}
1452 */
1453
1454 /** Legacy definitions for compatibility purpose
1455 @cond 0
1456 */
1457 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1458 /**
1459 @endcond
1460 */
1461
1462 /**
1463 * @}
1464 */
1465
1466 /* Exported macro ------------------------------------------------------------*/
1467 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1468 * @{
1469 */
1470
1471 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1472 * @{
1473 */
1474 /**
1475 * @brief Write a value in TIM register.
1476 * @param __INSTANCE__ TIM Instance
1477 * @param __REG__ Register to be written
1478 * @param __VALUE__ Value to be written in the register
1479 * @retval None
1480 */
1481 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1482
1483 /**
1484 * @brief Read a value in TIM register.
1485 * @param __INSTANCE__ TIM Instance
1486 * @param __REG__ Register to be read
1487 * @retval Register value
1488 */
1489 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1490 /**
1491 * @}
1492 */
1493
1494 /**
1495 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1496 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1497 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1498 * to TIMx_CNT register bit 31)
1499 * @param __CNT__ Counter value
1500 * @retval UIF status bit
1501 */
1502 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1503 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1504
1505 /**
1506 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1507 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1508 * @param __TIMCLK__ timer input clock frequency (in Hz)
1509 * @param __CKD__ This parameter can be one of the following values:
1510 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1511 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1512 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1513 * @param __DT__ deadtime duration (in ns)
1514 * @retval DTG[0:7]
1515 */
1516 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1517 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1518 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1519 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1520 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1521 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1522 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1523 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1524 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1525 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1526 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1527 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1528 0U)
1529
1530 /**
1531 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1532 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1533 * @param __TIMCLK__ timer input clock frequency (in Hz)
1534 * @param __CNTCLK__ counter clock frequency (in Hz)
1535 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1536 */
1537 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1538 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1539
1540 /**
1541 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1542 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1543 * @param __TIMCLK__ timer input clock frequency (in Hz)
1544 * @param __PSC__ prescaler
1545 * @param __FREQ__ output signal frequency (in Hz)
1546 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1547 */
1548 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1549 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1550
1551 /**
1552 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1553 * output signal frequency.
1554 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1555 * @param __TIMCLK__ timer input clock frequency (in Hz)
1556 * @param __PSC__ prescaler
1557 * @param __FREQ__ output signal frequency (in Hz)
1558 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1559 */
1560 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1561 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1562 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1563
1564 /**
1565 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1566 * active/inactive delay.
1567 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1568 * @param __TIMCLK__ timer input clock frequency (in Hz)
1569 * @param __PSC__ prescaler
1570 * @param __DELAY__ timer output compare active/inactive delay (in us)
1571 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1572 */
1573 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1574 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1575 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1576
1577 /**
1578 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1579 * output compare active/inactive delay.
1580 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1581 * @param __TIMCLK__ timer input clock frequency (in Hz)
1582 * @param __PSC__ prescaler
1583 * @param __DELAY__ timer output compare active/inactive delay (in us)
1584 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1585 */
1586 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1587 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1588 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1589
1590 /**
1591 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1592 * (when the timer operates in one pulse mode).
1593 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1594 * @param __TIMCLK__ timer input clock frequency (in Hz)
1595 * @param __PSC__ prescaler
1596 * @param __DELAY__ timer output compare active/inactive delay (in us)
1597 * @param __PULSE__ pulse duration (in us)
1598 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1599 */
1600 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1601 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1602 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1603
1604 /**
1605 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1606 * pulse duration (when the timer operates in one pulse mode).
1607 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1608 * @param __TIMCLK__ timer input clock frequency (in Hz)
1609 * @param __PSC__ prescaler
1610 * @param __DELAY__ timer output compare active/inactive delay (in us)
1611 * @param __PULSE__ pulse duration (in us)
1612 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1613 */
1614 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1615 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1616 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1617
1618 /**
1619 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1620 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1621 * @param __ICPSC__ This parameter can be one of the following values:
1622 * @arg @ref LL_TIM_ICPSC_DIV1
1623 * @arg @ref LL_TIM_ICPSC_DIV2
1624 * @arg @ref LL_TIM_ICPSC_DIV4
1625 * @arg @ref LL_TIM_ICPSC_DIV8
1626 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1627 */
1628 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1629 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1630
1631
1632 /**
1633 * @}
1634 */
1635
1636 /* Exported functions --------------------------------------------------------*/
1637 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1638 * @{
1639 */
1640
1641 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1642 * @{
1643 */
1644 /**
1645 * @brief Enable timer counter.
1646 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1647 * @param TIMx Timer instance
1648 * @retval None
1649 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1650 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1651 {
1652 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1653 }
1654
1655 /**
1656 * @brief Disable timer counter.
1657 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1658 * @param TIMx Timer instance
1659 * @retval None
1660 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1661 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1662 {
1663 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1664 }
1665
1666 /**
1667 * @brief Indicates whether the timer counter is enabled.
1668 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1669 * @param TIMx Timer instance
1670 * @retval State of bit (1 or 0).
1671 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1672 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1673 {
1674 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1675 }
1676
1677 /**
1678 * @brief Enable update event generation.
1679 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1680 * @param TIMx Timer instance
1681 * @retval None
1682 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1683 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1684 {
1685 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1686 }
1687
1688 /**
1689 * @brief Disable update event generation.
1690 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1691 * @param TIMx Timer instance
1692 * @retval None
1693 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1694 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1695 {
1696 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1697 }
1698
1699 /**
1700 * @brief Indicates whether update event generation is enabled.
1701 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1702 * @param TIMx Timer instance
1703 * @retval Inverted state of bit (0 or 1).
1704 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1705 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1706 {
1707 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1708 }
1709
1710 /**
1711 * @brief Set update event source
1712 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1713 * generate an update interrupt or DMA request if enabled:
1714 * - Counter overflow/underflow
1715 * - Setting the UG bit
1716 * - Update generation through the slave mode controller
1717 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1718 * overflow/underflow generates an update interrupt or DMA request if enabled.
1719 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1720 * @param TIMx Timer instance
1721 * @param UpdateSource This parameter can be one of the following values:
1722 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1723 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1724 * @retval None
1725 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1726 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1727 {
1728 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1729 }
1730
1731 /**
1732 * @brief Get actual event update source
1733 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1734 * @param TIMx Timer instance
1735 * @retval Returned value can be one of the following values:
1736 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1737 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1738 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1739 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1740 {
1741 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1742 }
1743
1744 /**
1745 * @brief Set one pulse mode (one shot v.s. repetitive).
1746 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1747 * @param TIMx Timer instance
1748 * @param OnePulseMode This parameter can be one of the following values:
1749 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1750 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1751 * @retval None
1752 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1753 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1754 {
1755 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1756 }
1757
1758 /**
1759 * @brief Get actual one pulse mode.
1760 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1761 * @param TIMx Timer instance
1762 * @retval Returned value can be one of the following values:
1763 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1764 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1765 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1766 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1767 {
1768 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1769 }
1770
1771 /**
1772 * @brief Set the timer counter counting mode.
1773 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1774 * check whether or not the counter mode selection feature is supported
1775 * by a timer instance.
1776 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1777 * requires a timer reset to avoid unexpected direction
1778 * due to DIR bit readonly in center aligned mode.
1779 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1780 * CR1 CMS LL_TIM_SetCounterMode
1781 * @param TIMx Timer instance
1782 * @param CounterMode This parameter can be one of the following values:
1783 * @arg @ref LL_TIM_COUNTERMODE_UP
1784 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1785 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1786 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1787 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1788 * @retval None
1789 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1790 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1791 {
1792 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1793 }
1794
1795 /**
1796 * @brief Get actual counter mode.
1797 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1798 * check whether or not the counter mode selection feature is supported
1799 * by a timer instance.
1800 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1801 * CR1 CMS LL_TIM_GetCounterMode
1802 * @param TIMx Timer instance
1803 * @retval Returned value can be one of the following values:
1804 * @arg @ref LL_TIM_COUNTERMODE_UP
1805 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1806 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1807 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1808 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1809 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1810 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1811 {
1812 uint32_t counter_mode;
1813
1814 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1815
1816 if (counter_mode == 0U)
1817 {
1818 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1819 }
1820
1821 return counter_mode;
1822 }
1823
1824 /**
1825 * @brief Enable auto-reload (ARR) preload.
1826 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1827 * @param TIMx Timer instance
1828 * @retval None
1829 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1830 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1831 {
1832 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1833 }
1834
1835 /**
1836 * @brief Disable auto-reload (ARR) preload.
1837 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1838 * @param TIMx Timer instance
1839 * @retval None
1840 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1841 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1842 {
1843 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1844 }
1845
1846 /**
1847 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1848 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1849 * @param TIMx Timer instance
1850 * @retval State of bit (1 or 0).
1851 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1852 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1853 {
1854 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1855 }
1856
1857 /**
1858 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1859 * (when supported) and the digital filters.
1860 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1861 * whether or not the clock division feature is supported by the timer
1862 * instance.
1863 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1864 * @param TIMx Timer instance
1865 * @param ClockDivision This parameter can be one of the following values:
1866 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1867 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1868 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1869 * @retval None
1870 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1871 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1872 {
1873 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1874 }
1875
1876 /**
1877 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1878 * generators (when supported) and the digital filters.
1879 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1880 * whether or not the clock division feature is supported by the timer
1881 * instance.
1882 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1883 * @param TIMx Timer instance
1884 * @retval Returned value can be one of the following values:
1885 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1886 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1887 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1888 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1889 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1890 {
1891 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1892 }
1893
1894 /**
1895 * @brief Set the counter value.
1896 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1897 * whether or not a timer instance supports a 32 bits counter.
1898 * @note If dithering is activated, pay attention to the Counter value interpretation
1899 * @rmtoll CNT CNT LL_TIM_SetCounter
1900 * @param TIMx Timer instance
1901 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1902 * @retval None
1903 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1904 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1905 {
1906 WRITE_REG(TIMx->CNT, Counter);
1907 }
1908
1909 /**
1910 * @brief Get the counter value.
1911 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1912 * whether or not a timer instance supports a 32 bits counter.
1913 * @note If dithering is activated, pay attention to the Counter value interpretation
1914 * @rmtoll CNT CNT LL_TIM_GetCounter
1915 * @param TIMx Timer instance
1916 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1917 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1918 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1919 {
1920 return (uint32_t)(READ_REG(TIMx->CNT));
1921 }
1922
1923 /**
1924 * @brief Get the current direction of the counter
1925 * @rmtoll CR1 DIR LL_TIM_GetDirection
1926 * @param TIMx Timer instance
1927 * @retval Returned value can be one of the following values:
1928 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1929 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1930 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1931 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1932 {
1933 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1934 }
1935
1936 /**
1937 * @brief Set the prescaler value.
1938 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1939 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1940 * prescaler ratio is taken into account at the next update event.
1941 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1942 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1943 * @param TIMx Timer instance
1944 * @param Prescaler between Min_Data=0 and Max_Data=65535
1945 * @retval None
1946 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1947 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1948 {
1949 WRITE_REG(TIMx->PSC, Prescaler);
1950 }
1951
1952 /**
1953 * @brief Get the prescaler value.
1954 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1955 * @param TIMx Timer instance
1956 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1957 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1958 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1959 {
1960 return (uint32_t)(READ_REG(TIMx->PSC));
1961 }
1962
1963 /**
1964 * @brief Set the auto-reload value.
1965 * @note The counter is blocked while the auto-reload value is null.
1966 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1967 * whether or not a timer instance supports a 32 bits counter.
1968 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1969 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
1970 * parameter.
1971 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1972 * @param TIMx Timer instance
1973 * @param AutoReload between Min_Data=0 and Max_Data=65535
1974 * @retval None
1975 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1976 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1977 {
1978 WRITE_REG(TIMx->ARR, AutoReload);
1979 }
1980
1981 /**
1982 * @brief Get the auto-reload value.
1983 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1984 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1985 * whether or not a timer instance supports a 32 bits counter.
1986 * @note If dithering is activated, pay attention to the returned value interpretation
1987 * @param TIMx Timer instance
1988 * @retval Auto-reload value
1989 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1990 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1991 {
1992 return (uint32_t)(READ_REG(TIMx->ARR));
1993 }
1994
1995 /**
1996 * @brief Set the repetition counter value.
1997 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1998 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1999 * whether or not a timer instance supports a repetition counter.
2000 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2001 * @param TIMx Timer instance
2002 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2003 * @retval None
2004 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2005 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2006 {
2007 WRITE_REG(TIMx->RCR, RepetitionCounter);
2008 }
2009
2010 /**
2011 * @brief Get the repetition counter value.
2012 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2013 * whether or not a timer instance supports a repetition counter.
2014 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2015 * @param TIMx Timer instance
2016 * @retval Repetition counter value
2017 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2018 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2019 {
2020 return (uint32_t)(READ_REG(TIMx->RCR));
2021 }
2022
2023 /**
2024 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2025 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2026 * in an atomic way.
2027 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2028 * @param TIMx Timer instance
2029 * @retval None
2030 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2031 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2032 {
2033 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2034 }
2035
2036 /**
2037 * @brief Disable update interrupt flag (UIF) remapping.
2038 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2039 * @param TIMx Timer instance
2040 * @retval None
2041 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2042 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2043 {
2044 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2045 }
2046
2047 /**
2048 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2049 * @param Counter Counter value
2050 * @retval State of bit (1 or 0).
2051 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2052 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2053 {
2054 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2055 }
2056
2057 /**
2058 * @brief Enable dithering.
2059 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2060 * a timer instance provides dithering.
2061 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2062 * @param TIMx Timer instance
2063 * @retval None
2064 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2065 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2066 {
2067 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2068 }
2069
2070 /**
2071 * @brief Disable dithering.
2072 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2073 * a timer instance provides dithering.
2074 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2075 * @param TIMx Timer instance
2076 * @retval None
2077 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2078 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2079 {
2080 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2081 }
2082
2083 /**
2084 * @brief Indicates whether dithering is activated.
2085 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2086 * a timer instance provides dithering.
2087 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2088 * @param TIMx Timer instance
2089 * @retval State of bit (1 or 0).
2090 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2091 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2092 {
2093 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2094 }
2095
2096 /**
2097 * @}
2098 */
2099
2100 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2101 * @{
2102 */
2103 /**
2104 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2105 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2106 * they are updated only when a commutation event (COM) occurs.
2107 * @note Only on channels that have a complementary output.
2108 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2109 * whether or not a timer instance is able to generate a commutation event.
2110 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2111 * @param TIMx Timer instance
2112 * @retval None
2113 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2114 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2115 {
2116 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2117 }
2118
2119 /**
2120 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2121 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2122 * whether or not a timer instance is able to generate a commutation event.
2123 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2124 * @param TIMx Timer instance
2125 * @retval None
2126 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2127 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2128 {
2129 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2130 }
2131
2132 /**
2133 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2134 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2135 * @param TIMx Timer instance
2136 * @retval State of bit (1 or 0).
2137 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2138 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2139 {
2140 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2141 }
2142
2143 /**
2144 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2145 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2146 * whether or not a timer instance is able to generate a commutation event.
2147 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2148 * @param TIMx Timer instance
2149 * @param CCUpdateSource This parameter can be one of the following values:
2150 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2151 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2152 * @retval None
2153 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2154 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2155 {
2156 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2157 }
2158
2159 /**
2160 * @brief Set the trigger of the capture/compare DMA request.
2161 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2162 * @param TIMx Timer instance
2163 * @param DMAReqTrigger This parameter can be one of the following values:
2164 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2165 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2166 * @retval None
2167 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2168 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2169 {
2170 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2171 }
2172
2173 /**
2174 * @brief Get actual trigger of the capture/compare DMA request.
2175 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2176 * @param TIMx Timer instance
2177 * @retval Returned value can be one of the following values:
2178 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2179 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2180 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2181 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2182 {
2183 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2184 }
2185
2186 /**
2187 * @brief Set the lock level to freeze the
2188 * configuration of several capture/compare parameters.
2189 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2190 * the lock mechanism is supported by a timer instance.
2191 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2192 * @param TIMx Timer instance
2193 * @param LockLevel This parameter can be one of the following values:
2194 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2195 * @arg @ref LL_TIM_LOCKLEVEL_1
2196 * @arg @ref LL_TIM_LOCKLEVEL_2
2197 * @arg @ref LL_TIM_LOCKLEVEL_3
2198 * @retval None
2199 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2200 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2201 {
2202 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2203 }
2204
2205 /**
2206 * @brief Enable capture/compare channels.
2207 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2208 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2209 * CCER CC2E LL_TIM_CC_EnableChannel\n
2210 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2211 * CCER CC3E LL_TIM_CC_EnableChannel\n
2212 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2213 * CCER CC4E LL_TIM_CC_EnableChannel\n
2214 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2215 * CCER CC5E LL_TIM_CC_EnableChannel\n
2216 * CCER CC6E LL_TIM_CC_EnableChannel
2217 * @param TIMx Timer instance
2218 * @param Channels This parameter can be a combination of the following values:
2219 * @arg @ref LL_TIM_CHANNEL_CH1
2220 * @arg @ref LL_TIM_CHANNEL_CH1N
2221 * @arg @ref LL_TIM_CHANNEL_CH2
2222 * @arg @ref LL_TIM_CHANNEL_CH2N
2223 * @arg @ref LL_TIM_CHANNEL_CH3
2224 * @arg @ref LL_TIM_CHANNEL_CH3N
2225 * @arg @ref LL_TIM_CHANNEL_CH4
2226 * @arg @ref LL_TIM_CHANNEL_CH4N
2227 * @arg @ref LL_TIM_CHANNEL_CH5
2228 * @arg @ref LL_TIM_CHANNEL_CH6
2229 * @retval None
2230 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2231 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2232 {
2233 SET_BIT(TIMx->CCER, Channels);
2234 }
2235
2236 /**
2237 * @brief Disable capture/compare channels.
2238 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2239 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2240 * CCER CC2E LL_TIM_CC_DisableChannel\n
2241 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2242 * CCER CC3E LL_TIM_CC_DisableChannel\n
2243 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2244 * CCER CC4E LL_TIM_CC_DisableChannel\n
2245 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2246 * CCER CC5E LL_TIM_CC_DisableChannel\n
2247 * CCER CC6E LL_TIM_CC_DisableChannel
2248 * @param TIMx Timer instance
2249 * @param Channels This parameter can be a combination of the following values:
2250 * @arg @ref LL_TIM_CHANNEL_CH1
2251 * @arg @ref LL_TIM_CHANNEL_CH1N
2252 * @arg @ref LL_TIM_CHANNEL_CH2
2253 * @arg @ref LL_TIM_CHANNEL_CH2N
2254 * @arg @ref LL_TIM_CHANNEL_CH3
2255 * @arg @ref LL_TIM_CHANNEL_CH3N
2256 * @arg @ref LL_TIM_CHANNEL_CH4
2257 * @arg @ref LL_TIM_CHANNEL_CH4N
2258 * @arg @ref LL_TIM_CHANNEL_CH5
2259 * @arg @ref LL_TIM_CHANNEL_CH6
2260 * @retval None
2261 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2262 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2263 {
2264 CLEAR_BIT(TIMx->CCER, Channels);
2265 }
2266
2267 /**
2268 * @brief Indicate whether channel(s) is(are) enabled.
2269 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2270 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2271 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2272 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2273 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2274 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2275 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2276 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2277 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2278 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2279 * @param TIMx Timer instance
2280 * @param Channels This parameter can be a combination of the following values:
2281 * @arg @ref LL_TIM_CHANNEL_CH1
2282 * @arg @ref LL_TIM_CHANNEL_CH1N
2283 * @arg @ref LL_TIM_CHANNEL_CH2
2284 * @arg @ref LL_TIM_CHANNEL_CH2N
2285 * @arg @ref LL_TIM_CHANNEL_CH3
2286 * @arg @ref LL_TIM_CHANNEL_CH3N
2287 * @arg @ref LL_TIM_CHANNEL_CH4
2288 * @arg @ref LL_TIM_CHANNEL_CH4N
2289 * @arg @ref LL_TIM_CHANNEL_CH5
2290 * @arg @ref LL_TIM_CHANNEL_CH6
2291 * @retval State of bit (1 or 0).
2292 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2293 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2294 {
2295 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2296 }
2297
2298 /**
2299 * @}
2300 */
2301
2302 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2303 * @{
2304 */
2305 /**
2306 * @brief Configure an output channel.
2307 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2308 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2309 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2310 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2311 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2312 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2313 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2314 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2315 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2316 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2317 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2318 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2319 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2320 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2321 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2322 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2323 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2324 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2325 * @param TIMx Timer instance
2326 * @param Channel This parameter can be one of the following values:
2327 * @arg @ref LL_TIM_CHANNEL_CH1
2328 * @arg @ref LL_TIM_CHANNEL_CH2
2329 * @arg @ref LL_TIM_CHANNEL_CH3
2330 * @arg @ref LL_TIM_CHANNEL_CH4
2331 * @arg @ref LL_TIM_CHANNEL_CH5
2332 * @arg @ref LL_TIM_CHANNEL_CH6
2333 * @param Configuration This parameter must be a combination of all the following values:
2334 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2335 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2336 * @retval None
2337 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2338 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2339 {
2340 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2341 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2342 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2343 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2344 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2345 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2346 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2347 }
2348
2349 /**
2350 * @brief Define the behavior of the output reference signal OCxREF from which
2351 * OCx and OCxN (when relevant) are derived.
2352 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2353 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2354 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2355 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2356 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2357 * CCMR3 OC6M LL_TIM_OC_SetMode
2358 * @param TIMx Timer instance
2359 * @param Channel This parameter can be one of the following values:
2360 * @arg @ref LL_TIM_CHANNEL_CH1
2361 * @arg @ref LL_TIM_CHANNEL_CH2
2362 * @arg @ref LL_TIM_CHANNEL_CH3
2363 * @arg @ref LL_TIM_CHANNEL_CH4
2364 * @arg @ref LL_TIM_CHANNEL_CH5
2365 * @arg @ref LL_TIM_CHANNEL_CH6
2366 * @param Mode This parameter can be one of the following values:
2367 * @arg @ref LL_TIM_OCMODE_FROZEN
2368 * @arg @ref LL_TIM_OCMODE_ACTIVE
2369 * @arg @ref LL_TIM_OCMODE_INACTIVE
2370 * @arg @ref LL_TIM_OCMODE_TOGGLE
2371 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2372 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2373 * @arg @ref LL_TIM_OCMODE_PWM1
2374 * @arg @ref LL_TIM_OCMODE_PWM2
2375 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2376 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2377 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2378 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2379 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2380 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2381 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2382 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2383 * @retval None
2384 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2385 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2386 {
2387 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2388 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2389 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2390 }
2391
2392 /**
2393 * @brief Get the output compare mode of an output channel.
2394 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2395 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2396 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2397 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2398 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2399 * CCMR3 OC6M LL_TIM_OC_GetMode
2400 * @param TIMx Timer instance
2401 * @param Channel This parameter can be one of the following values:
2402 * @arg @ref LL_TIM_CHANNEL_CH1
2403 * @arg @ref LL_TIM_CHANNEL_CH2
2404 * @arg @ref LL_TIM_CHANNEL_CH3
2405 * @arg @ref LL_TIM_CHANNEL_CH4
2406 * @arg @ref LL_TIM_CHANNEL_CH5
2407 * @arg @ref LL_TIM_CHANNEL_CH6
2408 * @retval Returned value can be one of the following values:
2409 * @arg @ref LL_TIM_OCMODE_FROZEN
2410 * @arg @ref LL_TIM_OCMODE_ACTIVE
2411 * @arg @ref LL_TIM_OCMODE_INACTIVE
2412 * @arg @ref LL_TIM_OCMODE_TOGGLE
2413 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2414 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2415 * @arg @ref LL_TIM_OCMODE_PWM1
2416 * @arg @ref LL_TIM_OCMODE_PWM2
2417 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2418 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2419 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2420 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2421 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2422 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2423 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2424 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2425 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2426 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2427 {
2428 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2429 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2430 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2431 }
2432
2433 /**
2434 * @brief Set the polarity of an output channel.
2435 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2436 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2437 * CCER CC2P LL_TIM_OC_SetPolarity\n
2438 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2439 * CCER CC3P LL_TIM_OC_SetPolarity\n
2440 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2441 * CCER CC4P LL_TIM_OC_SetPolarity\n
2442 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2443 * CCER CC5P LL_TIM_OC_SetPolarity\n
2444 * CCER CC6P LL_TIM_OC_SetPolarity
2445 * @param TIMx Timer instance
2446 * @param Channel This parameter can be one of the following values:
2447 * @arg @ref LL_TIM_CHANNEL_CH1
2448 * @arg @ref LL_TIM_CHANNEL_CH1N
2449 * @arg @ref LL_TIM_CHANNEL_CH2
2450 * @arg @ref LL_TIM_CHANNEL_CH2N
2451 * @arg @ref LL_TIM_CHANNEL_CH3
2452 * @arg @ref LL_TIM_CHANNEL_CH3N
2453 * @arg @ref LL_TIM_CHANNEL_CH4
2454 * @arg @ref LL_TIM_CHANNEL_CH4N
2455 * @arg @ref LL_TIM_CHANNEL_CH5
2456 * @arg @ref LL_TIM_CHANNEL_CH6
2457 * @param Polarity This parameter can be one of the following values:
2458 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2459 * @arg @ref LL_TIM_OCPOLARITY_LOW
2460 * @retval None
2461 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2462 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2463 {
2464 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2465 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2466 }
2467
2468 /**
2469 * @brief Get the polarity of an output channel.
2470 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2471 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2472 * CCER CC2P LL_TIM_OC_GetPolarity\n
2473 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2474 * CCER CC3P LL_TIM_OC_GetPolarity\n
2475 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2476 * CCER CC4P LL_TIM_OC_GetPolarity\n
2477 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2478 * CCER CC5P LL_TIM_OC_GetPolarity\n
2479 * CCER CC6P LL_TIM_OC_GetPolarity
2480 * @param TIMx Timer instance
2481 * @param Channel This parameter can be one of the following values:
2482 * @arg @ref LL_TIM_CHANNEL_CH1
2483 * @arg @ref LL_TIM_CHANNEL_CH1N
2484 * @arg @ref LL_TIM_CHANNEL_CH2
2485 * @arg @ref LL_TIM_CHANNEL_CH2N
2486 * @arg @ref LL_TIM_CHANNEL_CH3
2487 * @arg @ref LL_TIM_CHANNEL_CH3N
2488 * @arg @ref LL_TIM_CHANNEL_CH4
2489 * @arg @ref LL_TIM_CHANNEL_CH4N
2490 * @arg @ref LL_TIM_CHANNEL_CH5
2491 * @arg @ref LL_TIM_CHANNEL_CH6
2492 * @retval Returned value can be one of the following values:
2493 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2494 * @arg @ref LL_TIM_OCPOLARITY_LOW
2495 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2496 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2497 {
2498 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2499 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2500 }
2501
2502 /**
2503 * @brief Set the IDLE state of an output channel
2504 * @note This function is significant only for the timer instances
2505 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2506 * can be used to check whether or not a timer instance provides
2507 * a break input.
2508 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2509 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2510 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2511 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2512 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2513 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2514 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2515 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2516 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2517 * CR2 OIS6 LL_TIM_OC_SetIdleState
2518 * @param TIMx Timer instance
2519 * @param Channel This parameter can be one of the following values:
2520 * @arg @ref LL_TIM_CHANNEL_CH1
2521 * @arg @ref LL_TIM_CHANNEL_CH1N
2522 * @arg @ref LL_TIM_CHANNEL_CH2
2523 * @arg @ref LL_TIM_CHANNEL_CH2N
2524 * @arg @ref LL_TIM_CHANNEL_CH3
2525 * @arg @ref LL_TIM_CHANNEL_CH3N
2526 * @arg @ref LL_TIM_CHANNEL_CH4
2527 * @arg @ref LL_TIM_CHANNEL_CH4N
2528 * @arg @ref LL_TIM_CHANNEL_CH5
2529 * @arg @ref LL_TIM_CHANNEL_CH6
2530 * @param IdleState This parameter can be one of the following values:
2531 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2532 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2533 * @retval None
2534 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2535 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2536 {
2537 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2538 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2539 }
2540
2541 /**
2542 * @brief Get the IDLE state of an output channel
2543 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2544 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2545 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2546 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2547 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2548 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2549 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2550 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2551 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2552 * CR2 OIS6 LL_TIM_OC_GetIdleState
2553 * @param TIMx Timer instance
2554 * @param Channel This parameter can be one of the following values:
2555 * @arg @ref LL_TIM_CHANNEL_CH1
2556 * @arg @ref LL_TIM_CHANNEL_CH1N
2557 * @arg @ref LL_TIM_CHANNEL_CH2
2558 * @arg @ref LL_TIM_CHANNEL_CH2N
2559 * @arg @ref LL_TIM_CHANNEL_CH3
2560 * @arg @ref LL_TIM_CHANNEL_CH3N
2561 * @arg @ref LL_TIM_CHANNEL_CH4
2562 * @arg @ref LL_TIM_CHANNEL_CH4N
2563 * @arg @ref LL_TIM_CHANNEL_CH5
2564 * @arg @ref LL_TIM_CHANNEL_CH6
2565 * @retval Returned value can be one of the following values:
2566 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2567 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2568 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2569 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2570 {
2571 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2572 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2573 }
2574
2575 /**
2576 * @brief Enable fast mode for the output channel.
2577 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2578 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2579 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2580 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2581 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2582 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2583 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2584 * @param TIMx Timer instance
2585 * @param Channel This parameter can be one of the following values:
2586 * @arg @ref LL_TIM_CHANNEL_CH1
2587 * @arg @ref LL_TIM_CHANNEL_CH2
2588 * @arg @ref LL_TIM_CHANNEL_CH3
2589 * @arg @ref LL_TIM_CHANNEL_CH4
2590 * @arg @ref LL_TIM_CHANNEL_CH5
2591 * @arg @ref LL_TIM_CHANNEL_CH6
2592 * @retval None
2593 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2594 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2595 {
2596 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2597 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2598 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2599
2600 }
2601
2602 /**
2603 * @brief Disable fast mode for the output channel.
2604 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2605 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2606 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2607 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2608 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2609 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2610 * @param TIMx Timer instance
2611 * @param Channel This parameter can be one of the following values:
2612 * @arg @ref LL_TIM_CHANNEL_CH1
2613 * @arg @ref LL_TIM_CHANNEL_CH2
2614 * @arg @ref LL_TIM_CHANNEL_CH3
2615 * @arg @ref LL_TIM_CHANNEL_CH4
2616 * @arg @ref LL_TIM_CHANNEL_CH5
2617 * @arg @ref LL_TIM_CHANNEL_CH6
2618 * @retval None
2619 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2620 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2621 {
2622 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2623 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2624 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2625
2626 }
2627
2628 /**
2629 * @brief Indicates whether fast mode is enabled for the output channel.
2630 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2631 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2632 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2633 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2634 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2635 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2636 * @param TIMx Timer instance
2637 * @param Channel This parameter can be one of the following values:
2638 * @arg @ref LL_TIM_CHANNEL_CH1
2639 * @arg @ref LL_TIM_CHANNEL_CH2
2640 * @arg @ref LL_TIM_CHANNEL_CH3
2641 * @arg @ref LL_TIM_CHANNEL_CH4
2642 * @arg @ref LL_TIM_CHANNEL_CH5
2643 * @arg @ref LL_TIM_CHANNEL_CH6
2644 * @retval State of bit (1 or 0).
2645 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2646 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2647 {
2648 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2649 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2650 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2651 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2652 }
2653
2654 /**
2655 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2656 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2657 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2658 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2659 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2660 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2661 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2662 * @param TIMx Timer instance
2663 * @param Channel This parameter can be one of the following values:
2664 * @arg @ref LL_TIM_CHANNEL_CH1
2665 * @arg @ref LL_TIM_CHANNEL_CH2
2666 * @arg @ref LL_TIM_CHANNEL_CH3
2667 * @arg @ref LL_TIM_CHANNEL_CH4
2668 * @arg @ref LL_TIM_CHANNEL_CH5
2669 * @arg @ref LL_TIM_CHANNEL_CH6
2670 * @retval None
2671 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2672 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2673 {
2674 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2675 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2676 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2677 }
2678
2679 /**
2680 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2681 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2682 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2683 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2684 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2685 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2686 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2687 * @param TIMx Timer instance
2688 * @param Channel This parameter can be one of the following values:
2689 * @arg @ref LL_TIM_CHANNEL_CH1
2690 * @arg @ref LL_TIM_CHANNEL_CH2
2691 * @arg @ref LL_TIM_CHANNEL_CH3
2692 * @arg @ref LL_TIM_CHANNEL_CH4
2693 * @arg @ref LL_TIM_CHANNEL_CH5
2694 * @arg @ref LL_TIM_CHANNEL_CH6
2695 * @retval None
2696 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2697 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2698 {
2699 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2700 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2701 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2702 }
2703
2704 /**
2705 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2706 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2707 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2708 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2709 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2710 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2711 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2712 * @param TIMx Timer instance
2713 * @param Channel This parameter can be one of the following values:
2714 * @arg @ref LL_TIM_CHANNEL_CH1
2715 * @arg @ref LL_TIM_CHANNEL_CH2
2716 * @arg @ref LL_TIM_CHANNEL_CH3
2717 * @arg @ref LL_TIM_CHANNEL_CH4
2718 * @arg @ref LL_TIM_CHANNEL_CH5
2719 * @arg @ref LL_TIM_CHANNEL_CH6
2720 * @retval State of bit (1 or 0).
2721 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2722 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2723 {
2724 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2725 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2726 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2727 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2728 }
2729
2730 /**
2731 * @brief Enable clearing the output channel on an external event.
2732 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2733 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2734 * or not a timer instance can clear the OCxREF signal on an external event.
2735 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2736 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2737 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2738 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2739 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2740 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2741 * @param TIMx Timer instance
2742 * @param Channel This parameter can be one of the following values:
2743 * @arg @ref LL_TIM_CHANNEL_CH1
2744 * @arg @ref LL_TIM_CHANNEL_CH2
2745 * @arg @ref LL_TIM_CHANNEL_CH3
2746 * @arg @ref LL_TIM_CHANNEL_CH4
2747 * @arg @ref LL_TIM_CHANNEL_CH5
2748 * @arg @ref LL_TIM_CHANNEL_CH6
2749 * @retval None
2750 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2751 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2752 {
2753 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2754 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2755 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2756 }
2757
2758 /**
2759 * @brief Disable clearing the output channel on an external event.
2760 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2761 * or not a timer instance can clear the OCxREF signal on an external event.
2762 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2763 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2764 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2765 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2766 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2767 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2768 * @param TIMx Timer instance
2769 * @param Channel This parameter can be one of the following values:
2770 * @arg @ref LL_TIM_CHANNEL_CH1
2771 * @arg @ref LL_TIM_CHANNEL_CH2
2772 * @arg @ref LL_TIM_CHANNEL_CH3
2773 * @arg @ref LL_TIM_CHANNEL_CH4
2774 * @arg @ref LL_TIM_CHANNEL_CH5
2775 * @arg @ref LL_TIM_CHANNEL_CH6
2776 * @retval None
2777 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2778 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2779 {
2780 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2781 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2782 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2783 }
2784
2785 /**
2786 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2787 * @note This function enables clearing the output channel on an external event.
2788 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2789 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2790 * or not a timer instance can clear the OCxREF signal on an external event.
2791 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2792 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2793 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2794 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2795 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2796 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2797 * @param TIMx Timer instance
2798 * @param Channel This parameter can be one of the following values:
2799 * @arg @ref LL_TIM_CHANNEL_CH1
2800 * @arg @ref LL_TIM_CHANNEL_CH2
2801 * @arg @ref LL_TIM_CHANNEL_CH3
2802 * @arg @ref LL_TIM_CHANNEL_CH4
2803 * @arg @ref LL_TIM_CHANNEL_CH5
2804 * @arg @ref LL_TIM_CHANNEL_CH6
2805 * @retval State of bit (1 or 0).
2806 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2807 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2808 {
2809 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2810 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2811 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2812 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2813 }
2814
2815 /**
2816 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2817 * the Ocx and OCxN signals).
2818 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2819 * dead-time insertion feature is supported by a timer instance.
2820 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2821 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2822 * @param TIMx Timer instance
2823 * @param DeadTime between Min_Data=0 and Max_Data=255
2824 * @retval None
2825 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2826 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2827 {
2828 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2829 }
2830
2831 /**
2832 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2833 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2834 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2835 * whether or not a timer instance supports a 32 bits counter.
2836 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2837 * output channel 1 is supported by a timer instance.
2838 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2839 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2840 * @param TIMx Timer instance
2841 * @param CompareValue between Min_Data=0 and Max_Data=65535
2842 * @retval None
2843 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2844 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2845 {
2846 WRITE_REG(TIMx->CCR1, CompareValue);
2847 }
2848
2849 /**
2850 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2851 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2852 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2853 * whether or not a timer instance supports a 32 bits counter.
2854 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2855 * output channel 2 is supported by a timer instance.
2856 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2857 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2858 * @param TIMx Timer instance
2859 * @param CompareValue between Min_Data=0 and Max_Data=65535
2860 * @retval None
2861 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2862 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2863 {
2864 WRITE_REG(TIMx->CCR2, CompareValue);
2865 }
2866
2867 /**
2868 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2869 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2870 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2871 * whether or not a timer instance supports a 32 bits counter.
2872 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2873 * output channel is supported by a timer instance.
2874 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2875 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2876 * @param TIMx Timer instance
2877 * @param CompareValue between Min_Data=0 and Max_Data=65535
2878 * @retval None
2879 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2880 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2881 {
2882 WRITE_REG(TIMx->CCR3, CompareValue);
2883 }
2884
2885 /**
2886 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2887 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2888 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2889 * whether or not a timer instance supports a 32 bits counter.
2890 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2891 * output channel 4 is supported by a timer instance.
2892 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2893 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2894 * @param TIMx Timer instance
2895 * @param CompareValue between Min_Data=0 and Max_Data=65535
2896 * @retval None
2897 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2898 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2899 {
2900 WRITE_REG(TIMx->CCR4, CompareValue);
2901 }
2902
2903 /**
2904 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2905 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2906 * output channel 5 is supported by a timer instance.
2907 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2908 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2909 * @param TIMx Timer instance
2910 * @param CompareValue between Min_Data=0 and Max_Data=65535
2911 * @retval None
2912 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2913 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2914 {
2915 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2916 }
2917
2918 /**
2919 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2920 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2921 * output channel 6 is supported by a timer instance.
2922 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2923 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2924 * @param TIMx Timer instance
2925 * @param CompareValue between Min_Data=0 and Max_Data=65535
2926 * @retval None
2927 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2928 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2929 {
2930 WRITE_REG(TIMx->CCR6, CompareValue);
2931 }
2932
2933 /**
2934 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2935 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2936 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2937 * whether or not a timer instance supports a 32 bits counter.
2938 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2939 * output channel 1 is supported by a timer instance.
2940 * @note If dithering is activated, pay attention to the returned value interpretation.
2941 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2942 * @param TIMx Timer instance
2943 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2944 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2945 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2946 {
2947 return (uint32_t)(READ_REG(TIMx->CCR1));
2948 }
2949
2950 /**
2951 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2952 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2953 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2954 * whether or not a timer instance supports a 32 bits counter.
2955 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2956 * output channel 2 is supported by a timer instance.
2957 * @note If dithering is activated, pay attention to the returned value interpretation.
2958 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2959 * @param TIMx Timer instance
2960 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2961 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2962 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2963 {
2964 return (uint32_t)(READ_REG(TIMx->CCR2));
2965 }
2966
2967 /**
2968 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2969 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2970 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2971 * whether or not a timer instance supports a 32 bits counter.
2972 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2973 * output channel 3 is supported by a timer instance.
2974 * @note If dithering is activated, pay attention to the returned value interpretation.
2975 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2976 * @param TIMx Timer instance
2977 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2978 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2979 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2980 {
2981 return (uint32_t)(READ_REG(TIMx->CCR3));
2982 }
2983
2984 /**
2985 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2986 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2987 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2988 * whether or not a timer instance supports a 32 bits counter.
2989 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2990 * output channel 4 is supported by a timer instance.
2991 * @note If dithering is activated, pay attention to the returned value interpretation.
2992 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2993 * @param TIMx Timer instance
2994 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2995 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2996 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2997 {
2998 return (uint32_t)(READ_REG(TIMx->CCR4));
2999 }
3000
3001 /**
3002 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3003 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3004 * output channel 5 is supported by a timer instance.
3005 * @note If dithering is activated, pay attention to the returned value interpretation.
3006 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3007 * @param TIMx Timer instance
3008 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3009 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3010 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3011 {
3012 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3013 }
3014
3015 /**
3016 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3017 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3018 * output channel 6 is supported by a timer instance.
3019 * @note If dithering is activated, pay attention to the returned value interpretation.
3020 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3021 * @param TIMx Timer instance
3022 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3023 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3024 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3025 {
3026 return (uint32_t)(READ_REG(TIMx->CCR6));
3027 }
3028
3029 /**
3030 * @brief Select on which reference signal the OC5REF is combined to.
3031 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3032 * whether or not a timer instance supports the combined 3-phase PWM mode.
3033 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3034 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3035 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3036 * @param TIMx Timer instance
3037 * @param GroupCH5 This parameter can be a combination of the following values:
3038 * @arg @ref LL_TIM_GROUPCH5_NONE
3039 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3040 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3041 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3042 * @retval None
3043 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3044 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3045 {
3046 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3047 }
3048
3049 /**
3050 * @brief Set the pulse on compare pulse width prescaler.
3051 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3052 * whether or not the pulse on compare feature is supported by the timer
3053 * instance.
3054 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3055 * @param TIMx Timer instance
3056 * @param PulseWidthPrescaler This parameter can be one of the following values:
3057 * @arg @ref LL_TIM_PWPRSC_X1
3058 * @arg @ref LL_TIM_PWPRSC_X2
3059 * @arg @ref LL_TIM_PWPRSC_X4
3060 * @arg @ref LL_TIM_PWPRSC_X8
3061 * @arg @ref LL_TIM_PWPRSC_X16
3062 * @arg @ref LL_TIM_PWPRSC_X32
3063 * @arg @ref LL_TIM_PWPRSC_X64
3064 * @arg @ref LL_TIM_PWPRSC_X128
3065 * @retval None
3066 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3067 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3068 {
3069 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3070 }
3071
3072 /**
3073 * @brief Get the pulse on compare pulse width prescaler.
3074 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3075 * whether or not the pulse on compare feature is supported by the timer
3076 * instance.
3077 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3078 * @param TIMx Timer instance
3079 * @retval Returned value can be one of the following values:
3080 * @arg @ref LL_TIM_PWPRSC_X1
3081 * @arg @ref LL_TIM_PWPRSC_X2
3082 * @arg @ref LL_TIM_PWPRSC_X4
3083 * @arg @ref LL_TIM_PWPRSC_X8
3084 * @arg @ref LL_TIM_PWPRSC_X16
3085 * @arg @ref LL_TIM_PWPRSC_X32
3086 * @arg @ref LL_TIM_PWPRSC_X64
3087 * @arg @ref LL_TIM_PWPRSC_X128
3088 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3089 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3090 {
3091 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3092 }
3093
3094 /**
3095 * @brief Set the pulse on compare pulse width duration.
3096 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3097 * whether or not the pulse on compare feature is supported by the timer
3098 * instance.
3099 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3100 * @param TIMx Timer instance
3101 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3102 * @retval None
3103 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3104 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3105 {
3106 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3107 }
3108
3109 /**
3110 * @brief Get the pulse on compare pulse width duration.
3111 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3112 * whether or not the pulse on compare feature is supported by the timer
3113 * instance.
3114 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3115 * @param TIMx Timer instance
3116 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3117 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3118 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3119 {
3120 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3121 }
3122
3123 /**
3124 * @}
3125 */
3126
3127 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3128 * @{
3129 */
3130 /**
3131 * @brief Configure input channel.
3132 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3133 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3134 * CCMR1 IC1F LL_TIM_IC_Config\n
3135 * CCMR1 CC2S LL_TIM_IC_Config\n
3136 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3137 * CCMR1 IC2F LL_TIM_IC_Config\n
3138 * CCMR2 CC3S LL_TIM_IC_Config\n
3139 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3140 * CCMR2 IC3F LL_TIM_IC_Config\n
3141 * CCMR2 CC4S LL_TIM_IC_Config\n
3142 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3143 * CCMR2 IC4F LL_TIM_IC_Config\n
3144 * CCER CC1P LL_TIM_IC_Config\n
3145 * CCER CC1NP LL_TIM_IC_Config\n
3146 * CCER CC2P LL_TIM_IC_Config\n
3147 * CCER CC2NP LL_TIM_IC_Config\n
3148 * CCER CC3P LL_TIM_IC_Config\n
3149 * CCER CC3NP LL_TIM_IC_Config\n
3150 * CCER CC4P LL_TIM_IC_Config\n
3151 * CCER CC4NP LL_TIM_IC_Config
3152 * @param TIMx Timer instance
3153 * @param Channel This parameter can be one of the following values:
3154 * @arg @ref LL_TIM_CHANNEL_CH1
3155 * @arg @ref LL_TIM_CHANNEL_CH2
3156 * @arg @ref LL_TIM_CHANNEL_CH3
3157 * @arg @ref LL_TIM_CHANNEL_CH4
3158 * @param Configuration This parameter must be a combination of all the following values:
3159 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3160 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3161 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3162 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3163 * @retval None
3164 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3165 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3166 {
3167 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3168 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3169 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3170 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3171 << SHIFT_TAB_ICxx[iChannel]);
3172 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3173 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3174 }
3175
3176 /**
3177 * @brief Set the active input.
3178 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3179 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3180 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3181 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3182 * @param TIMx Timer instance
3183 * @param Channel This parameter can be one of the following values:
3184 * @arg @ref LL_TIM_CHANNEL_CH1
3185 * @arg @ref LL_TIM_CHANNEL_CH2
3186 * @arg @ref LL_TIM_CHANNEL_CH3
3187 * @arg @ref LL_TIM_CHANNEL_CH4
3188 * @param ICActiveInput This parameter can be one of the following values:
3189 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3190 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3191 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3192 * @retval None
3193 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3194 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3195 {
3196 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3197 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3198 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3199 }
3200
3201 /**
3202 * @brief Get the current active input.
3203 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3204 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3205 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3206 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3207 * @param TIMx Timer instance
3208 * @param Channel This parameter can be one of the following values:
3209 * @arg @ref LL_TIM_CHANNEL_CH1
3210 * @arg @ref LL_TIM_CHANNEL_CH2
3211 * @arg @ref LL_TIM_CHANNEL_CH3
3212 * @arg @ref LL_TIM_CHANNEL_CH4
3213 * @retval Returned value can be one of the following values:
3214 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3215 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3216 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3217 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3218 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3219 {
3220 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3221 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3222 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3223 }
3224
3225 /**
3226 * @brief Set the prescaler of input channel.
3227 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3228 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3229 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3230 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3231 * @param TIMx Timer instance
3232 * @param Channel This parameter can be one of the following values:
3233 * @arg @ref LL_TIM_CHANNEL_CH1
3234 * @arg @ref LL_TIM_CHANNEL_CH2
3235 * @arg @ref LL_TIM_CHANNEL_CH3
3236 * @arg @ref LL_TIM_CHANNEL_CH4
3237 * @param ICPrescaler This parameter can be one of the following values:
3238 * @arg @ref LL_TIM_ICPSC_DIV1
3239 * @arg @ref LL_TIM_ICPSC_DIV2
3240 * @arg @ref LL_TIM_ICPSC_DIV4
3241 * @arg @ref LL_TIM_ICPSC_DIV8
3242 * @retval None
3243 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3244 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3245 {
3246 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3247 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3248 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3249 }
3250
3251 /**
3252 * @brief Get the current prescaler value acting on an input channel.
3253 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3254 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3255 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3256 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3257 * @param TIMx Timer instance
3258 * @param Channel This parameter can be one of the following values:
3259 * @arg @ref LL_TIM_CHANNEL_CH1
3260 * @arg @ref LL_TIM_CHANNEL_CH2
3261 * @arg @ref LL_TIM_CHANNEL_CH3
3262 * @arg @ref LL_TIM_CHANNEL_CH4
3263 * @retval Returned value can be one of the following values:
3264 * @arg @ref LL_TIM_ICPSC_DIV1
3265 * @arg @ref LL_TIM_ICPSC_DIV2
3266 * @arg @ref LL_TIM_ICPSC_DIV4
3267 * @arg @ref LL_TIM_ICPSC_DIV8
3268 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3269 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3270 {
3271 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3272 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3273 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3274 }
3275
3276 /**
3277 * @brief Set the input filter duration.
3278 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3279 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3280 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3281 * CCMR2 IC4F LL_TIM_IC_SetFilter
3282 * @param TIMx Timer instance
3283 * @param Channel This parameter can be one of the following values:
3284 * @arg @ref LL_TIM_CHANNEL_CH1
3285 * @arg @ref LL_TIM_CHANNEL_CH2
3286 * @arg @ref LL_TIM_CHANNEL_CH3
3287 * @arg @ref LL_TIM_CHANNEL_CH4
3288 * @param ICFilter This parameter can be one of the following values:
3289 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3290 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3291 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3292 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3293 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3294 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3295 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3296 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3297 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3298 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3299 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3300 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3301 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3302 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3303 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3304 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3305 * @retval None
3306 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3307 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3308 {
3309 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3310 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3311 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3312 }
3313
3314 /**
3315 * @brief Get the input filter duration.
3316 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3317 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3318 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3319 * CCMR2 IC4F LL_TIM_IC_GetFilter
3320 * @param TIMx Timer instance
3321 * @param Channel This parameter can be one of the following values:
3322 * @arg @ref LL_TIM_CHANNEL_CH1
3323 * @arg @ref LL_TIM_CHANNEL_CH2
3324 * @arg @ref LL_TIM_CHANNEL_CH3
3325 * @arg @ref LL_TIM_CHANNEL_CH4
3326 * @retval Returned value can be one of the following values:
3327 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3328 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3329 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3330 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3331 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3332 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3333 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3334 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3335 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3336 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3337 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3338 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3339 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3340 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3341 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3342 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3343 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3344 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3345 {
3346 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3347 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3348 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3349 }
3350
3351 /**
3352 * @brief Set the input channel polarity.
3353 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3354 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3355 * CCER CC2P LL_TIM_IC_SetPolarity\n
3356 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3357 * CCER CC3P LL_TIM_IC_SetPolarity\n
3358 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3359 * CCER CC4P LL_TIM_IC_SetPolarity\n
3360 * CCER CC4NP LL_TIM_IC_SetPolarity
3361 * @param TIMx Timer instance
3362 * @param Channel This parameter can be one of the following values:
3363 * @arg @ref LL_TIM_CHANNEL_CH1
3364 * @arg @ref LL_TIM_CHANNEL_CH2
3365 * @arg @ref LL_TIM_CHANNEL_CH3
3366 * @arg @ref LL_TIM_CHANNEL_CH4
3367 * @param ICPolarity This parameter can be one of the following values:
3368 * @arg @ref LL_TIM_IC_POLARITY_RISING
3369 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3370 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3371 * @retval None
3372 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3373 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3374 {
3375 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3376 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3377 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3378 }
3379
3380 /**
3381 * @brief Get the current input channel polarity.
3382 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3383 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3384 * CCER CC2P LL_TIM_IC_GetPolarity\n
3385 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3386 * CCER CC3P LL_TIM_IC_GetPolarity\n
3387 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3388 * CCER CC4P LL_TIM_IC_GetPolarity\n
3389 * CCER CC4NP LL_TIM_IC_GetPolarity
3390 * @param TIMx Timer instance
3391 * @param Channel This parameter can be one of the following values:
3392 * @arg @ref LL_TIM_CHANNEL_CH1
3393 * @arg @ref LL_TIM_CHANNEL_CH2
3394 * @arg @ref LL_TIM_CHANNEL_CH3
3395 * @arg @ref LL_TIM_CHANNEL_CH4
3396 * @retval Returned value can be one of the following values:
3397 * @arg @ref LL_TIM_IC_POLARITY_RISING
3398 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3399 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3400 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3401 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3402 {
3403 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3404 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3405 SHIFT_TAB_CCxP[iChannel]);
3406 }
3407
3408 /**
3409 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3410 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3411 * a timer instance provides an XOR input.
3412 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3413 * @param TIMx Timer instance
3414 * @retval None
3415 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3416 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3417 {
3418 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3419 }
3420
3421 /**
3422 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3423 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3424 * a timer instance provides an XOR input.
3425 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3426 * @param TIMx Timer instance
3427 * @retval None
3428 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3429 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3430 {
3431 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3432 }
3433
3434 /**
3435 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3436 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3437 * a timer instance provides an XOR input.
3438 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3439 * @param TIMx Timer instance
3440 * @retval State of bit (1 or 0).
3441 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3442 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3443 {
3444 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3445 }
3446
3447 /**
3448 * @brief Get captured value for input channel 1.
3449 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3450 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3451 * whether or not a timer instance supports a 32 bits counter.
3452 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3453 * input channel 1 is supported by a timer instance.
3454 * @note If dithering is activated, pay attention to the returned value interpretation.
3455 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3456 * @param TIMx Timer instance
3457 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3458 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3459 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3460 {
3461 return (uint32_t)(READ_REG(TIMx->CCR1));
3462 }
3463
3464 /**
3465 * @brief Get captured value for input channel 2.
3466 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3467 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3468 * whether or not a timer instance supports a 32 bits counter.
3469 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3470 * input channel 2 is supported by a timer instance.
3471 * @note If dithering is activated, pay attention to the returned value interpretation.
3472 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3473 * @param TIMx Timer instance
3474 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3475 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3476 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3477 {
3478 return (uint32_t)(READ_REG(TIMx->CCR2));
3479 }
3480
3481 /**
3482 * @brief Get captured value for input channel 3.
3483 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3484 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3485 * whether or not a timer instance supports a 32 bits counter.
3486 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3487 * input channel 3 is supported by a timer instance.
3488 * @note If dithering is activated, pay attention to the returned value interpretation.
3489 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3490 * @param TIMx Timer instance
3491 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3492 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3493 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3494 {
3495 return (uint32_t)(READ_REG(TIMx->CCR3));
3496 }
3497
3498 /**
3499 * @brief Get captured value for input channel 4.
3500 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3501 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3502 * whether or not a timer instance supports a 32 bits counter.
3503 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3504 * input channel 4 is supported by a timer instance.
3505 * @note If dithering is activated, pay attention to the returned value interpretation.
3506 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3507 * @param TIMx Timer instance
3508 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3509 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3510 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3511 {
3512 return (uint32_t)(READ_REG(TIMx->CCR4));
3513 }
3514
3515 /**
3516 * @}
3517 */
3518
3519 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3520 * @{
3521 */
3522 /**
3523 * @brief Enable external clock mode 2.
3524 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3525 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3526 * whether or not a timer instance supports external clock mode2.
3527 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3528 * @param TIMx Timer instance
3529 * @retval None
3530 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3531 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3532 {
3533 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3534 }
3535
3536 /**
3537 * @brief Disable external clock mode 2.
3538 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3539 * whether or not a timer instance supports external clock mode2.
3540 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3541 * @param TIMx Timer instance
3542 * @retval None
3543 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3544 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3545 {
3546 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3547 }
3548
3549 /**
3550 * @brief Indicate whether external clock mode 2 is enabled.
3551 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3552 * whether or not a timer instance supports external clock mode2.
3553 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3554 * @param TIMx Timer instance
3555 * @retval State of bit (1 or 0).
3556 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3557 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3558 {
3559 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3560 }
3561
3562 /**
3563 * @brief Set the clock source of the counter clock.
3564 * @note when selected clock source is external clock mode 1, the timer input
3565 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3566 * function. This timer input must be configured by calling
3567 * the @ref LL_TIM_IC_Config() function.
3568 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3569 * whether or not a timer instance supports external clock mode1.
3570 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3571 * whether or not a timer instance supports external clock mode2.
3572 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3573 * SMCR ECE LL_TIM_SetClockSource
3574 * @param TIMx Timer instance
3575 * @param ClockSource This parameter can be one of the following values:
3576 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3577 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3578 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3579 * @retval None
3580 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3581 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3582 {
3583 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3584 }
3585
3586 /**
3587 * @brief Set the encoder interface mode.
3588 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3589 * whether or not a timer instance supports the encoder mode.
3590 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3591 * @param TIMx Timer instance
3592 * @param EncoderMode This parameter can be one of the following values:
3593 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3594 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3595 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3596 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3597 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3598 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3599 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3600 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3601 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3602 * @retval None
3603 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3604 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3605 {
3606 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3607 }
3608
3609 /**
3610 * @}
3611 */
3612
3613 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3614 * @{
3615 */
3616 /**
3617 * @brief Set the trigger output (TRGO) used for timer synchronization .
3618 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3619 * whether or not a timer instance can operate as a master timer.
3620 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3621 * @param TIMx Timer instance
3622 * @param TimerSynchronization This parameter can be one of the following values:
3623 * @arg @ref LL_TIM_TRGO_RESET
3624 * @arg @ref LL_TIM_TRGO_ENABLE
3625 * @arg @ref LL_TIM_TRGO_UPDATE
3626 * @arg @ref LL_TIM_TRGO_CC1IF
3627 * @arg @ref LL_TIM_TRGO_OC1REF
3628 * @arg @ref LL_TIM_TRGO_OC2REF
3629 * @arg @ref LL_TIM_TRGO_OC3REF
3630 * @arg @ref LL_TIM_TRGO_OC4REF
3631 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3632 * @retval None
3633 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3634 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3635 {
3636 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3637 }
3638
3639 /**
3640 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3641 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3642 * whether or not a timer instance can be used for ADC synchronization.
3643 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3644 * @param TIMx Timer Instance
3645 * @param ADCSynchronization This parameter can be one of the following values:
3646 * @arg @ref LL_TIM_TRGO2_RESET
3647 * @arg @ref LL_TIM_TRGO2_ENABLE
3648 * @arg @ref LL_TIM_TRGO2_UPDATE
3649 * @arg @ref LL_TIM_TRGO2_CC1F
3650 * @arg @ref LL_TIM_TRGO2_OC1
3651 * @arg @ref LL_TIM_TRGO2_OC2
3652 * @arg @ref LL_TIM_TRGO2_OC3
3653 * @arg @ref LL_TIM_TRGO2_OC4
3654 * @arg @ref LL_TIM_TRGO2_OC5
3655 * @arg @ref LL_TIM_TRGO2_OC6
3656 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3657 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3658 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3659 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3660 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3661 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3662 * @retval None
3663 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3664 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3665 {
3666 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3667 }
3668
3669 /**
3670 * @brief Set the synchronization mode of a slave timer.
3671 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3672 * a timer instance can operate as a slave timer.
3673 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3674 * @param TIMx Timer instance
3675 * @param SlaveMode This parameter can be one of the following values:
3676 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3677 * @arg @ref LL_TIM_SLAVEMODE_RESET
3678 * @arg @ref LL_TIM_SLAVEMODE_GATED
3679 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3680 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3681 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3682 * @retval None
3683 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3684 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3685 {
3686 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3687 }
3688
3689 /**
3690 * @brief Set the selects the trigger input to be used to synchronize the counter.
3691 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3692 * a timer instance can operate as a slave timer.
3693 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3694 * @param TIMx Timer instance
3695 * @param TriggerInput This parameter can be one of the following values:
3696 * @arg @ref LL_TIM_TS_ITR0
3697 * @arg @ref LL_TIM_TS_ITR1
3698 * @arg @ref LL_TIM_TS_ITR2
3699 * @arg @ref LL_TIM_TS_ITR7
3700 * @arg @ref LL_TIM_TS_ITR8
3701 * @arg @ref LL_TIM_TS_TI1F_ED
3702 * @arg @ref LL_TIM_TS_TI1FP1
3703 * @arg @ref LL_TIM_TS_TI2FP2
3704 * @arg @ref LL_TIM_TS_ETRF
3705 * @retval None
3706 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3707 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3708 {
3709 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3710 }
3711
3712 /**
3713 * @brief Enable the Master/Slave mode.
3714 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3715 * a timer instance can operate as a slave timer.
3716 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3717 * @param TIMx Timer instance
3718 * @retval None
3719 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3720 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3721 {
3722 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3723 }
3724
3725 /**
3726 * @brief Disable the Master/Slave mode.
3727 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3728 * a timer instance can operate as a slave timer.
3729 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3730 * @param TIMx Timer instance
3731 * @retval None
3732 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3733 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3734 {
3735 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3736 }
3737
3738 /**
3739 * @brief Indicates whether the Master/Slave mode is enabled.
3740 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3741 * a timer instance can operate as a slave timer.
3742 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3743 * @param TIMx Timer instance
3744 * @retval State of bit (1 or 0).
3745 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3746 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3747 {
3748 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3749 }
3750
3751 /**
3752 * @brief Configure the external trigger (ETR) input.
3753 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3754 * a timer instance provides an external trigger input.
3755 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3756 * SMCR ETPS LL_TIM_ConfigETR\n
3757 * SMCR ETF LL_TIM_ConfigETR
3758 * @param TIMx Timer instance
3759 * @param ETRPolarity This parameter can be one of the following values:
3760 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3761 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3762 * @param ETRPrescaler This parameter can be one of the following values:
3763 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3764 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3765 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3766 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3767 * @param ETRFilter This parameter can be one of the following values:
3768 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3769 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3770 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3771 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3772 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3773 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3774 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3775 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3776 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3777 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3778 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3779 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3780 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3781 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3782 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3783 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3784 * @retval None
3785 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3786 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3787 uint32_t ETRFilter)
3788 {
3789 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3790 }
3791
3792 /**
3793 * @brief Select the external trigger (ETR) input source.
3794 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3795 * not a timer instance supports ETR source selection.
3796 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3797 * @param TIMx Timer instance
3798 * @param ETRSource This parameter can be one of the following values:
3799 *
3800 * For TIM1, the parameter is one of the following values:
3801 *
3802 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3803 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*)
3804 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*)
3805 * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI
3806 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
3807 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
3808 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
3809 *
3810 * For TIM2, the parameter is one of the following values:
3811 *
3812 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3813 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*)
3814 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*)
3815 * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI
3816 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
3817 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
3818 *
3819 * For TIM3, the parameter is one of the following values:
3820 *
3821 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3822 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*)
3823 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*)
3824 * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI
3825 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
3826 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1
3827 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2
3828 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3
3829 *
3830 * (*) Value not defined in all devices. \n
3831 * @retval None
3832 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3833 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3834 {
3835 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3836 }
3837
3838 /**
3839 * @brief Enable SMS preload.
3840 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3841 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3842 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
3843 * @param TIMx Timer instance
3844 * @retval None
3845 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)3846 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
3847 {
3848 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3849 }
3850
3851 /**
3852 * @brief Disable SMS preload.
3853 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3854 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3855 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
3856 * @param TIMx Timer instance
3857 * @retval None
3858 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)3859 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
3860 {
3861 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3862 }
3863
3864 /**
3865 * @brief Indicate whether SMS preload is enabled.
3866 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3867 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3868 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
3869 * @param TIMx Timer instance
3870 * @retval State of bit (1 or 0).
3871 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)3872 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
3873 {
3874 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
3875 }
3876
3877 /**
3878 * @brief Set the preload source of SMS.
3879 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3880 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3881 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
3882 * @param TIMx Timer instance
3883 * @param PreloadSource This parameter can be one of the following values:
3884 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
3885 * @arg @ref LL_TIM_SMSPS_INDEX
3886 * @retval None
3887 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)3888 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
3889 {
3890 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
3891 }
3892
3893 /**
3894 * @brief Get the preload source of SMS.
3895 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3896 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3897 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
3898 * @param TIMx Timer instance
3899 * @retval Returned value can be one of the following values:
3900 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
3901 * @arg @ref LL_TIM_SMSPS_INDEX
3902 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)3903 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
3904 {
3905 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
3906 }
3907
3908 /**
3909 * @}
3910 */
3911
3912 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3913 * @{
3914 */
3915 /**
3916 * @brief Enable the break function.
3917 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3918 * a timer instance provides a break input.
3919 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3920 * @param TIMx Timer instance
3921 * @retval None
3922 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3923 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3924 {
3925 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3926 }
3927
3928 /**
3929 * @brief Disable the break function.
3930 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3931 * @param TIMx Timer instance
3932 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3933 * a timer instance provides a break input.
3934 * @retval None
3935 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3936 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3937 {
3938 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3939 }
3940
3941 /**
3942 * @brief Configure the break input.
3943 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3944 * a timer instance provides a break input.
3945 * @note Bidirectional mode is only supported by advanced timer instances.
3946 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3947 * a timer instance is an advanced-control timer.
3948 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3949 * in input mode and in open drain output mode. Any active Break event will
3950 * assert a low logic level on the Break input to indicate an internal break
3951 * event to external devices.
3952 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3953 * LL_TIM_BREAK_AFMODE_INPUT.
3954 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3955 * BDTR BKF LL_TIM_ConfigBRK\n
3956 * BDTR BKBID LL_TIM_ConfigBRK
3957 * @param TIMx Timer instance
3958 * @param BreakPolarity This parameter can be one of the following values:
3959 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3960 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3961 * @param BreakFilter This parameter can be one of the following values:
3962 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3963 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3964 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3965 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3966 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3967 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3968 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3969 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3970 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3971 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3972 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3973 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3974 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3975 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3976 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3977 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3978 * @param BreakAFMode This parameter can be one of the following values:
3979 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3980 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3981 * @retval None
3982 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3983 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3984 uint32_t BreakAFMode)
3985 {
3986 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3987 }
3988
3989 /**
3990 * @brief Disarm the break input (when it operates in bidirectional mode).
3991 * @note The break input can be disarmed only when it is configured in
3992 * bidirectional mode and when when MOE is reset.
3993 * @note Purpose is to be able to have the input voltage back to high-state,
3994 * whatever the time constant on the output .
3995 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3996 * @param TIMx Timer instance
3997 * @retval None
3998 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3999 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4000 {
4001 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4002 }
4003
4004 /**
4005 * @brief Enable the break 2 function.
4006 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4007 * a timer instance provides a second break input.
4008 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4009 * @param TIMx Timer instance
4010 * @retval None
4011 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4012 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4013 {
4014 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4015 }
4016
4017 /**
4018 * @brief Disable the break 2 function.
4019 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4020 * a timer instance provides a second break input.
4021 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4022 * @param TIMx Timer instance
4023 * @retval None
4024 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4025 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4026 {
4027 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4028 }
4029
4030 /**
4031 * @brief Configure the break 2 input.
4032 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4033 * a timer instance provides a second break input.
4034 * @note Bidirectional mode is only supported by advanced timer instances.
4035 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4036 * a timer instance is an advanced-control timer.
4037 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4038 * in input mode and in open drain output mode. Any active Break event will
4039 * assert a low logic level on the Break 2 input to indicate an internal break
4040 * event to external devices.
4041 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4042 * LL_TIM_BREAK2_AFMODE_INPUT.
4043 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4044 * BDTR BK2F LL_TIM_ConfigBRK2\n
4045 * BDTR BK2BID LL_TIM_ConfigBRK2
4046 * @param TIMx Timer instance
4047 * @param Break2Polarity This parameter can be one of the following values:
4048 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4049 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4050 * @param Break2Filter This parameter can be one of the following values:
4051 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4052 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4053 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4054 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4055 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4056 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4057 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4058 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4059 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4060 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4061 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4062 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4063 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4064 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4065 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4066 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4067 * @param Break2AFMode This parameter can be one of the following values:
4068 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4069 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4070 * @retval None
4071 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4072 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4073 uint32_t Break2AFMode)
4074 {
4075 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4076 }
4077
4078 /**
4079 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4080 * @note The break 2 input can be disarmed only when it is configured in
4081 * bidirectional mode and when when MOE is reset.
4082 * @note Purpose is to be able to have the input voltage back to high-state,
4083 * whatever the time constant on the output.
4084 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4085 * @param TIMx Timer instance
4086 * @retval None
4087 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4088 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4089 {
4090 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4091 }
4092
4093 /**
4094 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4095 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4096 * a timer instance provides a break input.
4097 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4098 * BDTR OSSR LL_TIM_SetOffStates
4099 * @param TIMx Timer instance
4100 * @param OffStateIdle This parameter can be one of the following values:
4101 * @arg @ref LL_TIM_OSSI_DISABLE
4102 * @arg @ref LL_TIM_OSSI_ENABLE
4103 * @param OffStateRun This parameter can be one of the following values:
4104 * @arg @ref LL_TIM_OSSR_DISABLE
4105 * @arg @ref LL_TIM_OSSR_ENABLE
4106 * @retval None
4107 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4108 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4109 {
4110 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4111 }
4112
4113 /**
4114 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4115 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4116 * a timer instance provides a break input.
4117 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4118 * @param TIMx Timer instance
4119 * @retval None
4120 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4121 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4122 {
4123 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4124 }
4125
4126 /**
4127 * @brief Disable automatic output (MOE can be set only by software).
4128 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4129 * a timer instance provides a break input.
4130 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4131 * @param TIMx Timer instance
4132 * @retval None
4133 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4134 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4135 {
4136 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4137 }
4138
4139 /**
4140 * @brief Indicate whether automatic output is enabled.
4141 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4142 * a timer instance provides a break input.
4143 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4144 * @param TIMx Timer instance
4145 * @retval State of bit (1 or 0).
4146 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4147 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4148 {
4149 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4150 }
4151
4152 /**
4153 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4154 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4155 * software and is reset in case of break or break2 event
4156 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4157 * a timer instance provides a break input.
4158 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4159 * @param TIMx Timer instance
4160 * @retval None
4161 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4162 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4163 {
4164 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4165 }
4166
4167 /**
4168 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4169 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4170 * software and is reset in case of break or break2 event.
4171 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4172 * a timer instance provides a break input.
4173 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4174 * @param TIMx Timer instance
4175 * @retval None
4176 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4177 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4178 {
4179 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4180 }
4181
4182 /**
4183 * @brief Indicates whether outputs are enabled.
4184 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4185 * a timer instance provides a break input.
4186 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4187 * @param TIMx Timer instance
4188 * @retval State of bit (1 or 0).
4189 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4190 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4191 {
4192 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4193 }
4194
4195 /**
4196 * @brief Enable the signals connected to the designated timer break input.
4197 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4198 * or not a timer instance allows for break input selection.
4199 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4200 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4201 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4202 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4203 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4204 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4205 * @param TIMx Timer instance
4206 * @param BreakInput This parameter can be one of the following values:
4207 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4208 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4209 * @param Source This parameter can be one of the following values:
4210 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4211 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4212 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4213 * @retval None
4214 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4215 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4216 {
4217 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4218 SET_BIT(*pReg, Source);
4219 }
4220
4221 /**
4222 * @brief Disable the signals connected to the designated timer break input.
4223 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4224 * or not a timer instance allows for break input selection.
4225 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4226 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4227 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4228 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4229 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4230 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
4231 * @param TIMx Timer instance
4232 * @param BreakInput This parameter can be one of the following values:
4233 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4234 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4235 * @param Source This parameter can be one of the following values:
4236 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4237 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4238 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4239 * @retval None
4240 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4241 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4242 {
4243 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4244 CLEAR_BIT(*pReg, Source);
4245 }
4246
4247 /**
4248 * @brief Set the polarity of the break signal for the timer break input.
4249 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4250 * or not a timer instance allows for break input selection.
4251 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4252 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4253 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4254 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4255 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4256 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
4257 * @param TIMx Timer instance
4258 * @param BreakInput This parameter can be one of the following values:
4259 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4260 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4261 * @param Source This parameter can be one of the following values:
4262 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4263 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4264 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4265 * @param Polarity This parameter can be one of the following values:
4266 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4267 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4268 * @retval None
4269 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4270 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4271 uint32_t Polarity)
4272 {
4273 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4274 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4275 }
4276 /**
4277 * @brief Enable asymmetrical deadtime.
4278 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4279 * a timer instance provides asymmetrical deadtime.
4280 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4281 * @param TIMx Timer instance
4282 * @retval None
4283 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4284 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4285 {
4286 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4287 }
4288
4289 /**
4290 * @brief Disable asymmetrical dead-time.
4291 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4292 * a timer instance provides asymmetrical deadtime.
4293 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4294 * @param TIMx Timer instance
4295 * @retval None
4296 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4297 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4298 {
4299 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4300 }
4301
4302 /**
4303 * @brief Indicates whether asymmetrical deadtime is activated.
4304 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4305 * a timer instance provides asymmetrical deadtime.
4306 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4307 * @param TIMx Timer instance
4308 * @retval State of bit (1 or 0).
4309 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4310 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4311 {
4312 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4313 }
4314
4315 /**
4316 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4317 * rising edge of OCxN signals).
4318 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4319 * asymmetrical dead-time insertion feature is supported by a timer instance.
4320 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4321 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4322 * (LOCK bits in TIMx_BDTR register).
4323 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4324 * @param TIMx Timer instance
4325 * @param DeadTime between Min_Data=0 and Max_Data=255
4326 * @retval None
4327 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4328 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4329 {
4330 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4331 }
4332
4333 /**
4334 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4335 * the rising edge of OCxN signals).
4336 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4337 * asymmetrical dead-time insertion feature is supported by a timer instance.
4338 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4339 * (LOCK bits in TIMx_BDTR register).
4340 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4341 * @param TIMx Timer instance
4342 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4343 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4344 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4345 {
4346 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4347 }
4348
4349 /**
4350 * @brief Enable deadtime preload.
4351 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4352 * a timer instance provides deadtime preload.
4353 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4354 * @param TIMx Timer instance
4355 * @retval None
4356 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4357 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4358 {
4359 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4360 }
4361
4362 /**
4363 * @brief Disable dead-time preload.
4364 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4365 * a timer instance provides deadtime preload.
4366 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4367 * @param TIMx Timer instance
4368 * @retval None
4369 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4370 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4371 {
4372 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4373 }
4374
4375 /**
4376 * @brief Indicates whether deadtime preload is activated.
4377 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4378 * a timer instance provides deadtime preload.
4379 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4380 * @param TIMx Timer instance
4381 * @retval State of bit (1 or 0).
4382 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4383 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4384 {
4385 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4386 }
4387
4388 /**
4389 * @}
4390 */
4391
4392 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4393 * @{
4394 */
4395 /**
4396 * @brief Configures the timer DMA burst feature.
4397 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4398 * not a timer instance supports the DMA burst mode.
4399 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4400 * DCR DBA LL_TIM_ConfigDMABurst
4401 * @param TIMx Timer instance
4402 * @param DMABurstBaseAddress This parameter can be one of the following values:
4403 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4404 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4405 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4406 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4407 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4408 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4409 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4410 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4411 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4412 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4413 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4414 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4415 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4416 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4417 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4418 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4419 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4420 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4421 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4422 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4423 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4424 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4425 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4426 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4427 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4428 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4429 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
4430 * @param DMABurstLength This parameter can be one of the following values:
4431 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4432 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4433 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4434 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4435 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4436 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4437 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4438 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4439 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4440 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4441 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4442 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4443 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4444 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4445 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4446 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4447 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4448 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4449 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4450 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4451 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4452 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4453 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4454 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4455 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4456 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4457 * @param DMABurstSource This parameter can be one of the following values:
4458 * @arg @ref LL_TIM_DMA_UPDATE
4459 * @arg @ref LL_TIM_DMA_CC1
4460 * @arg @ref LL_TIM_DMA_CC2
4461 * @arg @ref LL_TIM_DMA_CC3
4462 * @arg @ref LL_TIM_DMA_CC4
4463 * @arg @ref LL_TIM_DMA_COM
4464 * @arg @ref LL_TIM_DMA_TRIGGER
4465 * @retval None
4466 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4467 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4468 uint32_t DMABurstSource)
4469 {
4470 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4471 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4472 }
4473
4474 /**
4475 * @}
4476 */
4477
4478 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4479 * @{
4480 */
4481
4482 /**
4483 * @brief Enable encoder index.
4484 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4485 * a timer instance provides an index input.
4486 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4487 * @param TIMx Timer instance
4488 * @retval None
4489 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4490 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4491 {
4492 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4493 }
4494
4495 /**
4496 * @brief Disable encoder index.
4497 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4498 * a timer instance provides an index input.
4499 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4500 * @param TIMx Timer instance
4501 * @retval None
4502 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4503 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4504 {
4505 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4506 }
4507
4508 /**
4509 * @brief Indicate whether encoder index is enabled.
4510 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4511 * a timer instance provides an index input.
4512 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4513 * @param TIMx Timer instance
4514 * @retval State of bit (1 or 0).
4515 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4516 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4517 {
4518 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4519 }
4520
4521 /**
4522 * @brief Set index direction
4523 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4524 * a timer instance provides an index input.
4525 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4526 * @param TIMx Timer instance
4527 * @param IndexDirection This parameter can be one of the following values:
4528 * @arg @ref LL_TIM_INDEX_UP_DOWN
4529 * @arg @ref LL_TIM_INDEX_UP
4530 * @arg @ref LL_TIM_INDEX_DOWN
4531 * @retval None
4532 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4533 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4534 {
4535 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4536 }
4537
4538 /**
4539 * @brief Get actual index direction
4540 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4541 * a timer instance provides an index input.
4542 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4543 * @param TIMx Timer instance
4544 * @retval Returned value can be one of the following values:
4545 * @arg @ref LL_TIM_INDEX_UP_DOWN
4546 * @arg @ref LL_TIM_INDEX_UP
4547 * @arg @ref LL_TIM_INDEX_DOWN
4548 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4549 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4550 {
4551 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4552 }
4553
4554 /**
4555 * @brief Set index blanking
4556 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4557 * a timer instance provides an index input.
4558 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4559 * @param TIMx Timer instance
4560 * @param Indexblanking This parameter can be one of the following values:
4561 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4562 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4563 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4564 * @retval None
4565 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4566 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4567 {
4568 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4569 }
4570
4571 /**
4572 * @brief Get actual index blanking
4573 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4574 * a timer instance provides an index input.
4575 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4576 * @param TIMx Timer instance
4577 * @retval Returned value can be one of the following values:
4578 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4579 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4580 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4581 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4582 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4583 {
4584 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4585 }
4586
4587
4588 /**
4589 * @brief Enable first index.
4590 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4591 * a timer instance provides an index input.
4592 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4593 * @param TIMx Timer instance
4594 * @retval None
4595 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4596 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4597 {
4598 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4599 }
4600
4601 /**
4602 * @brief Disable first index.
4603 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4604 * a timer instance provides an index input.
4605 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4606 * @param TIMx Timer instance
4607 * @retval None
4608 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4609 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4610 {
4611 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4612 }
4613
4614 /**
4615 * @brief Indicates whether first index is enabled.
4616 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4617 * a timer instance provides an index input.
4618 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4619 * @param TIMx Timer instance
4620 * @retval State of bit (1 or 0).
4621 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4622 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4623 {
4624 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4625 }
4626
4627 /**
4628 * @brief Set index positioning
4629 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4630 * a timer instance provides an index input.
4631 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4632 * @param TIMx Timer instance
4633 * @param IndexPositionning This parameter can be one of the following values:
4634 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4635 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4636 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4637 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4638 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4639 * @arg @ref LL_TIM_INDEX_POSITION_UP
4640 * @retval None
4641 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4642 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4643 {
4644 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4645 }
4646
4647 /**
4648 * @brief Get actual index positioning
4649 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4650 * a timer instance provides an index input.
4651 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4652 * @param TIMx Timer instance
4653 * @retval Returned value can be one of the following values:
4654 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4655 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4656 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4657 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4658 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4659 * @arg @ref LL_TIM_INDEX_POSITION_UP
4660 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4661 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4662 {
4663 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
4664 }
4665
4666 /**
4667 * @brief Configure encoder index.
4668 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4669 * a timer instance provides an index input.
4670 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
4671 * ECR IBLK LL_TIM_ConfigIDX\n
4672 * ECR FIDX LL_TIM_ConfigIDX\n
4673 * ECR IPOS LL_TIM_ConfigIDX
4674 * @param TIMx Timer instance
4675 * @param Configuration This parameter must be a combination of all the following values:
4676 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
4677 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
4678 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
4679 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
4680 * @retval None
4681 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)4682 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
4683 {
4684 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
4685 }
4686
4687 /**
4688 * @}
4689 */
4690
4691 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4692 * @{
4693 */
4694 /**
4695 * @brief Remap TIM inputs (input channel, internal/external triggers).
4696 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4697 * a some timer inputs can be remapped.
4698 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
4699 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
4700 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
4701 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
4702 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4703 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
4704 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4705 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
4706 * @param TIMx Timer instance
4707 * @param Remap Remap param depends on the TIMx. Description available only
4708 * in CHM version of the User Manual (not in .pdf).
4709 * Otherwise see Reference Manual description of TISEL registers.
4710 *
4711 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4712 *
4713 * TIM1: one of the following values:
4714 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
4715 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*)
4716 * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*)
4717 *
4718 * TIM2: one of the following values:
4719 * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
4720 * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output (*)
4721 * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output (*)
4722 * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
4723 * @arg LL_TIM_TIM2_TI2_RMP_COMP1: TIM2 TI2 is connected to COMP1 output (*)
4724 * @arg LL_TIM_TIM2_TI2_RMP_COMP2: TIM2 TI2 is connected to COMP2 output (*)
4725 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
4726 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output (*)
4727 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output (*)
4728 *
4729 * TIM3: one of the following values:
4730 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
4731 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*)
4732 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*)
4733 * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
4734 * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*)
4735 * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*)
4736 *
4737 * TIM16: one of the following values:
4738 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
4739 * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO
4740 * @arg LL_TIM_TIM16_TI1_RMP_HSE_DIV32: TIM16 TI1 is connected to HSE DIV32
4741 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC
4742 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
4743 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
4744 * @arg LL_TIM_TIM16_TI1_RMP_HSI_256: TIM16 TI1 is connected to HSI/256
4745 *
4746 * TIM17: one of the following values:
4747 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
4748 * @arg LL_TIM_TIM17_TI1_RMP_MCO: TIM17 TI1 is connected to MCO
4749 * @arg LL_TIM_TIM17_TI1_RMP_HSE_DIV32: TIM17 TI1 is connected to HSE DIV32
4750 * @arg LL_TIM_TIM17_TI1_RMP_RTC: TIM17 TI1 is connected to RTC
4751 * @arg LL_TIM_TIM17_TI1_RMP_LSE: TIM17 TI1 is connected to LSE
4752 * @arg LL_TIM_TIM17_TI1_RMP_LSI: TIM17 TI1 is connected to LSI
4753 * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256
4754 *
4755 * (*) Value not defined in all devices. \n
4756
4757 *
4758 * @retval None
4759 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4760 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4761 {
4762 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4763 }
4764
4765 /**
4766 * @brief Enable request for HSE/32 clock used for TISEL remap.
4767 * @note Only TIM16 and TIM17 support HSE/32 remap
4768 * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
4769 * @param TIMx Timer instance
4770 * @retval None
4771 */
LL_TIM_EnableHSE32(TIM_TypeDef * TIMx)4772 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
4773 {
4774 SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
4775 }
4776
4777 /**
4778 * @brief Disable request for HSE/32 clock used for TISEL remap.
4779 * @note Only TIM16 and TIM17 support HSE/32 remap
4780 * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
4781 * @param TIMx Timer instance
4782 * @retval None
4783 */
LL_TIM_DisableHSE32(TIM_TypeDef * TIMx)4784 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
4785 {
4786 CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
4787 }
4788
4789 /**
4790 * @brief Indicate whether request for HSE/32 clock is enabled.
4791 * @note Only TIM16 and TIM17 support HSE/32 remap
4792 * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
4793 * @param TIMx Timer instance
4794 * @retval State of bit (1 or 0).
4795 */
LL_TIM_IsEnabledHSE32(const TIM_TypeDef * TIMx)4796 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx)
4797 {
4798 return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
4799 }
4800
4801 /**
4802 * @}
4803 */
4804
4805 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4806 * @{
4807 */
4808 /**
4809 * @brief Set the OCREF clear input source
4810 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4811 * @note This function can only be used in Output compare and PWM modes.
4812 * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
4813 * or not a timer instance can configure OCREF clear input source.
4814 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4815 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
4816 * @param TIMx Timer instance
4817 * @param OCRefClearInputSource This parameter can be one of the following values:
4818 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4819 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
4820 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
4821 * @retval None
4822 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4823 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4824 {
4825 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
4826 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
4827 MODIFY_REG(TIMx->AF2, TIM_AF2_OCRSEL, OCRefClearInputSource);
4828 }
4829 /**
4830 * @}
4831 */
4832
4833 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4834 * @{
4835 */
4836 /**
4837 * @brief Clear the update interrupt flag (UIF).
4838 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4839 * @param TIMx Timer instance
4840 * @retval None
4841 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4842 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4843 {
4844 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4845 }
4846
4847 /**
4848 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4849 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4850 * @param TIMx Timer instance
4851 * @retval State of bit (1 or 0).
4852 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4853 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4854 {
4855 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4856 }
4857
4858 /**
4859 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4860 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4861 * @param TIMx Timer instance
4862 * @retval None
4863 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4864 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4865 {
4866 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4867 }
4868
4869 /**
4870 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4871 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4872 * @param TIMx Timer instance
4873 * @retval State of bit (1 or 0).
4874 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4875 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4876 {
4877 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4878 }
4879
4880 /**
4881 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4882 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4883 * @param TIMx Timer instance
4884 * @retval None
4885 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4886 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4887 {
4888 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4889 }
4890
4891 /**
4892 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4893 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4894 * @param TIMx Timer instance
4895 * @retval State of bit (1 or 0).
4896 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4897 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4898 {
4899 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4900 }
4901
4902 /**
4903 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4904 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4905 * @param TIMx Timer instance
4906 * @retval None
4907 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4908 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4909 {
4910 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4911 }
4912
4913 /**
4914 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4915 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4916 * @param TIMx Timer instance
4917 * @retval State of bit (1 or 0).
4918 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4919 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4920 {
4921 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4922 }
4923
4924 /**
4925 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4926 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4927 * @param TIMx Timer instance
4928 * @retval None
4929 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4930 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4931 {
4932 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4933 }
4934
4935 /**
4936 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4937 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4938 * @param TIMx Timer instance
4939 * @retval State of bit (1 or 0).
4940 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4941 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4942 {
4943 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4944 }
4945
4946 /**
4947 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4948 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4949 * @param TIMx Timer instance
4950 * @retval None
4951 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4952 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4953 {
4954 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4955 }
4956
4957 /**
4958 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4959 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4960 * @param TIMx Timer instance
4961 * @retval State of bit (1 or 0).
4962 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4963 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4964 {
4965 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4966 }
4967
4968 /**
4969 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4970 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4971 * @param TIMx Timer instance
4972 * @retval None
4973 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4974 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4975 {
4976 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4977 }
4978
4979 /**
4980 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4981 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4982 * @param TIMx Timer instance
4983 * @retval State of bit (1 or 0).
4984 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4985 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4986 {
4987 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4988 }
4989
4990 /**
4991 * @brief Clear the commutation interrupt flag (COMIF).
4992 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4993 * @param TIMx Timer instance
4994 * @retval None
4995 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4996 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4997 {
4998 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4999 }
5000
5001 /**
5002 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5003 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5004 * @param TIMx Timer instance
5005 * @retval State of bit (1 or 0).
5006 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5007 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5008 {
5009 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5010 }
5011
5012 /**
5013 * @brief Clear the trigger interrupt flag (TIF).
5014 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5015 * @param TIMx Timer instance
5016 * @retval None
5017 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5018 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5019 {
5020 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5021 }
5022
5023 /**
5024 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5025 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5026 * @param TIMx Timer instance
5027 * @retval State of bit (1 or 0).
5028 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5029 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5030 {
5031 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5032 }
5033
5034 /**
5035 * @brief Clear the break interrupt flag (BIF).
5036 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5037 * @param TIMx Timer instance
5038 * @retval None
5039 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5040 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5041 {
5042 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5043 }
5044
5045 /**
5046 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5047 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5048 * @param TIMx Timer instance
5049 * @retval State of bit (1 or 0).
5050 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5051 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5052 {
5053 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5054 }
5055
5056 /**
5057 * @brief Clear the break 2 interrupt flag (B2IF).
5058 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5059 * @param TIMx Timer instance
5060 * @retval None
5061 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5062 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5063 {
5064 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5065 }
5066
5067 /**
5068 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5069 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5070 * @param TIMx Timer instance
5071 * @retval State of bit (1 or 0).
5072 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5073 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5074 {
5075 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5076 }
5077
5078 /**
5079 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5080 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5081 * @param TIMx Timer instance
5082 * @retval None
5083 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5084 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5085 {
5086 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5087 }
5088
5089 /**
5090 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5091 * (Capture/Compare 1 interrupt is pending).
5092 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5093 * @param TIMx Timer instance
5094 * @retval State of bit (1 or 0).
5095 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5096 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5097 {
5098 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5099 }
5100
5101 /**
5102 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5103 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5104 * @param TIMx Timer instance
5105 * @retval None
5106 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5107 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5108 {
5109 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5110 }
5111
5112 /**
5113 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5114 * (Capture/Compare 2 over-capture interrupt is pending).
5115 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5116 * @param TIMx Timer instance
5117 * @retval State of bit (1 or 0).
5118 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5119 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5120 {
5121 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5122 }
5123
5124 /**
5125 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5126 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5127 * @param TIMx Timer instance
5128 * @retval None
5129 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5130 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5131 {
5132 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5133 }
5134
5135 /**
5136 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5137 * (Capture/Compare 3 over-capture interrupt is pending).
5138 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5139 * @param TIMx Timer instance
5140 * @retval State of bit (1 or 0).
5141 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5142 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5143 {
5144 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5145 }
5146
5147 /**
5148 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5149 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5150 * @param TIMx Timer instance
5151 * @retval None
5152 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5153 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5154 {
5155 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5156 }
5157
5158 /**
5159 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5160 * (Capture/Compare 4 over-capture interrupt is pending).
5161 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5162 * @param TIMx Timer instance
5163 * @retval State of bit (1 or 0).
5164 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5165 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5166 {
5167 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5168 }
5169
5170 /**
5171 * @brief Clear the system break interrupt flag (SBIF).
5172 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5173 * @param TIMx Timer instance
5174 * @retval None
5175 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5176 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5177 {
5178 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5179 }
5180
5181 /**
5182 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5183 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5184 * @param TIMx Timer instance
5185 * @retval State of bit (1 or 0).
5186 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5187 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5188 {
5189 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5190 }
5191
5192 /**
5193 * @brief Clear the transition error interrupt flag (TERRF).
5194 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5195 * a timer instance provides encoder error management.
5196 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5197 * @param TIMx Timer instance
5198 * @retval None
5199 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5200 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5201 {
5202 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5203 }
5204
5205 /**
5206 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5207 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5208 * a timer instance provides encoder error management.
5209 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5210 * @param TIMx Timer instance
5211 * @retval State of bit (1 or 0).
5212 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5213 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5214 {
5215 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5216 }
5217
5218 /**
5219 * @brief Clear the index error interrupt flag (IERRF).
5220 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5221 * a timer instance provides encoder error management.
5222 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5223 * @param TIMx Timer instance
5224 * @retval None
5225 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5226 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5227 {
5228 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5229 }
5230
5231 /**
5232 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5233 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5234 * a timer instance provides encoder error management.
5235 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5236 * @param TIMx Timer instance
5237 * @retval State of bit (1 or 0).
5238 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5239 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5240 {
5241 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5242 }
5243
5244 /**
5245 * @brief Clear the direction change interrupt flag (DIRF).
5246 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5247 * a timer instance provides encoder interrupt management.
5248 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5249 * @param TIMx Timer instance
5250 * @retval None
5251 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5252 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5253 {
5254 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5255 }
5256
5257 /**
5258 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5259 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5260 * a timer instance provides encoder interrupt management.
5261 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5262 * @param TIMx Timer instance
5263 * @retval State of bit (1 or 0).
5264 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5265 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5266 {
5267 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5268 }
5269
5270 /**
5271 * @brief Clear the index interrupt flag (IDXF).
5272 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5273 * a timer instance provides encoder interrupt management.
5274 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5275 * @param TIMx Timer instance
5276 * @retval None
5277 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5278 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5279 {
5280 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5281 }
5282
5283 /**
5284 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5285 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5286 * a timer instance provides encoder interrupt management.
5287 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5288 * @param TIMx Timer instance
5289 * @retval State of bit (1 or 0).
5290 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5291 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5292 {
5293 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5294 }
5295 /**
5296 * @}
5297 */
5298
5299 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5300 * @{
5301 */
5302 /**
5303 * @brief Enable update interrupt (UIE).
5304 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5305 * @param TIMx Timer instance
5306 * @retval None
5307 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5308 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5309 {
5310 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5311 }
5312
5313 /**
5314 * @brief Disable update interrupt (UIE).
5315 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5316 * @param TIMx Timer instance
5317 * @retval None
5318 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5319 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5320 {
5321 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5322 }
5323
5324 /**
5325 * @brief Indicates whether the update interrupt (UIE) is enabled.
5326 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5327 * @param TIMx Timer instance
5328 * @retval State of bit (1 or 0).
5329 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5330 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5331 {
5332 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5333 }
5334
5335 /**
5336 * @brief Enable capture/compare 1 interrupt (CC1IE).
5337 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5338 * @param TIMx Timer instance
5339 * @retval None
5340 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5341 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5342 {
5343 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5344 }
5345
5346 /**
5347 * @brief Disable capture/compare 1 interrupt (CC1IE).
5348 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5349 * @param TIMx Timer instance
5350 * @retval None
5351 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5352 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5353 {
5354 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5355 }
5356
5357 /**
5358 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5359 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5360 * @param TIMx Timer instance
5361 * @retval State of bit (1 or 0).
5362 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5363 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5364 {
5365 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5366 }
5367
5368 /**
5369 * @brief Enable capture/compare 2 interrupt (CC2IE).
5370 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5371 * @param TIMx Timer instance
5372 * @retval None
5373 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5374 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5375 {
5376 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5377 }
5378
5379 /**
5380 * @brief Disable capture/compare 2 interrupt (CC2IE).
5381 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5382 * @param TIMx Timer instance
5383 * @retval None
5384 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5385 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5386 {
5387 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5388 }
5389
5390 /**
5391 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5392 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5393 * @param TIMx Timer instance
5394 * @retval State of bit (1 or 0).
5395 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5396 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5397 {
5398 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5399 }
5400
5401 /**
5402 * @brief Enable capture/compare 3 interrupt (CC3IE).
5403 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5404 * @param TIMx Timer instance
5405 * @retval None
5406 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5407 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5408 {
5409 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5410 }
5411
5412 /**
5413 * @brief Disable capture/compare 3 interrupt (CC3IE).
5414 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5415 * @param TIMx Timer instance
5416 * @retval None
5417 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5418 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5419 {
5420 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5421 }
5422
5423 /**
5424 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5425 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5426 * @param TIMx Timer instance
5427 * @retval State of bit (1 or 0).
5428 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5429 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5430 {
5431 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5432 }
5433
5434 /**
5435 * @brief Enable capture/compare 4 interrupt (CC4IE).
5436 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5437 * @param TIMx Timer instance
5438 * @retval None
5439 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5440 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5441 {
5442 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5443 }
5444
5445 /**
5446 * @brief Disable capture/compare 4 interrupt (CC4IE).
5447 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5448 * @param TIMx Timer instance
5449 * @retval None
5450 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5451 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5452 {
5453 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5454 }
5455
5456 /**
5457 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5458 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5459 * @param TIMx Timer instance
5460 * @retval State of bit (1 or 0).
5461 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5462 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5463 {
5464 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5465 }
5466
5467 /**
5468 * @brief Enable commutation interrupt (COMIE).
5469 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5470 * @param TIMx Timer instance
5471 * @retval None
5472 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5473 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5474 {
5475 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5476 }
5477
5478 /**
5479 * @brief Disable commutation interrupt (COMIE).
5480 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5481 * @param TIMx Timer instance
5482 * @retval None
5483 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5484 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5485 {
5486 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5487 }
5488
5489 /**
5490 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5491 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5492 * @param TIMx Timer instance
5493 * @retval State of bit (1 or 0).
5494 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5495 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5496 {
5497 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5498 }
5499
5500 /**
5501 * @brief Enable trigger interrupt (TIE).
5502 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5503 * @param TIMx Timer instance
5504 * @retval None
5505 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5506 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5507 {
5508 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5509 }
5510
5511 /**
5512 * @brief Disable trigger interrupt (TIE).
5513 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5514 * @param TIMx Timer instance
5515 * @retval None
5516 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5517 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5518 {
5519 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5520 }
5521
5522 /**
5523 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5524 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5525 * @param TIMx Timer instance
5526 * @retval State of bit (1 or 0).
5527 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5528 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5529 {
5530 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5531 }
5532
5533 /**
5534 * @brief Enable break interrupt (BIE).
5535 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5536 * @param TIMx Timer instance
5537 * @retval None
5538 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5539 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5540 {
5541 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5542 }
5543
5544 /**
5545 * @brief Disable break interrupt (BIE).
5546 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5547 * @param TIMx Timer instance
5548 * @retval None
5549 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5550 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5551 {
5552 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5553 }
5554
5555 /**
5556 * @brief Indicates whether the break interrupt (BIE) is enabled.
5557 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5558 * @param TIMx Timer instance
5559 * @retval State of bit (1 or 0).
5560 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5561 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5562 {
5563 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5564 }
5565
5566 /**
5567 * @brief Enable transition error interrupt (TERRIE).
5568 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5569 * a timer instance provides encoder error management.
5570 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5571 * @param TIMx Timer instance
5572 * @retval None
5573 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5574 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5575 {
5576 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5577 }
5578
5579 /**
5580 * @brief Disable transition error interrupt (TERRIE).
5581 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5582 * a timer instance provides encoder error management.
5583 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5584 * @param TIMx Timer instance
5585 * @retval None
5586 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5587 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5588 {
5589 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5590 }
5591
5592 /**
5593 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5594 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5595 * a timer instance provides encoder error management.
5596 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5597 * @param TIMx Timer instance
5598 * @retval State of bit (1 or 0).
5599 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5600 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5601 {
5602 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5603 }
5604
5605 /**
5606 * @brief Enable index error interrupt (IERRIE).
5607 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5608 * a timer instance provides encoder error management.
5609 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5610 * @param TIMx Timer instance
5611 * @retval None
5612 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5613 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5614 {
5615 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5616 }
5617
5618 /**
5619 * @brief Disable index error interrupt (IERRIE).
5620 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5621 * a timer instance provides encoder error management.
5622 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
5623 * @param TIMx Timer instance
5624 * @retval None
5625 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)5626 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
5627 {
5628 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5629 }
5630
5631 /**
5632 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
5633 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5634 * a timer instance provides encoder error management.
5635 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
5636 * @param TIMx Timer instance
5637 * @retval State of bit (1 or 0).
5638 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)5639 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
5640 {
5641 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
5642 }
5643
5644 /**
5645 * @brief Enable direction change interrupt (DIRIE).
5646 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5647 * a timer instance provides encoder interrupt management.
5648 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
5649 * @param TIMx Timer instance
5650 * @retval None
5651 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)5652 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
5653 {
5654 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5655 }
5656
5657 /**
5658 * @brief Disable direction change interrupt (DIRIE).
5659 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5660 * a timer instance provides encoder interrupt management.
5661 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
5662 * @param TIMx Timer instance
5663 * @retval None
5664 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)5665 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
5666 {
5667 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5668 }
5669
5670 /**
5671 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
5672 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5673 * a timer instance provides encoder interrupt management.
5674 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
5675 * @param TIMx Timer instance
5676 * @retval State of bit (1 or 0).
5677 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)5678 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
5679 {
5680 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
5681 }
5682
5683 /**
5684 * @brief Enable index interrupt (IDXIE).
5685 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5686 * a timer instance provides encoder interrupt management.
5687 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
5688 * @param TIMx Timer instance
5689 * @retval None
5690 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)5691 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
5692 {
5693 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5694 }
5695
5696 /**
5697 * @brief Disable index interrupt (IDXIE).
5698 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5699 * a timer instance provides encoder interrupt management.
5700 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
5701 * @param TIMx Timer instance
5702 * @retval None
5703 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)5704 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
5705 {
5706 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5707 }
5708
5709 /**
5710 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
5711 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5712 * a timer instance provides encoder interrupt management.
5713 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
5714 * @param TIMx Timer instance
5715 * @retval State of bit (1 or 0).
5716 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)5717 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
5718 {
5719 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
5720 }
5721
5722 /**
5723 * @}
5724 */
5725
5726 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
5727 * @{
5728 */
5729 /**
5730 * @brief Enable update DMA request (UDE).
5731 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
5732 * @param TIMx Timer instance
5733 * @retval None
5734 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)5735 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5736 {
5737 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
5738 }
5739
5740 /**
5741 * @brief Disable update DMA request (UDE).
5742 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
5743 * @param TIMx Timer instance
5744 * @retval None
5745 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)5746 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5747 {
5748 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
5749 }
5750
5751 /**
5752 * @brief Indicates whether the update DMA request (UDE) is enabled.
5753 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
5754 * @param TIMx Timer instance
5755 * @retval State of bit (1 or 0).
5756 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)5757 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
5758 {
5759 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
5760 }
5761
5762 /**
5763 * @brief Enable capture/compare 1 DMA request (CC1DE).
5764 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
5765 * @param TIMx Timer instance
5766 * @retval None
5767 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)5768 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
5769 {
5770 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5771 }
5772
5773 /**
5774 * @brief Disable capture/compare 1 DMA request (CC1DE).
5775 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
5776 * @param TIMx Timer instance
5777 * @retval None
5778 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)5779 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
5780 {
5781 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5782 }
5783
5784 /**
5785 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
5786 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
5787 * @param TIMx Timer instance
5788 * @retval State of bit (1 or 0).
5789 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)5790 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
5791 {
5792 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
5793 }
5794
5795 /**
5796 * @brief Enable capture/compare 2 DMA request (CC2DE).
5797 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
5798 * @param TIMx Timer instance
5799 * @retval None
5800 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)5801 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
5802 {
5803 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5804 }
5805
5806 /**
5807 * @brief Disable capture/compare 2 DMA request (CC2DE).
5808 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
5809 * @param TIMx Timer instance
5810 * @retval None
5811 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)5812 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
5813 {
5814 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5815 }
5816
5817 /**
5818 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
5819 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
5820 * @param TIMx Timer instance
5821 * @retval State of bit (1 or 0).
5822 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)5823 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
5824 {
5825 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
5826 }
5827
5828 /**
5829 * @brief Enable capture/compare 3 DMA request (CC3DE).
5830 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
5831 * @param TIMx Timer instance
5832 * @retval None
5833 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)5834 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
5835 {
5836 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5837 }
5838
5839 /**
5840 * @brief Disable capture/compare 3 DMA request (CC3DE).
5841 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
5842 * @param TIMx Timer instance
5843 * @retval None
5844 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)5845 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
5846 {
5847 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5848 }
5849
5850 /**
5851 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
5852 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
5853 * @param TIMx Timer instance
5854 * @retval State of bit (1 or 0).
5855 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)5856 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
5857 {
5858 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
5859 }
5860
5861 /**
5862 * @brief Enable capture/compare 4 DMA request (CC4DE).
5863 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
5864 * @param TIMx Timer instance
5865 * @retval None
5866 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)5867 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
5868 {
5869 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5870 }
5871
5872 /**
5873 * @brief Disable capture/compare 4 DMA request (CC4DE).
5874 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
5875 * @param TIMx Timer instance
5876 * @retval None
5877 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)5878 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
5879 {
5880 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5881 }
5882
5883 /**
5884 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
5885 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
5886 * @param TIMx Timer instance
5887 * @retval State of bit (1 or 0).
5888 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)5889 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
5890 {
5891 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
5892 }
5893
5894 /**
5895 * @brief Enable commutation DMA request (COMDE).
5896 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
5897 * @param TIMx Timer instance
5898 * @retval None
5899 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)5900 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
5901 {
5902 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
5903 }
5904
5905 /**
5906 * @brief Disable commutation DMA request (COMDE).
5907 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
5908 * @param TIMx Timer instance
5909 * @retval None
5910 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)5911 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
5912 {
5913 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
5914 }
5915
5916 /**
5917 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
5918 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
5919 * @param TIMx Timer instance
5920 * @retval State of bit (1 or 0).
5921 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)5922 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
5923 {
5924 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
5925 }
5926
5927 /**
5928 * @brief Enable trigger interrupt (TDE).
5929 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
5930 * @param TIMx Timer instance
5931 * @retval None
5932 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)5933 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
5934 {
5935 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
5936 }
5937
5938 /**
5939 * @brief Disable trigger interrupt (TDE).
5940 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
5941 * @param TIMx Timer instance
5942 * @retval None
5943 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)5944 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
5945 {
5946 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
5947 }
5948
5949 /**
5950 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
5951 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
5952 * @param TIMx Timer instance
5953 * @retval State of bit (1 or 0).
5954 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)5955 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
5956 {
5957 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
5958 }
5959
5960 /**
5961 * @}
5962 */
5963
5964 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
5965 * @{
5966 */
5967 /**
5968 * @brief Generate an update event.
5969 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
5970 * @param TIMx Timer instance
5971 * @retval None
5972 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)5973 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
5974 {
5975 SET_BIT(TIMx->EGR, TIM_EGR_UG);
5976 }
5977
5978 /**
5979 * @brief Generate Capture/Compare 1 event.
5980 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
5981 * @param TIMx Timer instance
5982 * @retval None
5983 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)5984 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
5985 {
5986 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
5987 }
5988
5989 /**
5990 * @brief Generate Capture/Compare 2 event.
5991 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
5992 * @param TIMx Timer instance
5993 * @retval None
5994 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)5995 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
5996 {
5997 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
5998 }
5999
6000 /**
6001 * @brief Generate Capture/Compare 3 event.
6002 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6003 * @param TIMx Timer instance
6004 * @retval None
6005 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6006 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6007 {
6008 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6009 }
6010
6011 /**
6012 * @brief Generate Capture/Compare 4 event.
6013 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6014 * @param TIMx Timer instance
6015 * @retval None
6016 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6017 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6018 {
6019 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6020 }
6021
6022 /**
6023 * @brief Generate commutation event.
6024 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6025 * @param TIMx Timer instance
6026 * @retval None
6027 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6028 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6029 {
6030 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6031 }
6032
6033 /**
6034 * @brief Generate trigger event.
6035 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6036 * @param TIMx Timer instance
6037 * @retval None
6038 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6039 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6040 {
6041 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6042 }
6043
6044 /**
6045 * @brief Generate break event.
6046 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6047 * @param TIMx Timer instance
6048 * @retval None
6049 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6050 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6051 {
6052 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6053 }
6054
6055 /**
6056 * @brief Generate break 2 event.
6057 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6058 * @param TIMx Timer instance
6059 * @retval None
6060 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6061 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6062 {
6063 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6064 }
6065
6066 /**
6067 * @}
6068 */
6069
6070 #if defined(USE_FULL_LL_DRIVER)
6071 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6072 * @{
6073 */
6074
6075 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6076 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6077 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6078 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6079 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6080 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6081 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6082 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6083 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6084 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6085 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6086 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6087 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6088 /**
6089 * @}
6090 */
6091 #endif /* USE_FULL_LL_DRIVER */
6092
6093 /**
6094 * @}
6095 */
6096
6097 /**
6098 * @}
6099 */
6100
6101 #endif /* TIM1 || TIM2 || TIM3 || TIM16 || TIM17 */
6102
6103 /**
6104 * @}
6105 */
6106
6107 #ifdef __cplusplus
6108 }
6109 #endif
6110
6111 #endif /* __STM32WBAxx_LL_TIM_H */
6112
