1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_SPI_H
21 #define STM32WBAxx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI3)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
46 * @{
47 */
48 #if defined(IS_SPI_GRP1_INSTANCE)
49 #define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__)
50 #endif /* SPI_TRIG_GRP1 */
51 #define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__)
52 /**
53 * @}
54 */
55
56 /* Exported types ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup SPI_LL_Exported_Types SPI Exported Types
59 * @{
60 */
61
62 /**
63 * @brief SPI Init structures definition
64 */
65 typedef struct
66 {
67 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
68 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
69
70 This feature can be modified afterwards using unitary function
71 @ref LL_SPI_SetTransferDirection().*/
72
73 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
74 This parameter can be a value of @ref SPI_LL_EC_MODE.
75
76 This feature can be modified afterwards using unitary function
77 @ref LL_SPI_SetMode().*/
78
79 uint32_t DataWidth; /*!< Specifies the SPI data width.
80 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
81
82 This feature can be modified afterwards using unitary function
83 @ref LL_SPI_SetDataWidth().*/
84
85 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
86 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
87
88 This feature can be modified afterwards using unitary function
89 @ref LL_SPI_SetClockPolarity().*/
90
91 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
92 This parameter can be a value of @ref SPI_LL_EC_PHASE.
93
94 This feature can be modified afterwards using unitary function
95 @ref LL_SPI_SetClockPhase().*/
96
97 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
98 or by software using the SSI bit.
99
100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
101
102 This feature can be modified afterwards using unitary function
103 @ref LL_SPI_SetNSSMode().*/
104
105 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
106 the transmit and receive SCK clock.
107 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
108 @note The communication clock is derived from the master clock.
109 The slave clock does not need to be set.
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_SPI_SetBaudRatePrescaler().*/
113
114 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
115 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
116
117 This feature can be modified afterwards using unitary function
118 @ref LL_SPI_SetTransferBitOrder().*/
119
120 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
121 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
122
123 This feature can be modified afterwards using unitary functions
124 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
125
126 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
127 This parameter must be a number between Min_Data = 0x00
128 and Max_Data = 0xFFFFFFFF.
129
130 This feature can be modified afterwards using unitary function
131 @ref LL_SPI_SetCRCPolynomial().*/
132
133 } LL_SPI_InitTypeDef;
134
135 /**
136 * @}
137 */
138 #endif /*USE_FULL_LL_DRIVER*/
139
140 /* Exported types ------------------------------------------------------------*/
141
142 /* Exported constants --------------------------------------------------------*/
143 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
144 * @{
145 */
146
147 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_SPI_ReadReg function
149 * @{
150 */
151 #define LL_SPI_SR_RXP (SPI_SR_RXP)
152 #define LL_SPI_SR_TXP (SPI_SR_TXP)
153 #define LL_SPI_SR_DXP (SPI_SR_DXP)
154 #define LL_SPI_SR_EOT (SPI_SR_EOT)
155 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
156 #define LL_SPI_SR_UDR (SPI_SR_UDR)
157 #define LL_SPI_SR_CRCE (SPI_SR_CRCE)
158 #define LL_SPI_SR_MODF (SPI_SR_MODF)
159 #define LL_SPI_SR_OVR (SPI_SR_OVR)
160 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
161 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
162 #define LL_SPI_SR_TXC (SPI_SR_TXC)
163 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
164 /**
165 * @}
166 */
167
168 /** @defgroup SPI_LL_EC_IT IT Defines
169 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
170 * @{
171 */
172 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
173 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
174 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
175 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
176 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
177 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
178 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
179 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
180 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
181 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
182 /**
183 * @}
184 */
185
186 /** @defgroup SPI_LL_EC_MODE Mode
187 * @{
188 */
189 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
190 #define LL_SPI_MODE_SLAVE (0x00000000UL)
191 /**
192 * @}
193 */
194
195 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
196 * @{
197 */
198 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
199 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
200 /**
201 * @}
202 */
203
204 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
205 * @{
206 */
207 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
208 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
209 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
210 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
211 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
212 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
213 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
214 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
215 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
216 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
217 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
218 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
219 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
220 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
221 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
222 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
223 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
224 /**
225 * @}
226 */
227
228 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
229 * @{
230 */
231 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
232 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
233 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
234 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
235 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
236 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
237 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
238 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
239 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
240 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
241 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
242 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
243 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
244 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
245 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
246 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
247 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
248 /**
249 * @}
250 */
251
252 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
253 * @{
254 */
255 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
256 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
257 /**
258 * @}
259 */
260
261 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
262 * @{
263 */
264 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
265 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
266 /**
267 * @}
268 */
269
270 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
271 * @{
272 */
273 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
274 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)
275 /**
276 * @}
277 */
278
279 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
280 * @{
281 */
282 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
283 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
284 /**
285 * @}
286 */
287
288 /** @defgroup SPI_LL_EC_PHASE Phase
289 * @{
290 */
291 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
292 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
293 /**
294 * @}
295 */
296
297 /** @defgroup SPI_LL_EC_POLARITY Polarity
298 * @{
299 */
300 #define LL_SPI_POLARITY_LOW (0x00000000UL)
301 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
302 /**
303 * @}
304 */
305
306 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
307 * @{
308 */
309 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
310 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
311 /**
312 * @}
313 */
314
315 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
316 * @{
317 */
318 #define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
319 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
320 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
321 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
322 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
323 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
324 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
325 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
326 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
327 /**
328 * @}
329 */
330
331 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
332 * @{
333 */
334 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
335 #define LL_SPI_MSB_FIRST (0x00000000UL)
336 /**
337 * @}
338 */
339
340 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
341 * @{
342 */
343 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
344 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
345 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
346 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
347 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
348 /**
349 * @}
350 */
351
352 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
353 * @{
354 */
355 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
356 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
357 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
358 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
359 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
360 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
361 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
362 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
363 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
364 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
365 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
366 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
367 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
368 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
369 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
370 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
371 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
372 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
373 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
374 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
375 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
376 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
377 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
378 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
379 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
380 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
381 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
382 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
383 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
384 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
385 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
386 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
387 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
388 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
389 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
390 /**
391 * @}
392 */
393
394 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
395 * @{
396 */
397 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
398 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
399 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
400 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
401 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
402 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
403 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
404 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
405 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
406 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
407 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
408 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
409 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
410 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
411 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
412 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
413 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
414 /**
415 * @}
416 */
417
418 #if defined(USE_FULL_LL_DRIVER)
419
420 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
421 * @{
422 */
423 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
424 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
425 /**
426 * @}
427 */
428 #endif /* USE_FULL_LL_DRIVER */
429
430 /** @defgroup SPI_LL_EC_CRC CRC
431 * @{
432 */
433 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
434 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
435 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
436 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
437 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
438 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
439 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
440 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
441 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
442 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
443 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
444 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
445 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
446 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
447 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
448 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
449 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
450 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
451 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
452 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
453 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
454 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
455 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
456 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
457 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
458 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
459 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
460 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
461 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
462 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
463 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
464 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
465 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
466 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
467 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
468 /**
469 * @}
470 */
471
472 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
473 * @{
474 */
475 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
476 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
477 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
478 /**
479 * @}
480 */
481
482 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
483 * @{
484 */
485 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
486 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
487 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
488 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
489 /**
490 * @}
491 */
492
493 /** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
494 * @brief SPI Autonomous Trigger selection
495 * @{
496 */
497 #if defined(SPI1)
498 #define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 */
499 #endif /* SPI1 */
500 #define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */
501
502 #if defined(LL_SPI_TRIG_GRP1)
503 /*!< HW Trigger signal is GPDMA_CH0_TRG */
504 #define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U))
505 /*!< HW Trigger signal is GPDMA_CH1_TRG */
506 #define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
507 /*!< HW Trigger signal is GPDMA_CH2_TRG */
508 #define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
509 /*!< HW Trigger signal is GPDMA_CH3_TRG */
510 #define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
511 /*!< HW Trigger signal is EXTI4_TRG */
512 #define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
513 /*!< HW Trigger signal is EXTI9_TRG */
514 #define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
515 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
516 #define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
517 #if defined (LPTIM2)
518 /*!< HW Trigger signal is LPTIM2_CH1_TRG */
519 #define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
520 #endif /* LPTIM2 */
521 #if defined (COMP1)
522 /*!< HW Trigger signal is COMP1_TRG */
523 #define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
524 #endif /* COMP1 */
525 #if defined (COMP2)
526 /*!< HW Trigger signal is COMP2_TRG */
527 #define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
528 #endif /* COMP2 */
529 /*!< HW Trigger signal is RTC_ALRA_TRG */
530 #define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
531 /*!< HW Trigger signal is RTC_WUT_TRG */
532 #define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
533 #endif /* LL_SPI_TRIG_GRP1 */
534
535 /*!< HW Trigger signal is LPDMA_CH0_TRG */
536 #define LL_SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U))
537 /*!< HW Trigger signal is LPDMA_CH1_TRG */
538 #define LL_SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
539 /*!< HW Trigger signal is LPDMA_CH2_TRG */
540 #define LL_SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
541 /*!< HW Trigger signal is LPDMA_CH3_TRG */
542 #define LL_SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
543 /*!< HW Trigger signal is EXTI4_TRG */
544 #define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
545 /*!< HW Trigger signal is EXTI8_TRG */
546 #define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
547 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
548 #define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
549 #if defined (COMP1)
550 /*!< HW Trigger signal is COMP1_TRG */
551 #define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
552 #endif /* COMP1 */
553 /*!< HW Trigger signal is RTC_ALRA_TRG */
554 #define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
555 /*!< HW Trigger signal is RTC_WUT_TRG */
556 #define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
557 /**
558 * @}
559 */
560
561 /** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
562 * @brief SPI Autonomous Trigger Polarity
563 * @{
564 */
565 #define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */
566 #define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */
567 /**
568 * @}
569 */
570
571 /**
572 * @}
573 */
574
575 /* Exported macro ------------------------------------------------------------*/
576 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
577 * @{
578 */
579
580 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
581 * @{
582 */
583
584 /**
585 * @brief Write a value in SPI register
586 * @param __INSTANCE__ SPI Instance
587 * @param __REG__ Register to be written
588 * @param __VALUE__ Value to be written in the register
589 * @retval None
590 */
591 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
592
593 /**
594 * @brief Read a value in SPI register
595 * @param __INSTANCE__ SPI Instance
596 * @param __REG__ Register to be read
597 * @retval Register value
598 */
599 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
600 /**
601 * @}
602 */
603
604 /**
605 * @}
606 */
607
608
609 /* Exported functions --------------------------------------------------------*/
610
611 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
612 * @{
613 */
614
615 /** @defgroup SPI_LL_EF_Configuration Configuration
616 * @{
617 */
618
619 /**
620 * @brief Enable SPI peripheral
621 * @rmtoll CR1 SPE LL_SPI_Enable
622 * @param SPIx SPI Instance
623 * @retval None
624 */
LL_SPI_Enable(SPI_TypeDef * SPIx)625 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
626 {
627 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
628 }
629
630 /**
631 * @brief Disable SPI peripheral
632 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
633 * @rmtoll CR1 SPE LL_SPI_Disable
634 * @param SPIx SPI Instance
635 * @retval None
636 */
LL_SPI_Disable(SPI_TypeDef * SPIx)637 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
638 {
639 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
640 }
641
642 /**
643 * @brief Check if SPI peripheral is enabled
644 * @rmtoll CR1 SPE LL_SPI_IsEnabled
645 * @param SPIx SPI Instance
646 * @retval State of bit (1 or 0)
647 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)648 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
649 {
650 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
651 }
652
653 /**
654 * @brief Swap the MOSI and MISO pin
655 * @note This configuration can not be changed when SPI is enabled.
656 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
657 * @param SPIx SPI Instance
658 * @retval None
659 */
LL_SPI_EnableIOSwap(SPI_TypeDef * SPIx)660 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
661 {
662 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
663 }
664
665 /**
666 * @brief Restore default function for MOSI and MISO pin
667 * @note This configuration can not be changed when SPI is enabled.
668 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
669 * @param SPIx SPI Instance
670 * @retval None
671 */
LL_SPI_DisableIOSwap(SPI_TypeDef * SPIx)672 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
673 {
674 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
675 }
676
677 /**
678 * @brief Check if MOSI and MISO pin are swapped
679 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
680 * @param SPIx SPI Instance
681 * @retval State of bit (1 or 0)
682 */
LL_SPI_IsEnabledIOSwap(const SPI_TypeDef * SPIx)683 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
684 {
685 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
686 }
687
688 /**
689 * @brief Enable GPIO control
690 * @note This configuration can not be changed when SPI is enabled.
691 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
692 * @param SPIx SPI Instance
693 * @retval None
694 */
LL_SPI_EnableGPIOControl(SPI_TypeDef * SPIx)695 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
696 {
697 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
698 }
699
700 /**
701 * @brief Disable GPIO control
702 * @note This configuration can not be changed when SPI is enabled.
703 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
704 * @param SPIx SPI Instance
705 * @retval None
706 */
LL_SPI_DisableGPIOControl(SPI_TypeDef * SPIx)707 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
708 {
709 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
710 }
711
712 /**
713 * @brief Check if GPIO control is active
714 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
715 * @param SPIx SPI Instance
716 * @retval State of bit (1 or 0)
717 */
LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef * SPIx)718 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
719 {
720 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
721 }
722
723 /**
724 * @brief Set SPI Mode to Master or Slave
725 * @note This configuration can not be changed when SPI is enabled.
726 * @rmtoll CFG2 MASTER LL_SPI_SetMode
727 * @param SPIx SPI Instance
728 * @param Mode This parameter can be one of the following values:
729 * @arg @ref LL_SPI_MODE_MASTER
730 * @arg @ref LL_SPI_MODE_SLAVE
731 * @retval None
732 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)733 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
734 {
735 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
736 }
737
738 /**
739 * @brief Get SPI Mode (Master or Slave)
740 * @rmtoll CFG2 MASTER LL_SPI_GetMode
741 * @param SPIx SPI Instance
742 * @retval Returned value can be one of the following values:
743 * @arg @ref LL_SPI_MODE_MASTER
744 * @arg @ref LL_SPI_MODE_SLAVE
745 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)746 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
747 {
748 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
749 }
750
751 /**
752 * @brief Configure the Idleness applied by master between active edge of SS and first send data
753 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
754 * @param SPIx SPI Instance
755 * @param MasterSSIdleness This parameter can be one of the following values:
756 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
757 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
758 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
759 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
760 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
761 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
762 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
763 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
764 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
765 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
766 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
767 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
768 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
769 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
770 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
771 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
772 * @retval None
773 */
LL_SPI_SetMasterSSIdleness(SPI_TypeDef * SPIx,uint32_t MasterSSIdleness)774 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
775 {
776 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
777 }
778
779 /**
780 * @brief Get the configured Idleness applied by master
781 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
782 * @param SPIx SPI Instance
783 * @retval Returned value can be one of the following values:
784 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
785 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
786 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
787 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
788 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
789 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
790 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
791 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
792 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
793 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
794 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
795 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
796 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
797 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
798 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
799 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
800 */
LL_SPI_GetMasterSSIdleness(const SPI_TypeDef * SPIx)801 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
802 {
803 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
804 }
805
806 /**
807 * @brief Configure the idleness applied by master between data frame
808 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
809 * @param SPIx SPI Instance
810 * @param MasterInterDataIdleness This parameter can be one of the following values:
811 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
812 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
813 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
814 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
815 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
816 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
817 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
818 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
819 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
820 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
821 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
822 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
823 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
824 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
825 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
826 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
827 * @retval None
828 */
LL_SPI_SetInterDataIdleness(SPI_TypeDef * SPIx,uint32_t MasterInterDataIdleness)829 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
830 {
831 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
832 }
833
834 /**
835 * @brief Get the configured inter data idleness
836 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
837 * @param SPIx SPI Instance
838 * @retval Returned value can be one of the following values:
839 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
840 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
841 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
842 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
843 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
844 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
845 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
846 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
847 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
848 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
849 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
850 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
851 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
852 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
853 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
854 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
855 */
LL_SPI_GetInterDataIdleness(const SPI_TypeDef * SPIx)856 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
857 {
858 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
859 }
860
861 /**
862 * @brief Set transfer size
863 * @note Count is the number of frame to be transferred
864 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
865 * @param SPIx SPI Instance
866 * @param Count 0..0xFFFF
867 * @retval None
868 */
LL_SPI_SetTransferSize(SPI_TypeDef * SPIx,uint32_t Count)869 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
870 {
871 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
872 }
873
874 /**
875 * @brief Get transfer size
876 * @note Count is the number of frame to be transferred
877 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
878 * @param SPIx SPI Instance
879 * @retval 0..0xFFFF
880 */
LL_SPI_GetTransferSize(const SPI_TypeDef * SPIx)881 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
882 {
883 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
884 }
885
886 /**
887 * @brief Lock the AF configuration of associated IOs
888 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
889 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
890 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
891 * @param SPIx SPI Instance
892 * @retval None
893 */
LL_SPI_EnableIOLock(SPI_TypeDef * SPIx)894 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
895 {
896 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
897 }
898
899 /**
900 * @brief Check if the AF configuration is locked.
901 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
902 * @param SPIx SPI Instance
903 * @retval State of bit (1 or 0)
904 */
LL_SPI_IsEnabledIOLock(const SPI_TypeDef * SPIx)905 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
906 {
907 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
908 }
909
910 /**
911 * @brief Set Tx CRC Initialization Pattern
912 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
913 * @param SPIx SPI Instance
914 * @param TXCRCInitAll This parameter can be one of the following values:
915 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
916 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
917 * @retval None
918 */
LL_SPI_SetTxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t TXCRCInitAll)919 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
920 {
921 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
922 }
923
924 /**
925 * @brief Get Tx CRC Initialization Pattern
926 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
927 * @param SPIx SPI Instance
928 * @retval Returned value can be one of the following values:
929 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
930 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
931 */
LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef * SPIx)932 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
933 {
934 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
935 }
936
937 /**
938 * @brief Set Rx CRC Initialization Pattern
939 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
940 * @param SPIx SPI Instance
941 * @param RXCRCInitAll This parameter can be one of the following values:
942 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
943 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
944 * @retval None
945 */
LL_SPI_SetRxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t RXCRCInitAll)946 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
947 {
948 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
949 }
950
951 /**
952 * @brief Get Rx CRC Initialization Pattern
953 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
954 * @param SPIx SPI Instance
955 * @retval Returned value can be one of the following values:
956 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
957 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
958 */
LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef * SPIx)959 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
960 {
961 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
962 }
963
964 /**
965 * @brief Set internal SS input level ignoring what comes from PIN.
966 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
967 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
968 * @param SPIx SPI Instance
969 * @param SSLevel This parameter can be one of the following values:
970 * @arg @ref LL_SPI_SS_LEVEL_HIGH
971 * @arg @ref LL_SPI_SS_LEVEL_LOW
972 * @retval None
973 */
LL_SPI_SetInternalSSLevel(SPI_TypeDef * SPIx,uint32_t SSLevel)974 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
975 {
976 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
977 }
978
979 /**
980 * @brief Get internal SS input level
981 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
982 * @param SPIx SPI Instance
983 * @retval Returned value can be one of the following values:
984 * @arg @ref LL_SPI_SS_LEVEL_HIGH
985 * @arg @ref LL_SPI_SS_LEVEL_LOW
986 */
LL_SPI_GetInternalSSLevel(const SPI_TypeDef * SPIx)987 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
988 {
989 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
990 }
991
992 /**
993 * @brief Enable CRC computation on 33/17 bits
994 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
995 * @param SPIx SPI Instance
996 * @retval None
997 */
LL_SPI_EnableFullSizeCRC(SPI_TypeDef * SPIx)998 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
999 {
1000 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
1001 }
1002
1003 /**
1004 * @brief Disable CRC computation on 33/17 bits
1005 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
1006 * @param SPIx SPI Instance
1007 * @retval None
1008 */
LL_SPI_DisableFullSizeCRC(SPI_TypeDef * SPIx)1009 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
1010 {
1011 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
1012 }
1013
1014 /**
1015 * @brief Check if Enable CRC computation on 33/17 bits is enabled
1016 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
1017 * @param SPIx SPI Instance
1018 * @retval State of bit (1 or 0)
1019 */
LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef * SPIx)1020 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
1021 {
1022 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
1023 }
1024
1025 /**
1026 * @brief Suspend an ongoing transfer for Master configuration
1027 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
1028 * @param SPIx SPI Instance
1029 * @retval None
1030 */
LL_SPI_SuspendMasterTransfer(SPI_TypeDef * SPIx)1031 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
1032 {
1033 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
1034 }
1035
1036 /**
1037 * @brief Start effective transfer on wire for Master configuration
1038 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
1039 * @param SPIx SPI Instance
1040 * @retval None
1041 */
LL_SPI_StartMasterTransfer(SPI_TypeDef * SPIx)1042 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
1043 {
1044 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
1045 }
1046
1047 /**
1048 * @brief Check if there is an unfinished master transfer
1049 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
1050 * @param SPIx SPI Instance
1051 * @retval State of bit (1 or 0)
1052 */
LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef * SPIx)1053 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
1054 {
1055 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
1056 }
1057
1058 /**
1059 * @brief Enable Master Rx auto suspend in case of overrun
1060 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
1061 * @param SPIx SPI Instance
1062 * @retval None
1063 */
LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1064 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1065 {
1066 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
1067 }
1068
1069 /**
1070 * @brief Disable Master Rx auto suspend in case of overrun
1071 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
1072 * @param SPIx SPI Instance
1073 * @retval None
1074 */
LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1075 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1076 {
1077 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
1078 }
1079
1080 /**
1081 * @brief Check if Master Rx auto suspend is activated
1082 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1083 * @param SPIx SPI Instance
1084 * @retval State of bit (1 or 0)
1085 */
LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef * SPIx)1086 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
1087 {
1088 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1089 }
1090
1091 /**
1092 * @brief Set Underrun behavior
1093 * @note This configuration can not be changed when SPI is enabled.
1094 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1095 * @param SPIx SPI Instance
1096 * @param UDRConfig This parameter can be one of the following values:
1097 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1098 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1099 * @retval None
1100 */
LL_SPI_SetUDRConfiguration(SPI_TypeDef * SPIx,uint32_t UDRConfig)1101 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1102 {
1103 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1104 }
1105
1106 /**
1107 * @brief Get Underrun behavior
1108 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1109 * @param SPIx SPI Instance
1110 * @retval Returned value can be one of the following values:
1111 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1112 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1113 */
LL_SPI_GetUDRConfiguration(const SPI_TypeDef * SPIx)1114 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
1115 {
1116 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1117 }
1118
1119
1120 /**
1121 * @brief Set Serial protocol used
1122 * @note This configuration can not be changed when SPI is enabled.
1123 * @rmtoll CFG2 SP LL_SPI_SetStandard
1124 * @param SPIx SPI Instance
1125 * @param Standard This parameter can be one of the following values:
1126 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1127 * @arg @ref LL_SPI_PROTOCOL_TI
1128 * @retval None
1129 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1130 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1131 {
1132 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1133 }
1134
1135 /**
1136 * @brief Get Serial protocol used
1137 * @rmtoll CFG2 SP LL_SPI_GetStandard
1138 * @param SPIx SPI Instance
1139 * @retval Returned value can be one of the following values:
1140 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1141 * @arg @ref LL_SPI_PROTOCOL_TI
1142 */
LL_SPI_GetStandard(const SPI_TypeDef * SPIx)1143 __STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
1144 {
1145 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1146 }
1147
1148 /**
1149 * @brief Set Clock phase
1150 * @note This configuration can not be changed when SPI is enabled.
1151 * This bit is not used in SPI TI mode.
1152 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1153 * @param SPIx SPI Instance
1154 * @param ClockPhase This parameter can be one of the following values:
1155 * @arg @ref LL_SPI_PHASE_1EDGE
1156 * @arg @ref LL_SPI_PHASE_2EDGE
1157 * @retval None
1158 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)1159 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1160 {
1161 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1162 }
1163
1164 /**
1165 * @brief Get Clock phase
1166 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1167 * @param SPIx SPI Instance
1168 * @retval Returned value can be one of the following values:
1169 * @arg @ref LL_SPI_PHASE_1EDGE
1170 * @arg @ref LL_SPI_PHASE_2EDGE
1171 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)1172 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
1173 {
1174 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1175 }
1176
1177 /**
1178 * @brief Set Clock polarity
1179 * @note This configuration can not be changed when SPI is enabled.
1180 * This bit is not used in SPI TI mode.
1181 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1182 * @param SPIx SPI Instance
1183 * @param ClockPolarity This parameter can be one of the following values:
1184 * @arg @ref LL_SPI_POLARITY_LOW
1185 * @arg @ref LL_SPI_POLARITY_HIGH
1186 * @retval None
1187 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1188 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1189 {
1190 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1191 }
1192
1193 /**
1194 * @brief Get Clock polarity
1195 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1196 * @param SPIx SPI Instance
1197 * @retval Returned value can be one of the following values:
1198 * @arg @ref LL_SPI_POLARITY_LOW
1199 * @arg @ref LL_SPI_POLARITY_HIGH
1200 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)1201 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
1202 {
1203 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1204 }
1205
1206 /**
1207 * @brief Set NSS polarity
1208 * @note This configuration can not be changed when SPI is enabled.
1209 * This bit is not used in SPI TI mode.
1210 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1211 * @param SPIx SPI Instance
1212 * @param NSSPolarity This parameter can be one of the following values:
1213 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1214 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1215 * @retval None
1216 */
LL_SPI_SetNSSPolarity(SPI_TypeDef * SPIx,uint32_t NSSPolarity)1217 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1218 {
1219 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1220 }
1221
1222 /**
1223 * @brief Get NSS polarity
1224 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1225 * @param SPIx SPI Instance
1226 * @retval Returned value can be one of the following values:
1227 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1228 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1229 */
LL_SPI_GetNSSPolarity(const SPI_TypeDef * SPIx)1230 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
1231 {
1232 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1233 }
1234
1235 /**
1236 * @brief Set Baudrate Prescaler
1237 * @note This configuration can not be changed when SPI is enabled.
1238 * SPI BaudRate = fPCLK/Pescaler.
1239 * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n
1240 * CFG1 BPASS LL_SPI_SetBaudRatePrescaler
1241 * @param SPIx SPI Instance
1242 * @param Baudrate This parameter can be one of the following values:
1243 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1244 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1245 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1246 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1247 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1248 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1249 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1250 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1251 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1252 * @retval None
1253 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t Baudrate)1254 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1255 {
1256 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
1257 }
1258
1259 /**
1260 * @brief Get Baudrate Prescaler
1261 * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n
1262 * CFG1 BPASS LL_SPI_GetBaudRatePrescaler
1263 * @param SPIx SPI Instance
1264 * @retval Returned value can be one of the following values:
1265 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1266 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1267 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1268 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1269 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1270 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1271 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1272 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1273 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1274 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)1275 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
1276 {
1277 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
1278 }
1279
1280 /**
1281 * @brief Set Transfer Bit Order
1282 * @note This configuration can not be changed when SPI is enabled.
1283 * This bit is not used in SPI TI mode.
1284 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1285 * @param SPIx SPI Instance
1286 * @param BitOrder This parameter can be one of the following values:
1287 * @arg @ref LL_SPI_LSB_FIRST
1288 * @arg @ref LL_SPI_MSB_FIRST
1289 * @retval None
1290 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)1291 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1292 {
1293 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1294 }
1295
1296 /**
1297 * @brief Get Transfer Bit Order
1298 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1299 * @param SPIx SPI Instance
1300 * @retval Returned value can be one of the following values:
1301 * @arg @ref LL_SPI_LSB_FIRST
1302 * @arg @ref LL_SPI_MSB_FIRST
1303 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)1304 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
1305 {
1306 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1307 }
1308
1309 /**
1310 * @brief Set Transfer Mode
1311 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1312 * using LL_SPI_SetHalfDuplexDirection.
1313 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1314 * CFG2 COMM LL_SPI_SetTransferDirection
1315 * @param SPIx SPI Instance
1316 * @param TransferDirection This parameter can be one of the following values:
1317 * @arg @ref LL_SPI_FULL_DUPLEX
1318 * @arg @ref LL_SPI_SIMPLEX_TX
1319 * @arg @ref LL_SPI_SIMPLEX_RX
1320 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1321 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1322 * @retval None
1323 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)1324 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1325 {
1326 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1327 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1328 }
1329
1330 /**
1331 * @brief Get Transfer Mode
1332 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1333 * CFG2 COMM LL_SPI_GetTransferDirection
1334 * @param SPIx SPI Instance
1335 * @retval Returned value can be one of the following values:
1336 * @arg @ref LL_SPI_FULL_DUPLEX
1337 * @arg @ref LL_SPI_SIMPLEX_TX
1338 * @arg @ref LL_SPI_SIMPLEX_RX
1339 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1340 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1341 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)1342 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
1343 {
1344 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1345 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1346 return (Hddir | Comm);
1347 }
1348
1349 /**
1350 * @brief Set direction for Half-Duplex Mode
1351 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1352 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1353 * @param SPIx SPI Instance
1354 * @param HalfDuplexDirection This parameter can be one of the following values:
1355 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1356 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1357 * @retval None
1358 */
LL_SPI_SetHalfDuplexDirection(SPI_TypeDef * SPIx,uint32_t HalfDuplexDirection)1359 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1360 {
1361 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1362 }
1363
1364 /**
1365 * @brief Get direction for Half-Duplex Mode
1366 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1367 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1368 * @param SPIx SPI Instance
1369 * @retval Returned value can be one of the following values:
1370 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1371 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1372 */
LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef * SPIx)1373 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
1374 {
1375 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1376 }
1377
1378 /**
1379 * @brief Set Frame Data Size
1380 * @note This configuration can not be changed when SPI is enabled.
1381 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1382 * @param SPIx SPI Instance
1383 * @param DataWidth This parameter can be one of the following values:
1384 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1385 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1386 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1387 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1388 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1389 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1390 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1391 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1392 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1393 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1394 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1395 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1396 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1397 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1398 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1399 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1400 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1401 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1402 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1403 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1404 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1405 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1406 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1407 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1408 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1409 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1410 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1411 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1412 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1413 * @retval None
1414 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)1415 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1416 {
1417 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1418 }
1419
1420 /**
1421 * @brief Get Frame Data Size
1422 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1423 * @param SPIx SPI Instance
1424 * @retval Returned value can be one of the following values:
1425 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1426 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1427 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1428 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1429 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1430 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1431 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1432 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1433 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1434 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1435 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1436 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1437 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1438 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1439 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1440 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1441 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1442 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1443 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1444 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1445 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1446 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1447 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1448 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1449 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1450 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1451 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1452 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1453 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1454 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)1455 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
1456 {
1457 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1458 }
1459
1460 /**
1461 * @brief Set threshold of FIFO that triggers a transfer event
1462 * @note This configuration can not be changed when SPI is enabled.
1463 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1464 * @param SPIx SPI Instance
1465 * @param Threshold This parameter can be one of the following values:
1466 * @arg @ref LL_SPI_FIFO_TH_01DATA
1467 * @arg @ref LL_SPI_FIFO_TH_02DATA
1468 * @arg @ref LL_SPI_FIFO_TH_03DATA
1469 * @arg @ref LL_SPI_FIFO_TH_04DATA
1470 * @arg @ref LL_SPI_FIFO_TH_05DATA
1471 * @arg @ref LL_SPI_FIFO_TH_06DATA
1472 * @arg @ref LL_SPI_FIFO_TH_07DATA
1473 * @arg @ref LL_SPI_FIFO_TH_08DATA
1474 * @arg @ref LL_SPI_FIFO_TH_09DATA
1475 * @arg @ref LL_SPI_FIFO_TH_10DATA
1476 * @arg @ref LL_SPI_FIFO_TH_11DATA
1477 * @arg @ref LL_SPI_FIFO_TH_12DATA
1478 * @arg @ref LL_SPI_FIFO_TH_13DATA
1479 * @arg @ref LL_SPI_FIFO_TH_14DATA
1480 * @arg @ref LL_SPI_FIFO_TH_15DATA
1481 * @arg @ref LL_SPI_FIFO_TH_16DATA
1482 * @retval None
1483 */
LL_SPI_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)1484 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1485 {
1486 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1487 }
1488
1489 /**
1490 * @brief Get threshold of FIFO that triggers a transfer event
1491 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1492 * @param SPIx SPI Instance
1493 * @retval Returned value can be one of the following values:
1494 * @arg @ref LL_SPI_FIFO_TH_01DATA
1495 * @arg @ref LL_SPI_FIFO_TH_02DATA
1496 * @arg @ref LL_SPI_FIFO_TH_03DATA
1497 * @arg @ref LL_SPI_FIFO_TH_04DATA
1498 * @arg @ref LL_SPI_FIFO_TH_05DATA
1499 * @arg @ref LL_SPI_FIFO_TH_06DATA
1500 * @arg @ref LL_SPI_FIFO_TH_07DATA
1501 * @arg @ref LL_SPI_FIFO_TH_08DATA
1502 * @arg @ref LL_SPI_FIFO_TH_09DATA
1503 * @arg @ref LL_SPI_FIFO_TH_10DATA
1504 * @arg @ref LL_SPI_FIFO_TH_11DATA
1505 * @arg @ref LL_SPI_FIFO_TH_12DATA
1506 * @arg @ref LL_SPI_FIFO_TH_13DATA
1507 * @arg @ref LL_SPI_FIFO_TH_14DATA
1508 * @arg @ref LL_SPI_FIFO_TH_15DATA
1509 * @arg @ref LL_SPI_FIFO_TH_16DATA
1510 */
LL_SPI_GetFIFOThreshold(const SPI_TypeDef * SPIx)1511 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
1512 {
1513 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1514 }
1515
1516 /**
1517 * @brief Enable CRC
1518 * @note This configuration can not be changed when SPI is enabled.
1519 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1520 * @param SPIx SPI Instance
1521 * @retval None
1522 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)1523 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1524 {
1525 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1526 }
1527
1528 /**
1529 * @brief Disable CRC
1530 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1531 * @param SPIx SPI Instance
1532 * @retval None
1533 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)1534 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1535 {
1536 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1537 }
1538
1539 /**
1540 * @brief Check if CRC is enabled
1541 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1542 * @param SPIx SPI Instance
1543 * @retval State of bit (1 or 0).
1544 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)1545 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
1546 {
1547 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1548 }
1549
1550 /**
1551 * @brief Set CRC Length
1552 * @note This configuration can not be changed when SPI is enabled.
1553 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1554 * @param SPIx SPI Instance
1555 * @param CRCLength This parameter can be one of the following values:
1556 * @arg @ref LL_SPI_CRC_4BIT
1557 * @arg @ref LL_SPI_CRC_5BIT
1558 * @arg @ref LL_SPI_CRC_6BIT
1559 * @arg @ref LL_SPI_CRC_7BIT
1560 * @arg @ref LL_SPI_CRC_8BIT
1561 * @arg @ref LL_SPI_CRC_9BIT
1562 * @arg @ref LL_SPI_CRC_10BIT
1563 * @arg @ref LL_SPI_CRC_11BIT
1564 * @arg @ref LL_SPI_CRC_12BIT
1565 * @arg @ref LL_SPI_CRC_13BIT
1566 * @arg @ref LL_SPI_CRC_14BIT
1567 * @arg @ref LL_SPI_CRC_15BIT
1568 * @arg @ref LL_SPI_CRC_16BIT
1569 * @arg @ref LL_SPI_CRC_17BIT
1570 * @arg @ref LL_SPI_CRC_18BIT
1571 * @arg @ref LL_SPI_CRC_19BIT
1572 * @arg @ref LL_SPI_CRC_20BIT
1573 * @arg @ref LL_SPI_CRC_21BIT
1574 * @arg @ref LL_SPI_CRC_22BIT
1575 * @arg @ref LL_SPI_CRC_23BIT
1576 * @arg @ref LL_SPI_CRC_24BIT
1577 * @arg @ref LL_SPI_CRC_25BIT
1578 * @arg @ref LL_SPI_CRC_26BIT
1579 * @arg @ref LL_SPI_CRC_27BIT
1580 * @arg @ref LL_SPI_CRC_28BIT
1581 * @arg @ref LL_SPI_CRC_29BIT
1582 * @arg @ref LL_SPI_CRC_30BIT
1583 * @arg @ref LL_SPI_CRC_31BIT
1584 * @arg @ref LL_SPI_CRC_32BIT
1585 * @retval None
1586 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)1587 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1588 {
1589 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1590 }
1591
1592 /**
1593 * @brief Get CRC Length
1594 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1595 * @param SPIx SPI Instance
1596 * @retval Returned value can be one of the following values:
1597 * @arg @ref LL_SPI_CRC_4BIT
1598 * @arg @ref LL_SPI_CRC_5BIT
1599 * @arg @ref LL_SPI_CRC_6BIT
1600 * @arg @ref LL_SPI_CRC_7BIT
1601 * @arg @ref LL_SPI_CRC_8BIT
1602 * @arg @ref LL_SPI_CRC_9BIT
1603 * @arg @ref LL_SPI_CRC_10BIT
1604 * @arg @ref LL_SPI_CRC_11BIT
1605 * @arg @ref LL_SPI_CRC_12BIT
1606 * @arg @ref LL_SPI_CRC_13BIT
1607 * @arg @ref LL_SPI_CRC_14BIT
1608 * @arg @ref LL_SPI_CRC_15BIT
1609 * @arg @ref LL_SPI_CRC_16BIT
1610 * @arg @ref LL_SPI_CRC_17BIT
1611 * @arg @ref LL_SPI_CRC_18BIT
1612 * @arg @ref LL_SPI_CRC_19BIT
1613 * @arg @ref LL_SPI_CRC_20BIT
1614 * @arg @ref LL_SPI_CRC_21BIT
1615 * @arg @ref LL_SPI_CRC_22BIT
1616 * @arg @ref LL_SPI_CRC_23BIT
1617 * @arg @ref LL_SPI_CRC_24BIT
1618 * @arg @ref LL_SPI_CRC_25BIT
1619 * @arg @ref LL_SPI_CRC_26BIT
1620 * @arg @ref LL_SPI_CRC_27BIT
1621 * @arg @ref LL_SPI_CRC_28BIT
1622 * @arg @ref LL_SPI_CRC_29BIT
1623 * @arg @ref LL_SPI_CRC_30BIT
1624 * @arg @ref LL_SPI_CRC_31BIT
1625 * @arg @ref LL_SPI_CRC_32BIT
1626 */
LL_SPI_GetCRCWidth(const SPI_TypeDef * SPIx)1627 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
1628 {
1629 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1630 }
1631
1632 /**
1633 * @brief Set NSS Mode
1634 * @note This configuration can not be changed when SPI is enabled.
1635 * This bit is not used in SPI TI mode.
1636 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1637 * CFG2 SSOE LL_SPI_SetNSSMode
1638 * @param SPIx SPI Instance
1639 * @param NSS This parameter can be one of the following values:
1640 * @arg @ref LL_SPI_NSS_SOFT
1641 * @arg @ref LL_SPI_NSS_HARD_INPUT
1642 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1643 * @retval None
1644 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)1645 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1646 {
1647 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1648 }
1649
1650 /**
1651 * @brief Set NSS Mode
1652 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1653 * CFG2 SSOE LL_SPI_GetNSSMode
1654 * @param SPIx SPI Instance
1655 * @retval Returned value can be one of the following values:
1656 * @arg @ref LL_SPI_NSS_SOFT
1657 * @arg @ref LL_SPI_NSS_HARD_INPUT
1658 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1659 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)1660 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
1661 {
1662 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1663 }
1664
1665 /**
1666 * @brief Enable NSS pulse mgt
1667 * @note This configuration can not be changed when SPI is enabled.
1668 * This bit is not used in SPI TI mode.
1669 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1670 * @param SPIx SPI Instance
1671 * @retval None
1672 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)1673 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1674 {
1675 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1676 }
1677
1678 /**
1679 * @brief Disable NSS pulse mgt
1680 * @note This configuration can not be changed when SPI is enabled.
1681 * This bit is not used in SPI TI mode.
1682 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1683 * @param SPIx SPI Instance
1684 * @retval None
1685 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)1686 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1687 {
1688 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1689 }
1690
1691 /**
1692 * @brief Check if NSS pulse is enabled
1693 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1694 * @param SPIx SPI Instance
1695 * @retval State of bit (1 or 0)
1696 */
LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef * SPIx)1697 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
1698 {
1699 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1700 }
1701
1702 /**
1703 * @}
1704 */
1705
1706 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1707 * @{
1708 */
1709
1710 /**
1711 * @brief Check if there is enough data in FIFO to read a full packet
1712 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1713 * @param SPIx SPI Instance
1714 * @retval State of bit (1 or 0)
1715 */
LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef * SPIx)1716 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
1717 {
1718 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1719 }
1720
1721 /**
1722 * @brief Check if there is enough space in FIFO to hold a full packet
1723 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1724 * @param SPIx SPI Instance
1725 * @retval State of bit (1 or 0)
1726 */
LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef * SPIx)1727 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
1728 {
1729 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1730 }
1731
1732 /**
1733 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1734 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1735 * @param SPIx SPI Instance
1736 * @retval State of bit (1 or 0)
1737 */
LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef * SPIx)1738 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
1739 {
1740 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1741 }
1742
1743 /**
1744 * @brief Check that end of transfer event occurred
1745 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1746 * @param SPIx SPI Instance
1747 * @retval State of bit (1 or 0).
1748 */
LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef * SPIx)1749 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
1750 {
1751 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1752 }
1753
1754 /**
1755 * @brief Check that all required data has been filled in the fifo according to transfer size
1756 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1757 * @param SPIx SPI Instance
1758 * @retval State of bit (1 or 0).
1759 */
LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef * SPIx)1760 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
1761 {
1762 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1763 }
1764
1765 /**
1766 * @brief Get Underrun error flag
1767 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1768 * @param SPIx SPI Instance
1769 * @retval State of bit (1 or 0).
1770 */
LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)1771 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1772 {
1773 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1774 }
1775
1776 /**
1777 * @brief Get CRC error flag
1778 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1779 * @param SPIx SPI Instance
1780 * @retval State of bit (1 or 0).
1781 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)1782 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
1783 {
1784 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1785 }
1786
1787 /**
1788 * @brief Get Mode fault error flag
1789 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1790 * @param SPIx SPI Instance
1791 * @retval State of bit (1 or 0).
1792 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)1793 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
1794 {
1795 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Get Overrun error flag
1800 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1801 * @param SPIx SPI Instance
1802 * @retval State of bit (1 or 0).
1803 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)1804 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1805 {
1806 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1807 }
1808
1809 /**
1810 * @brief Get TI Frame format error flag
1811 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1812 * @param SPIx SPI Instance
1813 * @retval State of bit (1 or 0).
1814 */
LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)1815 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1816 {
1817 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @brief Check if a suspend operation is done
1822 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1823 * @param SPIx SPI Instance
1824 * @retval State of bit (1 or 0)
1825 */
LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef * SPIx)1826 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
1827 {
1828 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1829 }
1830
1831 /**
1832 * @brief Check if last TxFIFO or CRC frame transmission is completed
1833 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1834 * @param SPIx SPI Instance
1835 * @retval State of bit (1 or 0).
1836 */
LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef * SPIx)1837 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
1838 {
1839 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1840 }
1841
1842 /**
1843 * @brief Check if at least one 32-bit data is available in RxFIFO
1844 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1845 * @param SPIx SPI Instance
1846 * @retval State of bit (1 or 0)
1847 */
LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef * SPIx)1848 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
1849 {
1850 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1851 }
1852
1853 /**
1854 * @brief Get number of data framed remaining in current TSIZE
1855 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1856 * @param SPIx SPI Instance
1857 * @retval 0..0xFFFF
1858 */
LL_SPI_GetRemainingDataFrames(const SPI_TypeDef * SPIx)1859 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
1860 {
1861 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1862 }
1863
1864 /**
1865 * @brief Get RxFIFO packing Level
1866 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1867 * @param SPIx SPI Instance
1868 * @retval Returned value can be one of the following values:
1869 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1870 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1871 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1872 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1873 */
LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef * SPIx)1874 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
1875 {
1876 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1877 }
1878
1879 /**
1880 * @brief Clear End Of Transfer flag
1881 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1882 * @param SPIx SPI Instance
1883 * @retval None
1884 */
LL_SPI_ClearFlag_EOT(SPI_TypeDef * SPIx)1885 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1886 {
1887 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1888 }
1889
1890 /**
1891 * @brief Clear TXTF flag
1892 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1893 * @param SPIx SPI Instance
1894 * @retval None
1895 */
LL_SPI_ClearFlag_TXTF(SPI_TypeDef * SPIx)1896 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1897 {
1898 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1899 }
1900
1901 /**
1902 * @brief Clear Underrun error flag
1903 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1904 * @param SPIx SPI Instance
1905 * @retval None
1906 */
LL_SPI_ClearFlag_UDR(SPI_TypeDef * SPIx)1907 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1908 {
1909 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1910 }
1911
1912 /**
1913 * @brief Clear Overrun error flag
1914 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1915 * @param SPIx SPI Instance
1916 * @retval None
1917 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1918 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1919 {
1920 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1921 }
1922
1923 /**
1924 * @brief Clear CRC error flag
1925 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1926 * @param SPIx SPI Instance
1927 * @retval None
1928 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1929 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1930 {
1931 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1932 }
1933
1934 /**
1935 * @brief Clear Mode fault error flag
1936 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1937 * @param SPIx SPI Instance
1938 * @retval None
1939 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1940 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1941 {
1942 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1943 }
1944
1945 /**
1946 * @brief Clear Frame format error flag
1947 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1948 * @param SPIx SPI Instance
1949 * @retval None
1950 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1951 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1952 {
1953 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1954 }
1955
1956 /**
1957 * @brief Clear SUSP flag
1958 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1959 * @param SPIx SPI Instance
1960 * @retval None
1961 */
LL_SPI_ClearFlag_SUSP(SPI_TypeDef * SPIx)1962 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1963 {
1964 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1972 * @{
1973 */
1974
1975 /**
1976 * @brief Enable Rx Packet available IT
1977 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1978 * @param SPIx SPI Instance
1979 * @retval None
1980 */
LL_SPI_EnableIT_RXP(SPI_TypeDef * SPIx)1981 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1982 {
1983 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1984 }
1985
1986 /**
1987 * @brief Enable Tx Packet space available IT
1988 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1989 * @param SPIx SPI Instance
1990 * @retval None
1991 */
LL_SPI_EnableIT_TXP(SPI_TypeDef * SPIx)1992 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1993 {
1994 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1995 }
1996
1997 /**
1998 * @brief Enable Duplex Packet available IT
1999 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
2000 * @param SPIx SPI Instance
2001 * @retval None
2002 */
LL_SPI_EnableIT_DXP(SPI_TypeDef * SPIx)2003 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
2004 {
2005 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
2006 }
2007
2008 /**
2009 * @brief Enable End Of Transfer IT
2010 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
2011 * @param SPIx SPI Instance
2012 * @retval None
2013 */
LL_SPI_EnableIT_EOT(SPI_TypeDef * SPIx)2014 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
2015 {
2016 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
2017 }
2018
2019 /**
2020 * @brief Enable TXTF IT
2021 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
2022 * @param SPIx SPI Instance
2023 * @retval None
2024 */
LL_SPI_EnableIT_TXTF(SPI_TypeDef * SPIx)2025 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
2026 {
2027 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
2028 }
2029
2030 /**
2031 * @brief Enable Underrun IT
2032 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
2033 * @param SPIx SPI Instance
2034 * @retval None
2035 */
LL_SPI_EnableIT_UDR(SPI_TypeDef * SPIx)2036 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2037 {
2038 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2039 }
2040
2041 /**
2042 * @brief Enable Overrun IT
2043 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
2044 * @param SPIx SPI Instance
2045 * @retval None
2046 */
LL_SPI_EnableIT_OVR(SPI_TypeDef * SPIx)2047 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2048 {
2049 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2050 }
2051
2052 /**
2053 * @brief Enable CRC Error IT
2054 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
2055 * @param SPIx SPI Instance
2056 * @retval None
2057 */
LL_SPI_EnableIT_CRCERR(SPI_TypeDef * SPIx)2058 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2059 {
2060 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2061 }
2062
2063 /**
2064 * @brief Enable TI Frame Format Error IT
2065 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
2066 * @param SPIx SPI Instance
2067 * @retval None
2068 */
LL_SPI_EnableIT_FRE(SPI_TypeDef * SPIx)2069 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2070 {
2071 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2072 }
2073
2074 /**
2075 * @brief Enable MODF IT
2076 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
2077 * @param SPIx SPI Instance
2078 * @retval None
2079 */
LL_SPI_EnableIT_MODF(SPI_TypeDef * SPIx)2080 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2081 {
2082 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2083 }
2084
2085 /**
2086 * @brief Disable Rx Packet available IT
2087 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2088 * @param SPIx SPI Instance
2089 * @retval None
2090 */
LL_SPI_DisableIT_RXP(SPI_TypeDef * SPIx)2091 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2092 {
2093 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2094 }
2095
2096 /**
2097 * @brief Disable Tx Packet space available IT
2098 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2099 * @param SPIx SPI Instance
2100 * @retval None
2101 */
LL_SPI_DisableIT_TXP(SPI_TypeDef * SPIx)2102 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2103 {
2104 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2105 }
2106
2107 /**
2108 * @brief Disable Duplex Packet available IT
2109 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2110 * @param SPIx SPI Instance
2111 * @retval None
2112 */
LL_SPI_DisableIT_DXP(SPI_TypeDef * SPIx)2113 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2114 {
2115 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2116 }
2117
2118 /**
2119 * @brief Disable End Of Transfer IT
2120 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2121 * @param SPIx SPI Instance
2122 * @retval None
2123 */
LL_SPI_DisableIT_EOT(SPI_TypeDef * SPIx)2124 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2125 {
2126 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2127 }
2128
2129 /**
2130 * @brief Disable TXTF IT
2131 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2132 * @param SPIx SPI Instance
2133 * @retval None
2134 */
LL_SPI_DisableIT_TXTF(SPI_TypeDef * SPIx)2135 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2136 {
2137 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2138 }
2139
2140 /**
2141 * @brief Disable Underrun IT
2142 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2143 * @param SPIx SPI Instance
2144 * @retval None
2145 */
LL_SPI_DisableIT_UDR(SPI_TypeDef * SPIx)2146 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2147 {
2148 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2149 }
2150
2151 /**
2152 * @brief Disable Overrun IT
2153 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2154 * @param SPIx SPI Instance
2155 * @retval None
2156 */
LL_SPI_DisableIT_OVR(SPI_TypeDef * SPIx)2157 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2158 {
2159 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2160 }
2161
2162 /**
2163 * @brief Disable CRC Error IT
2164 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2165 * @param SPIx SPI Instance
2166 * @retval None
2167 */
LL_SPI_DisableIT_CRCERR(SPI_TypeDef * SPIx)2168 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2169 {
2170 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2171 }
2172
2173 /**
2174 * @brief Disable TI Frame Format Error IT
2175 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2176 * @param SPIx SPI Instance
2177 * @retval None
2178 */
LL_SPI_DisableIT_FRE(SPI_TypeDef * SPIx)2179 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2180 {
2181 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2182 }
2183
2184 /**
2185 * @brief Disable MODF IT
2186 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2187 * @param SPIx SPI Instance
2188 * @retval None
2189 */
LL_SPI_DisableIT_MODF(SPI_TypeDef * SPIx)2190 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2191 {
2192 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2193 }
2194
2195 /**
2196 * @brief Check if Rx Packet available IT is enabled
2197 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2198 * @param SPIx SPI Instance
2199 * @retval State of bit (1 or 0)
2200 */
LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef * SPIx)2201 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
2202 {
2203 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2204 }
2205
2206 /**
2207 * @brief Check if Tx Packet space available IT is enabled
2208 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2209 * @param SPIx SPI Instance
2210 * @retval State of bit (1 or 0)
2211 */
LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef * SPIx)2212 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
2213 {
2214 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2215 }
2216
2217 /**
2218 * @brief Check if Duplex Packet available IT is enabled
2219 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2220 * @param SPIx SPI Instance
2221 * @retval State of bit (1 or 0)
2222 */
LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef * SPIx)2223 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
2224 {
2225 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2226 }
2227
2228 /**
2229 * @brief Check if End Of Transfer IT is enabled
2230 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2231 * @param SPIx SPI Instance
2232 * @retval State of bit (1 or 0)
2233 */
LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef * SPIx)2234 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
2235 {
2236 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2237 }
2238
2239 /**
2240 * @brief Check if TXTF IT is enabled
2241 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2242 * @param SPIx SPI Instance
2243 * @retval State of bit (1 or 0)
2244 */
LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef * SPIx)2245 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
2246 {
2247 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2248 }
2249
2250 /**
2251 * @brief Check if Underrun IT is enabled
2252 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2253 * @param SPIx SPI Instance
2254 * @retval State of bit (1 or 0)
2255 */
LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef * SPIx)2256 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
2257 {
2258 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2259 }
2260
2261 /**
2262 * @brief Check if Overrun IT is enabled
2263 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2264 * @param SPIx SPI Instance
2265 * @retval State of bit (1 or 0)
2266 */
LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef * SPIx)2267 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
2268 {
2269 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2270 }
2271
2272 /**
2273 * @brief Check if CRC Error IT is enabled
2274 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2275 * @param SPIx SPI Instance
2276 * @retval State of bit (1 or 0)
2277 */
LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef * SPIx)2278 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
2279 {
2280 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2281 }
2282
2283 /**
2284 * @brief Check if TI Frame Format Error IT is enabled
2285 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2286 * @param SPIx SPI Instance
2287 * @retval State of bit (1 or 0)
2288 */
LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef * SPIx)2289 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
2290 {
2291 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2292 }
2293
2294 /**
2295 * @brief Check if MODF IT is enabled
2296 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2297 * @param SPIx SPI Instance
2298 * @retval State of bit (1 or 0)
2299 */
LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef * SPIx)2300 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
2301 {
2302 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2303 }
2304
2305 /**
2306 * @}
2307 */
2308
2309 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2310 * @{
2311 */
2312
2313 /**
2314 * @brief Enable DMA Rx
2315 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2316 * @param SPIx SPI Instance
2317 * @retval None
2318 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)2319 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2320 {
2321 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2322 }
2323
2324 /**
2325 * @brief Disable DMA Rx
2326 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2327 * @param SPIx SPI Instance
2328 * @retval None
2329 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)2330 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2331 {
2332 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2333 }
2334
2335 /**
2336 * @brief Check if DMA Rx is enabled
2337 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2338 * @param SPIx SPI Instance
2339 * @retval State of bit (1 or 0)
2340 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)2341 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
2342 {
2343 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2344 }
2345
2346 /**
2347 * @brief Enable DMA Tx
2348 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2349 * @param SPIx SPI Instance
2350 * @retval None
2351 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)2352 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2353 {
2354 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2355 }
2356
2357 /**
2358 * @brief Disable DMA Tx
2359 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2360 * @param SPIx SPI Instance
2361 * @retval None
2362 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)2363 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2364 {
2365 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2366 }
2367
2368 /**
2369 * @brief Check if DMA Tx is enabled
2370 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2371 * @param SPIx SPI Instance
2372 * @retval State of bit (1 or 0)
2373 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)2374 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
2375 {
2376 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2377 }
2378 /**
2379 * @brief Get the data register address used for DMA transfer
2380 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2381 * @param SPIx SPI Instance
2382 * @retval Address of data register
2383 */
LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef * SPIx)2384 __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
2385 {
2386 return (uint32_t) &(SPIx->TXDR);
2387 }
2388
2389 /**
2390 * @brief Get the data register address used for DMA transfer
2391 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2392 * @param SPIx SPI Instance
2393 * @retval Address of data register
2394 */
LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef * SPIx)2395 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
2396 {
2397 return (uint32_t) &(SPIx->RXDR);
2398 }
2399 /**
2400 * @}
2401 */
2402
2403 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2404 * @{
2405 */
2406
2407 /**
2408 * @brief Read Data Register
2409 * @rmtoll RXDR . LL_SPI_ReceiveData8
2410 * @param SPIx SPI Instance
2411 * @retval 0..0xFF
2412 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)2413 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2414 {
2415 return (*((__IO uint8_t *)&SPIx->RXDR));
2416 }
2417
2418 /**
2419 * @brief Read Data Register
2420 * @rmtoll RXDR . LL_SPI_ReceiveData16
2421 * @param SPIx SPI Instance
2422 * @retval 0..0xFFFF
2423 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)2424 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2425 {
2426 #if defined (__GNUC__)
2427 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2428 return (*spirxdr);
2429 #else
2430 return (*((__IO uint16_t *)&SPIx->RXDR));
2431 #endif /* __GNUC__ */
2432 }
2433
2434 /**
2435 * @brief Read Data Register
2436 * @rmtoll RXDR . LL_SPI_ReceiveData32
2437 * @param SPIx SPI Instance
2438 * @retval 0..0xFFFFFFFF
2439 */
LL_SPI_ReceiveData32(SPI_TypeDef * SPIx)2440 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2441 {
2442 return (*((__IO uint32_t *)&SPIx->RXDR));
2443 }
2444
2445 /**
2446 * @brief Write Data Register
2447 * @rmtoll TXDR . LL_SPI_TransmitData8
2448 * @param SPIx SPI Instance
2449 * @param TxData 0..0xFF
2450 * @retval None
2451 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)2452 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2453 {
2454 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2455 }
2456
2457 /**
2458 * @brief Write Data Register
2459 * @rmtoll TXDR . LL_SPI_TransmitData16
2460 * @param SPIx SPI Instance
2461 * @param TxData 0..0xFFFF
2462 * @retval None
2463 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2464 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2465 {
2466 #if defined (__GNUC__)
2467 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2468 *spitxdr = TxData;
2469 #else
2470 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2471 #endif /* __GNUC__ */
2472 }
2473
2474 /**
2475 * @brief Write Data Register
2476 * @rmtoll TXDR . LL_SPI_TransmitData32
2477 * @param SPIx SPI Instance
2478 * @param TxData 0..0xFFFFFFFF
2479 * @retval None
2480 */
LL_SPI_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)2481 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2482 {
2483 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2484 }
2485
2486 /**
2487 * @brief Set polynomial for CRC calcul
2488 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2489 * @param SPIx SPI Instance
2490 * @param CRCPoly 0..0xFFFFFFFF
2491 * @retval None
2492 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)2493 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2494 {
2495 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2496 }
2497
2498 /**
2499 * @brief Get polynomial for CRC calcul
2500 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2501 * @param SPIx SPI Instance
2502 * @retval 0..0xFFFFFFFF
2503 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)2504 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
2505 {
2506 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2507 }
2508
2509 /**
2510 * @brief Set the underrun pattern
2511 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2512 * @param SPIx SPI Instance
2513 * @param Pattern 0..0xFFFFFFFF
2514 * @retval None
2515 */
LL_SPI_SetUDRPattern(SPI_TypeDef * SPIx,uint32_t Pattern)2516 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2517 {
2518 WRITE_REG(SPIx->UDRDR, Pattern);
2519 }
2520
2521 /**
2522 * @brief Get the underrun pattern
2523 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2524 * @param SPIx SPI Instance
2525 * @retval 0..0xFFFFFFFF
2526 */
LL_SPI_GetUDRPattern(const SPI_TypeDef * SPIx)2527 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
2528 {
2529 return (uint32_t)(READ_REG(SPIx->UDRDR));
2530 }
2531
2532 /**
2533 * @brief Get Rx CRC
2534 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2535 * @param SPIx SPI Instance
2536 * @retval 0..0xFFFFFFFF
2537 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)2538 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
2539 {
2540 return (uint32_t)(READ_REG(SPIx->RXCRC));
2541 }
2542
2543 /**
2544 * @brief Get Tx CRC
2545 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2546 * @param SPIx SPI Instance
2547 * @retval 0..0xFFFFFFFF
2548 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)2549 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
2550 {
2551 return (uint32_t)(READ_REG(SPIx->TXCRC));
2552 }
2553
2554 /**
2555 * @}
2556 */
2557
2558 /** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature
2559 * @{
2560 */
2561
2562 /**
2563 * @brief Enable Selected Trigger
2564 * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger
2565 * @param SPIx SPI Instance.
2566 * @retval None
2567 */
LL_SPI_Enable_SelectedTrigger(SPI_TypeDef * SPIx)2568 __STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx)
2569 {
2570 SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
2571 }
2572
2573 /**
2574 * @brief Disable Selected Trigger
2575 * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger
2576 * @param SPIx SPI Instance.
2577 * @retval None
2578 */
LL_SPI_Disable_SelectedTrigger(SPI_TypeDef * SPIx)2579 __STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx)
2580 {
2581 CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
2582 }
2583
2584 /**
2585 * @brief Indicate if selected Trigger is disabled or enabled
2586 * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger
2587 * @param SPIx SPI Instance.
2588 * @retval State of bit (1 or 0).
2589 */
LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef * SPIx)2590 __STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx)
2591 {
2592 return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2593 }
2594
2595 /**
2596 * @brief Set the trigger polarity
2597 * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity
2598 * @param SPIx SPI Instance.
2599 * @param Polarity This parameter can be one of the following values:
2600 * @arg @ref LL_SPI_TRIG_POLARITY_RISING
2601 * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
2602 * @retval None
2603 */
LL_SPI_SetTriggerPolarity(SPI_TypeDef * SPIx,uint32_t Polarity)2604 __STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity)
2605 {
2606 MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity);
2607 }
2608
2609 /**
2610 * @brief Get the trigger polarity
2611 * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity
2612 * @param SPIx SPI Instance.
2613 * @retval Returned value can be one of the following values:
2614 * @arg @ref LL_SPI_TRIG_POLARITY_RISING
2615 * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
2616 */
LL_SPI_GetTriggerPolarity(const SPI_TypeDef * SPIx)2617 __STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx)
2618 {
2619 return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL));
2620 }
2621
2622 /**
2623 * @brief Set the selected trigger
2624 * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger
2625 * @param SPIx SPI Instance.
2626 * @param Trigger This parameter can be one of the following values:
2627 * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
2628 * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
2629 * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
2630 * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
2631 * @arg @ref LL_SPI_GRP1_EXTI4_TRG
2632 * @arg @ref LL_SPI_GRP1_EXTI9_TRG
2633 * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
2634 * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
2635 * @arg @ref LL_SPI_GRP1_COMP1_TRG
2636 * @arg @ref LL_SPI_GRP1_COMP2_TRG
2637 * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
2638 * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
2639 * @arg @ref LL_SPI_GRP2_GPDMA_CH0_TCF_TRG
2640 * @arg @ref LL_SPI_GRP2_GPDMA_CH1_TCF_TRG
2641 * @arg @ref LL_SPI_GRP2_GPDMA_CH2_TCF_TRG
2642 * @arg @ref LL_SPI_GRP2_GPDMA_CH3_TCF_TRG
2643 * @arg @ref LL_SPI_GRP2_EXTI4_TRG
2644 * @arg @ref LL_SPI_GRP2_EXTI8_TRG
2645 * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
2646 * @arg @ref LL_SPI_GRP2_COMP1_TRG
2647 * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
2648 * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
2649 * @retval None
2650 */
LL_SPI_SetSelectedTrigger(SPI_TypeDef * SPIx,uint32_t Trigger)2651 __STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger)
2652 {
2653 MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk));
2654 }
2655
2656 /**
2657 * @brief Get the selected trigger
2658 * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger
2659 * @param SPIx SPI Instance.
2660 * @retval Returned value can be one of the following values:
2661 * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
2662 * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
2663 * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
2664 * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
2665 * @arg @ref LL_SPI_GRP1_EXTI4_TRG
2666 * @arg @ref LL_SPI_GRP1_EXTI9_TRG
2667 * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
2668 * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
2669 * @arg @ref LL_SPI_GRP1_COMP1_TRG
2670 * @arg @ref LL_SPI_GRP1_COMP2_TRG
2671 * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
2672 * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
2673 * @arg @ref LL_SPI_GRP2_GPDMA_CH0_TCF_TRG
2674 * @arg @ref LL_SPI_GRP2_GPDMA_CH1_TCF_TRG
2675 * @arg @ref LL_SPI_GRP2_GPDMA_CH2_TCF_TRG
2676 * @arg @ref LL_SPI_GRP2_GPDMA_CH3_TCF_TRG
2677 * @arg @ref LL_SPI_GRP2_EXTI4_TRG
2678 * @arg @ref LL_SPI_GRP2_EXTI8_TRG
2679 * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
2680 * @arg @ref LL_SPI_GRP2_COMP1_TRG
2681 * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
2682 * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
2683 */
LL_SPI_GetSelectedTrigger(const SPI_TypeDef * SPIx)2684 __STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx)
2685 {
2686 #if defined(LL_SPI_TRIG_GRP1)
2687 if (IS_LL_SPI_GRP2_INSTANCE(SPIx))
2688 {
2689 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
2690 }
2691 else
2692 {
2693 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1));
2694 }
2695 #else
2696 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
2697 #endif /* LL_SPI_TRIG_GRP1 */
2698 }
2699
2700 /**
2701 * @}
2702 */
2703
2704 #if defined(USE_FULL_LL_DRIVER)
2705 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2706 * @{
2707 */
2708
2709 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
2710 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2711 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2712
2713 /**
2714 * @}
2715 */
2716 #endif /* USE_FULL_LL_DRIVER */
2717 /**
2718 * @}
2719 */
2720 /**
2721 * @}
2722 */
2723
2724
2725 #endif /* defined(SPI1) || defined(SPI3) */
2726
2727 /**
2728 * @}
2729 */
2730
2731 #ifdef __cplusplus
2732 }
2733 #endif
2734
2735 #endif /* STM32WBAxx_LL_SPI_H */
2736