1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_LPTIM_H
21 #define STM32WBAxx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94
95 /* Private macros ------------------------------------------------------------*/
96 #if defined(USE_FULL_LL_DRIVER)
97 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
98 * @{
99 */
100 /**
101 * @}
102 */
103 #endif /*USE_FULL_LL_DRIVER*/
104
105 /* Exported types ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
108 * @{
109 */
110
111 /**
112 * @brief LPTIM Init structure definition
113 */
114 typedef struct
115 {
116 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
117 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPTIM_SetClockSource().*/
121
122 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
123 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
124
125 This feature can be modified afterwards using using unitary
126 function @ref LL_LPTIM_SetPrescaler().*/
127
128 uint32_t Waveform; /*!< Specifies the waveform shape.
129 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPTIM_SetWaveform().*/
133 } LL_LPTIM_InitTypeDef;
134
135 /**
136 * @}
137 */
138 #endif /* USE_FULL_LL_DRIVER */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
142 * @{
143 */
144
145 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
146 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
147 * @{
148 */
149 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
150 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
151 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
152 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
153 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
154 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
155 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
156 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
157 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
158 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
159 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
160 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
161 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
162 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_IT IT Defines
168 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
169 * @{
170 */
171 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
172 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
173 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
174 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
175 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
176 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
177 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
178 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
179 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
180 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
181 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
182 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
183 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
189 * @{
190 */
191 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
192 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
193 /**
194 * @}
195 */
196
197 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
198 * @{
199 */
200 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
201 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
202 /**
203 * @}
204 */
205
206 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
207 * @{
208 */
209 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
210 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
211 /**
212 * @}
213 */
214
215 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
216 * @{
217 */
218 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
219 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
220 /**
221 * @}
222 */
223
224 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
225 * @{
226 */
227 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
228 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
229 /**
230 * @}
231 */
232
233 /** @defgroup TIM_LL_EC_CHANNEL Channel
234 * @{
235 */
236 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
237 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
243 * @{
244 */
245 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
246 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
247 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
248 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
249 /**
250 * @}
251 */
252
253 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
254 * @{
255 */
256 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
257 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
258 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
259 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
260 /**
261 * @}
262 */
263
264 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
265 * @{
266 */
267 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
268 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
269 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
270 /**
271 * @}
272 */
273 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
274 * @{
275 */
276 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
277 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
278 /**
279 * @}
280 */
281
282 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
283 * @{
284 */
285 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
286 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
287 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
288 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
289 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
290 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
291 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
292 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
293 /**
294 * @}
295 */
296
297 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
298 * @{
299 */
300 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
301 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
302 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
303 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
304 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
305 #if defined(COMP1)
306 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
307 #endif /* COMP1 */
308 #if defined(COMP2)
309 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
310 #endif /* COMP2 */
311 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
312 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
313 /**
314 * @}
315 */
316
317 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
318 * @{
319 */
320 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
321 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
322 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
323 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
324 /**
325 * @}
326 */
327
328 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
329 * @{
330 */
331 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
332 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
333 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
334 /**
335 * @}
336 */
337
338 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
339 * @{
340 */
341 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
342 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
343 /**
344 * @}
345 */
346
347 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
348 * @{
349 */
350 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
351 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
352 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
353 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
354 /**
355 * @}
356 */
357
358 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
359 * @{
360 */
361 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
362 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
363 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
364 /**
365 * @}
366 */
367
368 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
369 * @{
370 */
371 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
372 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
373 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
374 /**
375 * @}
376 */
377
378 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
379 * @{
380 */
381 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
382 #if defined(COMP1)
383 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
384 #endif /* COMP1 */
385 /**
386 * @}
387 */
388
389 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
390 * @{
391 */
392 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
393 #if defined(COMP2)
394 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */
395 #endif /* COMP2 */
396 /**
397 * @}
398 */
399
400 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
401 * @{
402 */
403 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
404 #if defined(COMP1)
405 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
406 #endif /* COMP1 */
407 #if defined(COMP2)
408 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
409 #endif /* COMP2 */
410 /**
411 * @}
412 */
413
414 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
415 * @{
416 */
417 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
418 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
419 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
420 /**
421 * @}
422 */
423
424 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
425 * @{
426 */
427 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
428 #if defined(COMP1)
429 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
430 #endif /* COMP1 */
431 #if defined(COMP2)
432 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
433 #endif /* COMP2 */
434 /**
435 * @}
436 */
437
438 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
439 * @{
440 */
441 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
442 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_256 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI/256 */
443 /**
444 * @}
445 */
446
447
448 /**
449 * @}
450 */
451
452 /* Exported macro ------------------------------------------------------------*/
453 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
454 * @{
455 */
456
457 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
458 * @{
459 */
460
461 /**
462 * @brief Write a value in LPTIM register
463 * @param __INSTANCE__ LPTIM Instance
464 * @param __REG__ Register to be written
465 * @param __VALUE__ Value to be written in the register
466 * @retval None
467 */
468 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
469
470 /**
471 * @brief Read a value in LPTIM register
472 * @param __INSTANCE__ LPTIM Instance
473 * @param __REG__ Register to be read
474 * @retval Register value
475 */
476 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
477
478 /**
479 * @brief LPTimer Input Capture Get Offset(in counter step unit)
480 * @note The real capture value corresponding to the input capture trigger can be calculated using
481 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
482 * The Offset value is depending on the glitch filter value for the channel
483 * and the value of the prescaler for the kernel clock.
484 * Please check Errata Sheet V1_8 for more details under "variable latency
485 * on input capture channel" section.
486 * @param __PSC__ This parameter can be one of the following values:
487 * @arg @ref LL_LPTIM_PRESCALER_DIV1
488 * @arg @ref LL_LPTIM_PRESCALER_DIV2
489 * @arg @ref LL_LPTIM_PRESCALER_DIV4
490 * @arg @ref LL_LPTIM_PRESCALER_DIV8
491 * @arg @ref LL_LPTIM_PRESCALER_DIV16
492 * @arg @ref LL_LPTIM_PRESCALER_DIV32
493 * @arg @ref LL_LPTIM_PRESCALER_DIV64
494 * @arg @ref LL_LPTIM_PRESCALER_DIV128
495 * @param __FLT__ This parameter can be one of the following values:
496 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
497 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
498 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
499 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
500 * @retval offset value
501 */
502 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
503 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
504 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
505 /**
506 * @}
507 */
508
509 /**
510 * @}
511 */
512
513 /* Exported functions --------------------------------------------------------*/
514 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
515 * @{
516 */
517
518 /** Legacy definitions for compatibility purpose
519 @cond 0
520 */
521 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
522 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
523 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
524 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
525 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
526 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
527 /**
528 @endcond
529 */
530
531 #if defined(USE_FULL_LL_DRIVER)
532 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
533 * @{
534 */
535
536 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
537 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
538 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
539 /**
540 * @}
541 */
542 #endif /* USE_FULL_LL_DRIVER */
543
544 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
545 * @{
546 */
547
548 /**
549 * @brief Enable the LPTIM instance
550 * @note After setting the ENABLE bit, a delay of two counter clock is needed
551 * before the LPTIM instance is actually enabled.
552 * @rmtoll CR ENABLE LL_LPTIM_Enable
553 * @param LPTIMx Low-Power Timer instance
554 * @retval None
555 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)556 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
557 {
558 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
559 }
560
561 /**
562 * @brief Disable the LPTIM instance
563 * @rmtoll CR ENABLE LL_LPTIM_Disable
564 * @param LPTIMx Low-Power Timer instance
565 * @retval None
566 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)567 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
568 {
569 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
570 }
571
572 /**
573 * @brief Indicates whether the LPTIM instance is enabled.
574 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
575 * @param LPTIMx Low-Power Timer instance
576 * @retval State of bit (1 or 0).
577 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)578 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
579 {
580 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
581 }
582
583 /**
584 * @brief Starts the LPTIM counter in the desired mode.
585 * @note LPTIM instance must be enabled before starting the counter.
586 * @note It is possible to change on the fly from One Shot mode to
587 * Continuous mode.
588 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
589 * CR SNGSTRT LL_LPTIM_StartCounter
590 * @param LPTIMx Low-Power Timer instance
591 * @param OperatingMode This parameter can be one of the following values:
592 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
593 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
594 * @retval None
595 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)596 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
597 {
598 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
599 }
600
601 /**
602 * @brief Enable reset after read.
603 * @note After calling this function any read access to LPTIM_CNT
604 * register will asynchronously reset the LPTIM_CNT register content.
605 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
606 * @param LPTIMx Low-Power Timer instance
607 * @retval None
608 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)609 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
610 {
611 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
612 }
613
614 /**
615 * @brief Disable reset after read.
616 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
617 * @param LPTIMx Low-Power Timer instance
618 * @retval None
619 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)620 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
621 {
622 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
623 }
624
625 /**
626 * @brief Indicate whether the reset after read feature is enabled.
627 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
628 * @param LPTIMx Low-Power Timer instance
629 * @retval State of bit (1 or 0).
630 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)631 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
632 {
633 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
634 }
635
636 /**
637 * @brief Reset of the LPTIM_CNT counter register (synchronous).
638 * @note Due to the synchronous nature of this reset, it only takes
639 * place after a synchronization delay of 3 LPTIM core clock cycles
640 * (LPTIM core clock may be different from APB clock).
641 * @note COUNTRST is automatically cleared by hardware
642 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
643 * @param LPTIMx Low-Power Timer instance
644 * @retval None
645 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)646 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
647 {
648 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
649 }
650
651 /**
652 * @brief Set the LPTIM registers update mode (enable/disable register preload)
653 * @note This function must be called when the LPTIM instance is disabled.
654 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
655 * @param LPTIMx Low-Power Timer instance
656 * @param UpdateMode This parameter can be one of the following values:
657 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
658 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
659 * @retval None
660 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)661 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
662 {
663 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
664 }
665
666 /**
667 * @brief Get the LPTIM registers update mode
668 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
669 * @param LPTIMx Low-Power Timer instance
670 * @retval Returned value can be one of the following values:
671 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
672 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
673 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)674 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
675 {
676 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
677 }
678
679 /**
680 * @brief Set the auto reload value
681 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
682 * @note After a write to the LPTIMx_ARR register a new write operation to the
683 * same register can only be performed when the previous write operation
684 * is completed. Any successive write before the ARROK flag is set, will
685 * lead to unpredictable results.
686 * @note autoreload value be strictly greater than the compare value.
687 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
688 * @param LPTIMx Low-Power Timer instance
689 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
690 * @retval None
691 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)692 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
693 {
694 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
695 }
696
697 /**
698 * @brief Get actual auto reload value
699 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
700 * @param LPTIMx Low-Power Timer instance
701 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
702 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)703 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
704 {
705 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
706 }
707
708 /**
709 * @brief Set the repetition value
710 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
711 * @rmtoll RCR REP LL_LPTIM_SetRepetition
712 * @param LPTIMx Low-Power Timer instance
713 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
714 * @retval None
715 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)716 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
717 {
718 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
719 }
720
721 /**
722 * @brief Get the repetition value
723 * @rmtoll RCR REP LL_LPTIM_GetRepetition
724 * @param LPTIMx Low-Power Timer instance
725 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
726 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)727 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
728 {
729 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
730 }
731
732 /**
733 * @brief Enable capture/compare channel.
734 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
735 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
736 * @param LPTIMx LPTimer instance
737 * @param Channel This parameter can be one of the following values:
738 * @arg @ref LL_LPTIM_CHANNEL_CH1
739 * @arg @ref LL_LPTIM_CHANNEL_CH2
740 * @retval None
741 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)742 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
743 {
744 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
745 }
746
747 /**
748 * @brief Disable capture/compare channel.
749 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
750 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
751 * @param LPTIMx LPTimer instance
752 * @param Channel This parameter can be one of the following values:
753 * @arg @ref LL_LPTIM_CHANNEL_CH1
754 * @arg @ref LL_LPTIM_CHANNEL_CH2
755 * @retval None
756 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)757 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
758 {
759 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
760 }
761
762 /**
763 * @brief Indicate whether channel is enabled.
764 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
765 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
766 * @param LPTIMx LPTimer instance
767 * @param Channel This parameter can be one of the following values:
768 * @arg @ref LL_LPTIM_CHANNEL_CH1
769 * @arg @ref LL_LPTIM_CHANNEL_CH2
770 * @retval State of bit (1 or 0).
771 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)772 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
773 {
774 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
775 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
776
777 }
778
779 /**
780 * @brief Set the compare value
781 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
782 * same register can only be performed when the previous write operation
783 * is completed. Any successive write before the CMP1OK flag is set, will
784 * lead to unpredictable results.
785 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
786 * @param LPTIMx Low-Power Timer instance
787 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
788 * @retval None
789 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)790 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
791 {
792 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
793 }
794
795 /**
796 * @brief Get actual compare value
797 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
798 * @param LPTIMx Low-Power Timer instance
799 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
800 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)801 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
802 {
803 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
804 }
805
806 /**
807 * @brief Set the compare value
808 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
809 * same register can only be performed when the previous write operation
810 * is completed. Any successive write before the CMP2OK flag is set, will
811 * lead to unpredictable results.
812 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
813 * @param LPTIMx Low-Power Timer instance
814 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
815 * @retval None
816 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)817 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
818 {
819 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
820 }
821
822 /**
823 * @brief Get actual compare value
824 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
825 * @param LPTIMx Low-Power Timer instance
826 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
827 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)828 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
829 {
830 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
831 }
832
833 /**
834 * @brief Get actual counter value
835 * @note When the LPTIM instance is running with an asynchronous clock, reading
836 * the LPTIMx_CNT register may return unreliable values. So in this case
837 * it is necessary to perform two consecutive read accesses and verify
838 * that the two returned values are identical.
839 * @rmtoll CNT CNT LL_LPTIM_GetCounter
840 * @param LPTIMx Low-Power Timer instance
841 * @retval Counter value
842 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)843 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
844 {
845 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
846 }
847
848 /**
849 * @brief Set the counter mode (selection of the LPTIM counter clock source).
850 * @note The counter mode can be set only when the LPTIM instance is disabled.
851 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
852 * @param LPTIMx Low-Power Timer instance
853 * @param CounterMode This parameter can be one of the following values:
854 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
855 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
856 * @retval None
857 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)858 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
859 {
860 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
861 }
862
863 /**
864 * @brief Get the counter mode
865 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
866 * @param LPTIMx Low-Power Timer instance
867 * @retval Returned value can be one of the following values:
868 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
869 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
870 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)871 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
872 {
873 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
874 }
875
876 /**
877 * @brief Set waveform shape
878 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
879 * @param LPTIMx Low-Power Timer instance
880 * @param Waveform This parameter can be one of the following values:
881 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
882 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
883 * @retval None
884 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)885 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
886 {
887 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
888 }
889
890 /**
891 * @brief Get actual waveform shape
892 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
893 * @param LPTIMx Low-Power Timer instance
894 * @retval Returned value can be one of the following values:
895 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
896 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
897 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)898 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
899 {
900 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
901 }
902
903 /**
904 * @brief Set the polarity of an output channel.
905 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
906 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
907 * @param LPTIMx Low-Power Timer instance
908 * @param Channel This parameter can be one of the following values:
909 * @arg @ref LL_LPTIM_CHANNEL_CH1
910 * @arg @ref LL_LPTIM_CHANNEL_CH2
911 * @param Polarity This parameter can be one of the following values:
912 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
913 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
914 * @retval None
915 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)916 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
917 {
918 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
919 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
920 }
921
922 /**
923 * @brief Get the polarity of an output channel.
924 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
925 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
926 * @param LPTIMx Low-Power Timer instance
927 * @param Channel This parameter can be one of the following values:
928 * @arg @ref LL_LPTIM_CHANNEL_CH1
929 * @arg @ref LL_LPTIM_CHANNEL_CH2
930 * @retval Returned value can be one of the following values:
931 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
932 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
933 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)934 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
935 {
936 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]))) >> \
937 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
938 }
939
940 /**
941 * @brief Set actual prescaler division ratio.
942 * @note This function must be called when the LPTIM instance is disabled.
943 * @note When the LPTIM is configured to be clocked by an internal clock source
944 * and the LPTIM counter is configured to be updated by active edges
945 * detected on the LPTIM external Input1, the internal clock provided to
946 * the LPTIM must be not be prescaled.
947 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
948 * @param LPTIMx Low-Power Timer instance
949 * @param Prescaler This parameter can be one of the following values:
950 * @arg @ref LL_LPTIM_PRESCALER_DIV1
951 * @arg @ref LL_LPTIM_PRESCALER_DIV2
952 * @arg @ref LL_LPTIM_PRESCALER_DIV4
953 * @arg @ref LL_LPTIM_PRESCALER_DIV8
954 * @arg @ref LL_LPTIM_PRESCALER_DIV16
955 * @arg @ref LL_LPTIM_PRESCALER_DIV32
956 * @arg @ref LL_LPTIM_PRESCALER_DIV64
957 * @arg @ref LL_LPTIM_PRESCALER_DIV128
958 * @retval None
959 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)960 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
961 {
962 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
963 }
964
965 /**
966 * @brief Get actual prescaler division ratio.
967 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
968 * @param LPTIMx Low-Power Timer instance
969 * @retval Returned value can be one of the following values:
970 * @arg @ref LL_LPTIM_PRESCALER_DIV1
971 * @arg @ref LL_LPTIM_PRESCALER_DIV2
972 * @arg @ref LL_LPTIM_PRESCALER_DIV4
973 * @arg @ref LL_LPTIM_PRESCALER_DIV8
974 * @arg @ref LL_LPTIM_PRESCALER_DIV16
975 * @arg @ref LL_LPTIM_PRESCALER_DIV32
976 * @arg @ref LL_LPTIM_PRESCALER_DIV64
977 * @arg @ref LL_LPTIM_PRESCALER_DIV128
978 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)979 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
980 {
981 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
982 }
983
984 /**
985 * @brief Set LPTIM input 1 source (default GPIO).
986 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
987 * @param LPTIMx Low-Power Timer instance
988 * @param Src This parameter can be one of the following values:
989 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
990 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 (*)
991 * (*) Value not defined for all devices
992 * @retval None
993 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)994 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
995 {
996 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
997 }
998
999 /**
1000 * @brief Set LPTIM input 2 source (default GPIO).
1001 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1002 * @param LPTIMx Low-Power Timer instance
1003 * @param Src This parameter can be one of the following values:
1004 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1005 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2 (*)
1006 * (*) Value not defined for all devices
1007 * @retval None
1008 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1009 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1010 {
1011 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1012 }
1013
1014 /**
1015 * @brief Set LPTIM input source (default GPIO).
1016 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1017 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1018 * @param LPTIMx Low-Power Timer instance
1019 * @param Src This parameter can be one of the following values:
1020 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1021 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1 (*)
1022 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2 (*)
1023 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1024 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
1025 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
1026 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1027 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 (*)
1028 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 (*)
1029 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1030 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_256
1031 *
1032 * (*) Value not defined in all devices. \n
1033 *
1034 * @retval None
1035 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1036 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1037 {
1038 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1039 }
1040
1041 /**
1042 * @brief Set the polarity of IC channel 1.
1043 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1044 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1045 * @param LPTIMx Low-Power Timer instance
1046 * @param Channel This parameter can be one of the following values:
1047 * @arg @ref LL_LPTIM_CHANNEL_CH1
1048 * @arg @ref LL_LPTIM_CHANNEL_CH2
1049 * @param Polarity This parameter can be one of the following values:
1050 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1051 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1052 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1053 * @retval None
1054 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1055 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1056 {
1057 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1058 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1059 }
1060
1061 /**
1062 * @brief Get the polarity of IC channels.
1063 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1064 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1065 * @param LPTIMx Low-Power Timer instance
1066 * @param Channel This parameter can be one of the following values:
1067 * @arg @ref LL_LPTIM_CHANNEL_CH1
1068 * @arg @ref LL_LPTIM_CHANNEL_CH2
1069 * @retval Returned value can be one of the following values:
1070 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1071 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1072 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1073 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1074 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1075 {
1076 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1077 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1078
1079 }
1080
1081 /**
1082 * @brief Set the filter of IC channels.
1083 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1084 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1085 * @param LPTIMx Low-Power Timer instance
1086 * @param Channel This parameter can be one of the following values:
1087 * @arg @ref LL_LPTIM_CHANNEL_CH1
1088 * @arg @ref LL_LPTIM_CHANNEL_CH2
1089 * @param Filter This parameter can be one of the following values:
1090 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1091 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1092 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1093 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1094 * @retval None
1095 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1096 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1097 {
1098 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1099 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1100 }
1101
1102 /**
1103 * @brief Get the filter of IC channels.
1104 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1105 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1106 * @param LPTIMx Low-Power Timer instance
1107 * @param Channel This parameter can be one of the following values:
1108 * @arg @ref LL_LPTIM_CHANNEL_CH1
1109 * @arg @ref LL_LPTIM_CHANNEL_CH2
1110 * @retval Returned value can be one of the following values:
1111 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1112 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1113 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1114 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1115 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1116 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1117 {
1118 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1119 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1120 }
1121
1122 /**
1123 * @brief Set the prescaler of IC channels.
1124 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1125 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1126 * @param LPTIMx Low-Power Timer instance
1127 * @param Channel This parameter can be one of the following values:
1128 * @arg @ref LL_LPTIM_CHANNEL_CH1
1129 * @arg @ref LL_LPTIM_CHANNEL_CH2
1130 * @param Prescaler This parameter can be one of the following values:
1131 * @arg @ref LL_LPTIM_ICPSC_DIV1
1132 * @arg @ref LL_LPTIM_ICPSC_DIV2
1133 * @arg @ref LL_LPTIM_ICPSC_DIV4
1134 * @arg @ref LL_LPTIM_ICPSC_DIV8
1135 * @retval None
1136 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1137 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1138 {
1139 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1140 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1141 }
1142
1143 /**
1144 * @brief Get the prescaler of IC channels.
1145 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1146 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1147 * @param LPTIMx Low-Power Timer instance
1148 * @param Channel This parameter can be one of the following values:
1149 * @arg @ref LL_LPTIM_CHANNEL_CH1
1150 * @arg @ref LL_LPTIM_CHANNEL_CH2
1151 * @retval Returned value can be one of the following values:
1152 * @arg @ref LL_LPTIM_ICPSC_DIV1
1153 * @arg @ref LL_LPTIM_ICPSC_DIV2
1154 * @arg @ref LL_LPTIM_ICPSC_DIV4
1155 * @arg @ref LL_LPTIM_ICPSC_DIV8
1156 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1157 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1158 {
1159 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1160 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1161 }
1162
1163 /**
1164 * @brief Set the Channel Mode.
1165 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1166 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1167 * @param LPTIMx Low-Power Timer instance
1168 * @param Channel This parameter can be one of the following values:
1169 * @arg @ref LL_LPTIM_CHANNEL_CH1
1170 * @arg @ref LL_LPTIM_CHANNEL_CH2
1171 * @param CCMode This parameter can be one of the following values:
1172 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1173 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1174 * @retval None
1175 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1176 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1177 {
1178 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1179 }
1180
1181 /**
1182 * @brief Get the Channel Mode.
1183 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1184 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1185 * @param LPTIMx Low-Power Timer instance
1186 * @param Channel This parameter can be one of the following values:
1187 * @arg @ref LL_LPTIM_CHANNEL_CH1
1188 * @arg @ref LL_LPTIM_CHANNEL_CH2
1189 * @retval Returned value can be one of the following values:
1190 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1191 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1192 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1193 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1194 {
1195 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1196 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1197 }
1198
1199 /**
1200 * @brief Get captured value for input channel 1.
1201 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1202 * @note The real capture value corresponding to the input capture trigger can be calculated using
1203 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1204 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1205 * @param LPTIMx Low-Power Timer instance
1206 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1207 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1208 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1209 {
1210 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1211 }
1212
1213 /**
1214 * @brief Get captured value for input channel 2.
1215 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1216 * @note The real capture value corresponding to the input capture trigger can be calculated using
1217 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1218 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1219 * @param LPTIMx Low-Power Timer instance
1220 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1221 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1222 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1223 {
1224 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1225 }
1226
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1232 * @{
1233 */
1234
1235 /**
1236 * @brief Enable the timeout function
1237 * @note This function must be called when the LPTIM instance is disabled.
1238 * @note The first trigger event will start the timer, any successive trigger
1239 * event will reset the counter and the timer will restart.
1240 * @note The timeout value corresponds to the compare value; if no trigger
1241 * occurs within the expected time frame, the MCU is waked-up by the
1242 * compare match event.
1243 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1244 * @param LPTIMx Low-Power Timer instance
1245 * @retval None
1246 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1247 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1248 {
1249 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1250 }
1251
1252 /**
1253 * @brief Disable the timeout function
1254 * @note This function must be called when the LPTIM instance is disabled.
1255 * @note A trigger event arriving when the timer is already started will be
1256 * ignored.
1257 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1258 * @param LPTIMx Low-Power Timer instance
1259 * @retval None
1260 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1261 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1262 {
1263 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1264 }
1265
1266 /**
1267 * @brief Indicate whether the timeout function is enabled.
1268 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1269 * @param LPTIMx Low-Power Timer instance
1270 * @retval State of bit (1 or 0).
1271 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1272 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1273 {
1274 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1275 }
1276
1277 /**
1278 * @brief Start the LPTIM counter
1279 * @note This function must be called when the LPTIM instance is disabled.
1280 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1281 * @param LPTIMx Low-Power Timer instance
1282 * @retval None
1283 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1284 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1285 {
1286 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1287 }
1288
1289 /**
1290 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1291 * @note This function must be called when the LPTIM instance is disabled.
1292 * @note An internal clock source must be present when a digital filter is
1293 * required for the trigger.
1294 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1295 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1296 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1297 * @param LPTIMx Low-Power Timer instance
1298 * @param Source This parameter can be one of the following values:
1299 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1300 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1301 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1302 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1303 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1304 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1305 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1306 *
1307 * (*) Value not defined in all devices. \n
1308 *
1309 * @param Filter This parameter can be one of the following values:
1310 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1311 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1312 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1313 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1314 * @param Polarity This parameter can be one of the following values:
1315 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1316 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1317 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1318 * @retval None
1319 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1320 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1321 {
1322 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1323 }
1324
1325 /**
1326 * @brief Get actual external trigger source.
1327 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1328 * @param LPTIMx Low-Power Timer instance
1329 * @retval Returned value can be one of the following values:
1330 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1331 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1332 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1333 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1334 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1335 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1336 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1337 *
1338 * (*) Value not defined in all devices. \n
1339 *
1340 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1341 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1342 {
1343 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1344 }
1345
1346 /**
1347 * @brief Get actual external trigger filter.
1348 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1349 * @param LPTIMx Low-Power Timer instance
1350 * @retval Returned value can be one of the following values:
1351 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1352 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1353 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1354 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1355 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1356 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1357 {
1358 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1359 }
1360
1361 /**
1362 * @brief Get actual external trigger polarity.
1363 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1364 * @param LPTIMx Low-Power Timer instance
1365 * @retval Returned value can be one of the following values:
1366 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1367 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1368 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1369 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1370 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1371 {
1372 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1373 }
1374
1375 /**
1376 * @}
1377 */
1378
1379 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1380 * @{
1381 */
1382
1383 /**
1384 * @brief Set the source of the clock used by the LPTIM instance.
1385 * @note This function must be called when the LPTIM instance is disabled.
1386 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1387 * @param LPTIMx Low-Power Timer instance
1388 * @param ClockSource This parameter can be one of the following values:
1389 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1390 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1391 * @retval None
1392 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1393 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1394 {
1395 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1396 }
1397
1398 /**
1399 * @brief Get actual LPTIM instance clock source.
1400 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1401 * @param LPTIMx Low-Power Timer instance
1402 * @retval Returned value can be one of the following values:
1403 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1404 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1405 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1406 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1407 {
1408 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1409 }
1410
1411 /**
1412 * @brief Configure the active edge or edges used by the counter when
1413 the LPTIM is clocked by an external clock source.
1414 * @note This function must be called when the LPTIM instance is disabled.
1415 * @note When both external clock signal edges are considered active ones,
1416 * the LPTIM must also be clocked by an internal clock source with a
1417 * frequency equal to at least four times the external clock frequency.
1418 * @note An internal clock source must be present when a digital filter is
1419 * required for external clock.
1420 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1421 * CFGR CKPOL LL_LPTIM_ConfigClock
1422 * @param LPTIMx Low-Power Timer instance
1423 * @param ClockFilter This parameter can be one of the following values:
1424 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1425 * @arg @ref LL_LPTIM_CLK_FILTER_2
1426 * @arg @ref LL_LPTIM_CLK_FILTER_4
1427 * @arg @ref LL_LPTIM_CLK_FILTER_8
1428 * @param ClockPolarity This parameter can be one of the following values:
1429 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1430 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1431 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1432 * @retval None
1433 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1434 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1435 {
1436 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1437 }
1438
1439 /**
1440 * @brief Get actual clock polarity
1441 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1442 * @param LPTIMx Low-Power Timer instance
1443 * @retval Returned value can be one of the following values:
1444 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1445 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1446 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1447 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1448 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1449 {
1450 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1451 }
1452
1453 /**
1454 * @brief Get actual clock digital filter
1455 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1456 * @param LPTIMx Low-Power Timer instance
1457 * @retval Returned value can be one of the following values:
1458 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1459 * @arg @ref LL_LPTIM_CLK_FILTER_2
1460 * @arg @ref LL_LPTIM_CLK_FILTER_4
1461 * @arg @ref LL_LPTIM_CLK_FILTER_8
1462 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1463 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1464 {
1465 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1466 }
1467
1468 /**
1469 * @}
1470 */
1471
1472 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1473 * @{
1474 */
1475
1476 /**
1477 * @brief Configure the encoder mode.
1478 * @note This function must be called when the LPTIM instance is disabled.
1479 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1480 * @param LPTIMx Low-Power Timer instance
1481 * @param EncoderMode This parameter can be one of the following values:
1482 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1483 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1484 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1485 * @retval None
1486 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1487 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1488 {
1489 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1490 }
1491
1492 /**
1493 * @brief Get actual encoder mode.
1494 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1495 * @param LPTIMx Low-Power Timer instance
1496 * @retval Returned value can be one of the following values:
1497 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1498 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1499 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1500 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1501 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1502 {
1503 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1504 }
1505
1506 /**
1507 * @brief Enable the encoder mode
1508 * @note This function must be called when the LPTIM instance is disabled.
1509 * @note In this mode the LPTIM instance must be clocked by an internal clock
1510 * source. Also, the prescaler division ratio must be equal to 1.
1511 * @note LPTIM instance must be configured in continuous mode prior enabling
1512 * the encoder mode.
1513 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1514 * @param LPTIMx Low-Power Timer instance
1515 * @retval None
1516 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1517 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1518 {
1519 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1520 }
1521
1522 /**
1523 * @brief Disable the encoder mode
1524 * @note This function must be called when the LPTIM instance is disabled.
1525 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1526 * @param LPTIMx Low-Power Timer instance
1527 * @retval None
1528 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1529 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1530 {
1531 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1532 }
1533
1534 /**
1535 * @brief Indicates whether the LPTIM operates in encoder mode.
1536 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1537 * @param LPTIMx Low-Power Timer instance
1538 * @retval State of bit (1 or 0).
1539 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1540 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1541 {
1542 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1543 }
1544
1545 /**
1546 * @}
1547 */
1548
1549 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1550 * @{
1551 */
1552
1553 /**
1554 * @brief Clear the compare match flag for channel 1 (CC1CF)
1555 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1556 * @param LPTIMx Low-Power Timer instance
1557 * @retval None
1558 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1559 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1560 {
1561 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1562 }
1563
1564 /**
1565 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1566 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1567 * @param LPTIMx Low-Power Timer instance
1568 * @retval State of bit (1 or 0).
1569 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1570 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1571 {
1572 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1573 }
1574
1575 /**
1576 * @brief Clear the compare match flag for channel 2 (CC2CF)
1577 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1578 * @param LPTIMx Low-Power Timer instance
1579 * @retval None
1580 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1581 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1582 {
1583 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1584 }
1585
1586 /**
1587 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1588 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1589 * @param LPTIMx Low-Power Timer instance
1590 * @retval State of bit (1 or 0).
1591 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1592 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1593 {
1594 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1595 }
1596
1597 /**
1598 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1599 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1600 * @param LPTIMx Low-Power Timer instance
1601 * @retval None
1602 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1603 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1604 {
1605 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1606 }
1607
1608 /**
1609 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1610 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1611 * @param LPTIMx Low-Power Timer instance
1612 * @retval State of bit (1 or 0).
1613 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1614 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1615 {
1616 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1617 }
1618
1619 /**
1620 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1621 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1622 * @param LPTIMx Low-Power Timer instance
1623 * @retval None
1624 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1625 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1626 {
1627 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1628 }
1629
1630 /**
1631 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1632 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1633 * @param LPTIMx Low-Power Timer instance
1634 * @retval State of bit (1 or 0).
1635 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1636 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1637 {
1638 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1639 }
1640
1641 /**
1642 * @brief Clear the autoreload match flag (ARRMCF)
1643 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1644 * @param LPTIMx Low-Power Timer instance
1645 * @retval None
1646 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1647 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1648 {
1649 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1650 }
1651
1652 /**
1653 * @brief Inform application whether a autoreload match interrupt has occurred.
1654 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1655 * @param LPTIMx Low-Power Timer instance
1656 * @retval State of bit (1 or 0).
1657 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1658 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1659 {
1660 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1661 }
1662
1663 /**
1664 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1665 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1666 * @param LPTIMx Low-Power Timer instance
1667 * @retval None
1668 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1669 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1670 {
1671 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1672 }
1673
1674 /**
1675 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1676 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1677 * @param LPTIMx Low-Power Timer instance
1678 * @retval State of bit (1 or 0).
1679 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1680 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1681 {
1682 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1683 }
1684
1685 /**
1686 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1687 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1688 * @param LPTIMx Low-Power Timer instance
1689 * @retval None
1690 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1691 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1692 {
1693 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1694 }
1695
1696 /**
1697 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1698 completed. If so, a new one can be initiated.
1699 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1700 * @param LPTIMx Low-Power Timer instance
1701 * @retval State of bit (1 or 0).
1702 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1703 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1704 {
1705 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1706 }
1707
1708 /**
1709 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1710 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1711 * @param LPTIMx Low-Power Timer instance
1712 * @retval None
1713 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1714 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1715 {
1716 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1717 }
1718
1719 /**
1720 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1721 completed. If so, a new one can be initiated.
1722 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1723 * @param LPTIMx Low-Power Timer instance
1724 * @retval State of bit (1 or 0).
1725 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1726 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1727 {
1728 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1729 }
1730
1731 /**
1732 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1733 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1734 * @param LPTIMx Low-Power Timer instance
1735 * @retval None
1736 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1737 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1738 {
1739 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1740 }
1741
1742 /**
1743 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1744 completed. If so, a new one can be initiated.
1745 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1746 * @param LPTIMx Low-Power Timer instance
1747 * @retval State of bit (1 or 0).
1748 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1749 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1750 {
1751 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1752 }
1753
1754 /**
1755 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1756 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1757 * @param LPTIMx Low-Power Timer instance
1758 * @retval None
1759 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1760 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1761 {
1762 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1763 }
1764
1765 /**
1766 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1767 completed. If so, a new one can be initiated.
1768 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1769 * @param LPTIMx Low-Power Timer instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1772 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1773 {
1774 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1775 }
1776
1777 /**
1778 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1779 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1780 * @param LPTIMx Low-Power Timer instance
1781 * @retval None
1782 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1783 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1784 {
1785 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1786 }
1787
1788 /**
1789 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1790 operates in encoder mode).
1791 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1792 * @param LPTIMx Low-Power Timer instance
1793 * @retval State of bit (1 or 0).
1794 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1795 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1796 {
1797 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1798 }
1799
1800 /**
1801 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1802 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1803 * @param LPTIMx Low-Power Timer instance
1804 * @retval None
1805 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1806 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1807 {
1808 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1809 }
1810
1811 /**
1812 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1813 operates in encoder mode).
1814 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1815 * @param LPTIMx Low-Power Timer instance
1816 * @retval State of bit (1 or 0).
1817 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1818 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1819 {
1820 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1821 }
1822
1823 /**
1824 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1825 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1826 * @param LPTIMx Low-Power Timer instance
1827 * @retval None
1828 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1829 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1830 {
1831 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1832 }
1833
1834 /**
1835 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1836 completed; If so, a new one can be initiated.
1837 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1838 * @param LPTIMx Low-Power Timer instance
1839 * @retval State of bit (1 or 0).
1840 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1841 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1842 {
1843 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1844 }
1845
1846 /**
1847 * @brief Clear the update event flag (UECF).
1848 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1849 * @param LPTIMx Low-Power Timer instance
1850 * @retval None
1851 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1852 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1853 {
1854 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1855 }
1856
1857 /**
1858 * @brief Informs application whether the LPTIMx update event has occurred.
1859 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1860 * @param LPTIMx Low-Power Timer instance
1861 * @retval State of bit (1 or 0).
1862 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1863 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1864 {
1865 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1866 }
1867
1868 /**
1869 * @}
1870 */
1871
1872 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1873 * @{
1874 */
1875 /**
1876 * @brief Enable capture/compare 1 interrupt (CC1IE).
1877 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1878 * @param LPTIMx Low-Power Timer instance
1879 * @retval None
1880 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1881 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1882 {
1883 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1884 }
1885
1886 /**
1887 * @brief Disable capture/compare 1 interrupt (CC1IE).
1888 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1889 * @param LPTIMx Low-Power Timer instance
1890 * @retval None
1891 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1892 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1893 {
1894 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1895 }
1896
1897 /**
1898 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1899 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1900 * @param LPTIMx Low-Power Timer instance
1901 * @retval State of bit (1 or 0).
1902 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1903 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1904 {
1905 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1906 }
1907
1908 /**
1909 * @brief Enable capture/compare 1 interrupt (CC2IE).
1910 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
1911 * @param LPTIMx Low-Power Timer instance
1912 * @retval None
1913 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)1914 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
1915 {
1916 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1917 }
1918
1919 /**
1920 * @brief Disable capture/compare 2 interrupt (CC2IE).
1921 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
1922 * @param LPTIMx Low-Power Timer instance
1923 * @retval None
1924 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)1925 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
1926 {
1927 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1928 }
1929
1930 /**
1931 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
1932 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
1933 * @param LPTIMx Low-Power Timer instance
1934 * @retval State of bit (1 or 0).
1935 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)1936 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
1937 {
1938 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
1939 }
1940
1941 /**
1942 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
1943 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
1944 * @param LPTIMx Low-Power Timer instance
1945 * @retval None
1946 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)1947 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1948 {
1949 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1950 }
1951
1952 /**
1953 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
1954 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
1955 * @param LPTIMx Low-Power Timer instance
1956 * @retval None
1957 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)1958 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1959 {
1960 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1961 }
1962
1963 /**
1964 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
1965 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
1966 * @param LPTIMx Low-Power Timer instance
1967 * @retval State of bit (1 or 0).
1968 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)1969 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
1970 {
1971 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
1972 }
1973
1974 /**
1975 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
1976 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
1977 * @param LPTIMx Low-Power Timer instance
1978 * @retval None
1979 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)1980 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
1981 {
1982 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
1983 }
1984
1985 /**
1986 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
1987 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
1988 * @param LPTIMx Low-Power Timer instance
1989 * @retval None
1990 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)1991 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
1992 {
1993 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
1994 }
1995
1996 /**
1997 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
1998 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
1999 * @param LPTIMx Low-Power Timer instance
2000 * @retval State of bit (1 or 0).
2001 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2002 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2003 {
2004 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2005 }
2006
2007 /**
2008 * @brief Enable autoreload match interrupt (ARRMIE).
2009 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2010 * @param LPTIMx Low-Power Timer instance
2011 * @retval None
2012 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2013 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2014 {
2015 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2016 }
2017
2018 /**
2019 * @brief Disable autoreload match interrupt (ARRMIE).
2020 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2021 * @param LPTIMx Low-Power Timer instance
2022 * @retval None
2023 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2024 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2025 {
2026 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2027 }
2028
2029 /**
2030 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2031 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2032 * @param LPTIMx Low-Power Timer instance
2033 * @retval State of bit (1 or 0).
2034 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2035 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2036 {
2037 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2038 }
2039
2040 /**
2041 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2042 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2043 * @param LPTIMx Low-Power Timer instance
2044 * @retval None
2045 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2046 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2047 {
2048 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2049 }
2050
2051 /**
2052 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2053 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2054 * @param LPTIMx Low-Power Timer instance
2055 * @retval None
2056 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2057 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2058 {
2059 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2060 }
2061
2062 /**
2063 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2064 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2065 * @param LPTIMx Low-Power Timer instance
2066 * @retval State of bit (1 or 0).
2067 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2068 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2069 {
2070 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2071 }
2072
2073 /**
2074 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2075 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2076 * @param LPTIMx Low-Power Timer instance
2077 * @retval None
2078 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2079 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2080 {
2081 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2082 }
2083
2084 /**
2085 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2086 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2087 * @param LPTIMx Low-Power Timer instance
2088 * @retval None
2089 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2090 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2091 {
2092 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2093 }
2094
2095 /**
2096 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2097 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2098 * @param LPTIMx Low-Power Timer instance
2099 * @retval State of bit (1 or 0).
2100 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2101 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2102 {
2103 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2104 }
2105
2106 /**
2107 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2108 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2109 * @param LPTIMx Low-Power Timer instance
2110 * @retval None
2111 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2112 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2113 {
2114 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2115 }
2116
2117 /**
2118 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2119 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2120 * @param LPTIMx Low-Power Timer instance
2121 * @retval None
2122 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2123 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2124 {
2125 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2126 }
2127
2128 /**
2129 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2130 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2131 * @param LPTIMx Low-Power Timer instance
2132 * @retval State of bit (1 or 0).
2133 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2134 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2135 {
2136 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2137 }
2138
2139 /**
2140 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2141 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2142 * @param LPTIMx Low-Power Timer instance
2143 * @retval None
2144 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2145 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2146 {
2147 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2148 }
2149
2150 /**
2151 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2152 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2153 * @param LPTIMx Low-Power Timer instance
2154 * @retval None
2155 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2156 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2157 {
2158 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2159 }
2160
2161 /**
2162 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2163 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2164 * @param LPTIMx Low-Power Timer instance
2165 * @retval State of bit(1 or 0).
2166 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2167 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2168 {
2169 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2170 }
2171
2172 /**
2173 * @brief Enable direction change to up interrupt (UPIE).
2174 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2175 * @param LPTIMx Low-Power Timer instance
2176 * @retval None
2177 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2178 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2179 {
2180 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2181 }
2182
2183 /**
2184 * @brief Disable direction change to up interrupt (UPIE).
2185 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2186 * @param LPTIMx Low-Power Timer instance
2187 * @retval None
2188 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2189 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2190 {
2191 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2192 }
2193
2194 /**
2195 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2196 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2197 * @param LPTIMx Low-Power Timer instance
2198 * @retval State of bit(1 or 0).
2199 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2200 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2201 {
2202 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2203 }
2204
2205 /**
2206 * @brief Enable direction change to down interrupt (DOWNIE).
2207 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2208 * @param LPTIMx Low-Power Timer instance
2209 * @retval None
2210 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2211 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2212 {
2213 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2214 }
2215
2216 /**
2217 * @brief Disable direction change to down interrupt (DOWNIE).
2218 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2219 * @param LPTIMx Low-Power Timer instance
2220 * @retval None
2221 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2222 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2223 {
2224 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2225 }
2226
2227 /**
2228 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2229 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2230 * @param LPTIMx Low-Power Timer instance
2231 * @retval State of bit(1 or 0).
2232 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2233 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2234 {
2235 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2236 }
2237
2238 /**
2239 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2240 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2241 * @param LPTIMx Low-Power Timer instance
2242 * @retval None
2243 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2244 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2245 {
2246 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2247 }
2248
2249 /**
2250 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2251 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2252 * @param LPTIMx Low-Power Timer instance
2253 * @retval None
2254 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2255 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2256 {
2257 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2258 }
2259
2260 /**
2261 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2262 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2263 * @param LPTIMx Low-Power Timer instance
2264 * @retval State of bit(1 or 0).
2265 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2266 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2267 {
2268 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2269 }
2270
2271 /**
2272 * @brief Enable update event interrupt (UEIE).
2273 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2274 * @param LPTIMx Low-Power Timer instance
2275 * @retval None
2276 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2277 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2278 {
2279 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2280 }
2281
2282 /**
2283 * @brief Disable update event interrupt (UEIE).
2284 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2285 * @param LPTIMx Low-Power Timer instance
2286 * @retval None
2287 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2288 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2289 {
2290 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2291 }
2292
2293 /**
2294 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2295 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2296 * @param LPTIMx Low-Power Timer instance
2297 *@ retval State of bit(1 or 0).
2298 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2299 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2300 {
2301 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2302 }
2303 /**
2304 * @}
2305 */
2306
2307
2308 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2309 * @{
2310 */
2311 /**
2312 * @brief Enable update DMA request.
2313 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2314 * @param LPTIMx Low-Power Timer instance
2315 * @retval None
2316 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2317 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2318 {
2319 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2320 }
2321
2322 /**
2323 * @brief Disable update DMA request.
2324 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2325 * @param LPTIMx Low-Power Timer instance
2326 * @retval None
2327 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2328 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2329 {
2330 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2331 }
2332
2333 /**
2334 * @brief Indicates whether the update DMA request is enabled.
2335 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2336 * @param LPTIMx Low-Power Timer instance
2337 * @retval State of bit (1 or 0).
2338 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2339 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2340 {
2341 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2342 }
2343
2344 /**
2345 * @brief Enable capture/compare 1 DMA request (CC1DE).
2346 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2347 * @param LPTIMx Low-Power Timer instance
2348 * @retval None
2349 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2350 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2351 {
2352 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2353 }
2354
2355 /**
2356 * @brief Disable capture/compare 1 DMA request (CC1DE).
2357 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2358 * @param LPTIMx Low-Power Timer instance
2359 * @retval None
2360 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2361 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2362 {
2363 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2364 }
2365
2366 /**
2367 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2368 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2369 * @param LPTIMx Low-Power Timer instance
2370 * @retval State of bit (1 or 0).
2371 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2372 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2373 {
2374 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2375 }
2376
2377 /**
2378 * @brief Enable capture/compare 2 DMA request (CC2DE).
2379 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2380 * @param LPTIMx Low-Power Timer instance
2381 * @retval None
2382 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2383 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2384 {
2385 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2386 }
2387
2388 /**
2389 * @brief Disable capture/compare 2 DMA request (CC2DE).
2390 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2391 * @param LPTIMx Low-Power Timer instance
2392 * @retval None
2393 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2394 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2395 {
2396 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2397 }
2398
2399 /**
2400 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2401 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2402 * @param LPTIMx Low-Power Timer instance
2403 * @retval State of bit (1 or 0).
2404 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2405 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2406 {
2407 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2408 }
2409
2410 /**
2411 * @}
2412 */
2413 /**
2414 * @}
2415 */
2416
2417 /**
2418 * @}
2419 */
2420
2421 #endif /* LPTIM1 || LPTIM2 */
2422
2423 /**
2424 * @}
2425 */
2426
2427 #ifdef __cplusplus
2428 }
2429 #endif
2430
2431 #endif /* STM32WBAxx_LL_LPTIM_H */
2432
