1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SysTick configuration used by LL_mDelay and LL_Init1msTick with
25 HCLK source or LL_Init1msTick_HCLK_Div8 or LL_Init1msTick_LSI or
26 LL_Init1msTick_LSE with external source
27 (+) Low power mode configuration (SCB register of Cortex-MCU)
28 (+) API to access to MCU info (CPUID register)
29 (+) API to enable fault handler (SHCSR accesses)
30 (+) API to enable and disable the MPU secure and non-secure
31 (+) API to configure the region of MPU secure and non-secure
32 (+) API to configure the attributes region of MPU secure and non-secure
33
34 @endverbatim
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32WBAxx_LL_CORTEX_H
39 #define STM32WBAxx_LL_CORTEX_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32wbaxx.h"
47
48 /** @addtogroup STM32WBAxx_LL_Driver
49 * @{
50 */
51
52 /** @defgroup CORTEX_LL CORTEX
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
60 * @{
61 */
62 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
63 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
64 /**
65 * @}
66 */
67
68 /* Private macros ------------------------------------------------------------*/
69 /* Exported types ------------------------------------------------------------*/
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
72 * @{
73 */
74
75 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
76 * @{
77 */
78 #define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as
79 SysTick clock source */
80 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
81 clock source */
82
83 /** Legacy definitions for compatibility purpose
84 @cond 0
85 */
86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL
87 /**
88 @endcond
89 */
90
91 /**
92 * @}
93 */
94
95 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
96 * @{
97 */
98 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
99 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
100 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
101 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
102 /**
103 * @}
104 */
105
106 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
107 * @{
108 */
109 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
110 #define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
111 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
112 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
113 /**
114 * @}
115 */
116
117 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
118 * @{
119 */
120 /* Device memory attributes */
121 #define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */
122 #define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */
123 #define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */
124 #define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */
125
126 /* Normal memory attributes */
127 /* Non-cacheable memory attribute */
128 #define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */
129
130 /* Cacheable memory attributes: combination of cache write policy, transient and allocation */
131 /* - cache write policy */
132 #define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */
133 #define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */
134 /* - transient mode attribute */
135 #define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */
136 #define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */
137 /* - allocation attribute */
138 #define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */
139 #define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */
140 #define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */
141 #define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */
142 /**
143 * @}
144 */
145
146 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
147 * @{
148 */
149 #define LL_MPU_REGION_ENABLE 1U
150 #define LL_MPU_REGION_DISABLE 0U
151 /**
152 * @}
153 */
154
155 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
156 * @{
157 */
158 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */
159 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */
160 /**
161 * @}
162 */
163
164 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
165 * @{
166 */
167 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */
168 #define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */
169 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
175 * @{
176 */
177 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */
178 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */
179 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */
180 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */
181 /**
182 * @}
183 */
184
185 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
186 * @{
187 */
188 #define LL_MPU_REGION_NUMBER0 0U
189 #define LL_MPU_REGION_NUMBER1 1U
190 #define LL_MPU_REGION_NUMBER2 2U
191 #define LL_MPU_REGION_NUMBER3 3U
192 #define LL_MPU_REGION_NUMBER4 4U
193 #define LL_MPU_REGION_NUMBER5 5U
194 #define LL_MPU_REGION_NUMBER6 6U
195 #define LL_MPU_REGION_NUMBER7 7U
196 /**
197 * @}
198 */
199
200 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
201 * @{
202 */
203 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
204 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
205 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
206 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
207 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
208 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
209 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
210 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
211 /**
212 * @}
213 */
214
215 /**
216 * @}
217 */
218
219 /* Exported macro ------------------------------------------------------------*/
220
221 /* Exported functions --------------------------------------------------------*/
222 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
223 * @{
224 */
225
226 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
227 * @brief CORTEX SYSTICK LL module driver
228 * @{
229 */
230
231 /**
232 * @brief This function checks if the Systick counter flag is active or not.
233 * @note It can be used in timeout function on application side.
234 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
235 * @retval State of bit (1 or 0).
236 */
LL_SYSTICK_IsActiveCounterFlag(void)237 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
238 {
239 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
240 }
241
242 /**
243 * @brief Configures the SysTick clock source
244 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
245 * @param Source This parameter can be one of the following values:
246 * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL
247 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
248 * @retval None
249 */
LL_SYSTICK_SetClkSource(uint32_t Source)250 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
251 {
252 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
253 {
254 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
255 }
256 else
257 {
258 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
259 }
260 }
261
262 /**
263 * @brief Get the SysTick clock source
264 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
265 * @retval Returned value can be one of the following values:
266 * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL
267 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
268 */
LL_SYSTICK_GetClkSource(void)269 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
270 {
271 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
272 }
273
274 /**
275 * @brief Enable SysTick exception request
276 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
277 * @retval None
278 */
LL_SYSTICK_EnableIT(void)279 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
280 {
281 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
282 }
283
284 /**
285 * @brief Disable SysTick exception request
286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
287 * @retval None
288 */
LL_SYSTICK_DisableIT(void)289 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
290 {
291 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
292 }
293
294 /**
295 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
297 * @retval State of bit (1 or 0).
298 */
LL_SYSTICK_IsEnabledIT(void)299 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
300 {
301 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
302 }
303
304 /**
305 * @}
306 */
307
308 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
309 * @{
310 */
311
312 /**
313 * @brief Processor uses sleep as its low power mode
314 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
315 * @retval None
316 */
LL_LPM_EnableSleep(void)317 __STATIC_INLINE void LL_LPM_EnableSleep(void)
318 {
319 /* Clear SLEEPDEEP bit of Cortex System Control Register */
320 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
321 }
322
323 /**
324 * @brief Processor uses deep sleep as its low power mode
325 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
326 * @retval None
327 */
LL_LPM_EnableDeepSleep(void)328 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
329 {
330 /* Set SLEEPDEEP bit of Cortex System Control Register */
331 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
332 }
333
334 /**
335 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
336 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
337 * empty main application.
338 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
339 * @retval None
340 */
LL_LPM_EnableSleepOnExit(void)341 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
342 {
343 /* Set SLEEPONEXIT bit of Cortex System Control Register */
344 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
345 }
346
347 /**
348 * @brief Do not sleep when returning to Thread mode.
349 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
350 * @retval None
351 */
LL_LPM_DisableSleepOnExit(void)352 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
353 {
354 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
355 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
356 }
357
358 /**
359 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
360 * processor.
361 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
362 * @retval None
363 */
LL_LPM_EnableEventOnPend(void)364 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
365 {
366 /* Set SEVEONPEND bit of Cortex System Control Register */
367 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
368 }
369
370 /**
371 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
372 * excluded
373 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
374 * @retval None
375 */
LL_LPM_DisableEventOnPend(void)376 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
377 {
378 /* Clear SEVEONPEND bit of Cortex System Control Register */
379 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
380 }
381
382 /**
383 * @}
384 */
385
386 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
387 * @{
388 */
389
390 /**
391 * @brief Enable a fault in System handler control register (SHCSR)
392 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
393 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
394 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
395 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
396 * @param Fault This parameter can be a combination of the following values:
397 * @arg @ref LL_HANDLER_FAULT_USG
398 * @arg @ref LL_HANDLER_FAULT_BUS
399 * @arg @ref LL_HANDLER_FAULT_MEM
400 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
401 *
402 * (*) value applicable in secure when the system implements the security.
403 * @retval None
404 */
LL_HANDLER_EnableFault(uint32_t Fault)405 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
406 {
407 /* Enable the system handler fault */
408 SET_BIT(SCB->SHCSR, Fault);
409 }
410
411 /**
412 * @brief Disable a fault in System handler control register (SHCSR)
413 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
414 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
415 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
416 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
417 * @param Fault This parameter can be a combination of the following values:
418 * @arg @ref LL_HANDLER_FAULT_USG
419 * @arg @ref LL_HANDLER_FAULT_BUS
420 * @arg @ref LL_HANDLER_FAULT_MEM
421 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
422 *
423 * (*) value applicable in secure when the system implements the security.
424 * @retval None
425 */
LL_HANDLER_DisableFault(uint32_t Fault)426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
427 {
428 /* Disable the system handler fault */
429 CLEAR_BIT(SCB->SHCSR, Fault);
430 }
431
432 /**
433 * @}
434 */
435
436 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
437 * @{
438 */
439
440 /**
441 * @brief Get Implementer code
442 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
443 * @retval Value should be equal to 0x41 for ARM
444 */
LL_CPUID_GetImplementer(void)445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
446 {
447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
448 }
449
450 /**
451 * @brief Get Variant number (The r value in the rnpn product revision identifier)
452 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
453 * @retval Value between 0 and 255 (0x0: revision 0)
454 */
LL_CPUID_GetVariant(void)455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
456 {
457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
458 }
459
460 /**
461 * @brief Get Architecture version
462 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
463 * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension")
464 */
LL_CPUID_GetArchitecture(void)465 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
466 {
467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
468 }
469
470 /**
471 * @brief Get Part number
472 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
473 * @retval Value should be equal to 0xD21 for Cortex-M33
474 */
LL_CPUID_GetParNo(void)475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
476 {
477 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
478 }
479
480 /**
481 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
482 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
483 * @retval Value between 0 and 255 (0x1: patch 1)
484 */
LL_CPUID_GetRevision(void)485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
486 {
487 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
488 }
489
490 /**
491 * @}
492 */
493
494 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
495 * @{
496 */
497
498 /**
499 * @brief Enable MPU with input options
500 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
501 * @param MPU_Control This parameter can be one of the following values:
502 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
503 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
504 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
505 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
506 * @retval None
507 */
LL_MPU_Enable(uint32_t MPU_Control)508 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
509 {
510 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
511
512 /* Enable the MPU*/
513 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
514
515 /* Follow ARM recommendation with */
516 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
517 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
518 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
519 }
520
521 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
522 /**
523 * @brief Enable non-secure MPU with input options
524 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
525 * @param MPU_Control This parameter can be one of the following values:
526 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
527 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
528 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
529 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
530 * @retval None
531 */
LL_MPU_Enable_NS(uint32_t MPU_Control)532 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
533 {
534 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
535
536 /* Enable the MPU*/
537 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
538
539 /* Follow ARM recommendation with */
540 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
541 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
542 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
543 }
544 #endif /* __ARM_FEATURE_CMSE */
545
546 /**
547 * @brief Disable MPU
548 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
549 * @retval None
550 */
LL_MPU_Disable(void)551 __STATIC_INLINE void LL_MPU_Disable(void)
552 {
553 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
554
555 /* Disable MPU*/
556 WRITE_REG(MPU->CTRL, 0U);
557
558 /* Follow ARM recommendation with */
559 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
560 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
561 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
562 }
563
564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
565 /**
566 * @brief Disable the non-secure MPU
567 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
568 * @retval None
569 */
LL_MPU_Disable_NS(void)570 __STATIC_INLINE void LL_MPU_Disable_NS(void)
571 {
572 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
573
574 /* Disable MPU*/
575 WRITE_REG(MPU_NS->CTRL, 0U);
576
577 /* Follow ARM recommendation with */
578 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
579 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
580 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
581 }
582 #endif /* __ARM_FEATURE_CMSE */
583
584
585 /**
586 * @brief Check if MPU is enabled or not
587 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
588 * @retval State of bit (1 or 0).
589 */
LL_MPU_IsEnabled(void)590 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
591 {
592 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
593 }
594
595 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
596 /**
597 * @brief Check if non-secure MPU is enabled or not
598 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
599 * @retval State of bit (1 or 0).
600 */
LL_MPU_IsEnabled_NS(void)601 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
602 {
603 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
604 }
605 #endif /* __ARM_FEATURE_CMSE */
606
607 /**
608 * @brief Enable a MPU region
609 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
610 * @param Region This parameter can be one of the following values:
611 * @arg @ref LL_MPU_REGION_NUMBER0
612 * @arg @ref LL_MPU_REGION_NUMBER1
613 * @arg @ref LL_MPU_REGION_NUMBER2
614 * @arg @ref LL_MPU_REGION_NUMBER3
615 * @arg @ref LL_MPU_REGION_NUMBER4
616 * @arg @ref LL_MPU_REGION_NUMBER5
617 * @arg @ref LL_MPU_REGION_NUMBER6
618 * @arg @ref LL_MPU_REGION_NUMBER7
619 * @note cortex-M33 supports 8 secure and 8 non secure regions.
620 * @retval None
621 */
LL_MPU_EnableRegion(uint32_t Region)622 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
623 {
624 /* Set Region number */
625 WRITE_REG(MPU->RNR, Region);
626
627 /* Enable the MPU region */
628 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
629 }
630
631 /**
632 * @brief Check if MPU region is enabled or not
633 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
634 * @param Region This parameter can be one of the following values:
635 * @arg @ref LL_MPU_REGION_NUMBER0
636 * @arg @ref LL_MPU_REGION_NUMBER1
637 * @arg @ref LL_MPU_REGION_NUMBER2
638 * @arg @ref LL_MPU_REGION_NUMBER3
639 * @arg @ref LL_MPU_REGION_NUMBER4
640 * @arg @ref LL_MPU_REGION_NUMBER5
641 * @arg @ref LL_MPU_REGION_NUMBER6
642 * @arg @ref LL_MPU_REGION_NUMBER7
643 * @note cortex-M33 supports 8 secure and 8 non secure regions.
644 * @retval State of bit (1 or 0).
645 */
LL_MPU_IsEnabled_Region(uint32_t Region)646 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
647 {
648 /* Set region index */
649 WRITE_REG(MPU->RNR, Region);
650
651 /* Return MPU region status */
652 return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
653 }
654
655 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
656 /**
657 * @brief Enable a non-secure MPU region
658 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
659 * @param Region This parameter can be one of the following values:
660 * @arg @ref LL_MPU_REGION_NUMBER0
661 * @arg @ref LL_MPU_REGION_NUMBER1
662 * @arg @ref LL_MPU_REGION_NUMBER2
663 * @arg @ref LL_MPU_REGION_NUMBER3
664 * @arg @ref LL_MPU_REGION_NUMBER4
665 * @arg @ref LL_MPU_REGION_NUMBER5
666 * @arg @ref LL_MPU_REGION_NUMBER6
667 * @arg @ref LL_MPU_REGION_NUMBER7
668 * @note cortex-M33 supports 8 secure and 8 non secure regions.
669 * @retval None
670 */
LL_MPU_EnableRegion_NS(uint32_t Region)671 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
672 {
673 /* Set Region number */
674 WRITE_REG(MPU_NS->RNR, Region);
675
676 /* Enable the MPU region */
677 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
678 }
679
680 /**
681 * @brief Check if non-secure MPU region is enabled or not
682 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS
683 * @param Region This parameter can be one of the following values:
684 * @arg @ref LL_MPU_REGION_NUMBER0
685 * @arg @ref LL_MPU_REGION_NUMBER1
686 * @arg @ref LL_MPU_REGION_NUMBER2
687 * @arg @ref LL_MPU_REGION_NUMBER3
688 * @arg @ref LL_MPU_REGION_NUMBER4
689 * @arg @ref LL_MPU_REGION_NUMBER5
690 * @arg @ref LL_MPU_REGION_NUMBER6
691 * @arg @ref LL_MPU_REGION_NUMBER7
692 * @note cortex-M33 supports 8 secure and 8 non secure regions.
693 * @retval State of bit (1 or 0).
694 */
LL_MPU_IsEnabled_Region_NS(uint32_t Region)695 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
696 {
697 /* Set region index */
698 WRITE_REG(MPU_NS->RNR, Region);
699
700 /* Return non-secure MPU region status */
701 return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
702 }
703 #endif /* __ARM_FEATURE_CMSE */
704
705 /**
706 * @brief Disable a MPU region
707 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
708 * MPU_RLAR ENABLE LL_MPU_DisableRegion
709 * @param Region This parameter can be one of the following values:
710 * @arg @ref LL_MPU_REGION_NUMBER0
711 * @arg @ref LL_MPU_REGION_NUMBER1
712 * @arg @ref LL_MPU_REGION_NUMBER2
713 * @arg @ref LL_MPU_REGION_NUMBER3
714 * @arg @ref LL_MPU_REGION_NUMBER4
715 * @arg @ref LL_MPU_REGION_NUMBER5
716 * @arg @ref LL_MPU_REGION_NUMBER6
717 * @arg @ref LL_MPU_REGION_NUMBER7
718 * @note cortex-M33 supports 8 secure and 8 non secure regions.
719 * @retval None
720 */
LL_MPU_DisableRegion(uint32_t Region)721 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
722 {
723 /* Set Region number */
724 WRITE_REG(MPU->RNR, Region);
725
726 /* Disable the MPU region */
727 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
728 }
729
730 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
731 /**
732 * @brief Disable a non-secure MPU region
733 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
734 * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
735 * @param Region This parameter can be one of the following values:
736 * @arg @ref LL_MPU_REGION_NUMBER0
737 * @arg @ref LL_MPU_REGION_NUMBER1
738 * @arg @ref LL_MPU_REGION_NUMBER2
739 * @arg @ref LL_MPU_REGION_NUMBER3
740 * @arg @ref LL_MPU_REGION_NUMBER4
741 * @arg @ref LL_MPU_REGION_NUMBER5
742 * @arg @ref LL_MPU_REGION_NUMBER6
743 * @arg @ref LL_MPU_REGION_NUMBER7
744 * @note cortex-M33 supports 8 secure and 8 non secure regions.
745 * @retval None
746 */
LL_MPU_DisableRegion_NS(uint32_t Region)747 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
748 {
749 /* Set Region number */
750 WRITE_REG(MPU_NS->RNR, Region);
751
752 /* Disable the MPU region */
753 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
754 }
755 #endif /* __ARM_FEATURE_CMSE */
756
757 /**
758 * @brief Configure and enable a MPU region
759 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
760 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
761 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
762 * MPU_RBAR XN LL_MPU_ConfigRegion\n
763 * MPU_RBAR AP LL_MPU_ConfigRegion\n
764 * MPU_RBAR SH LL_MPU_ConfigRegion\n
765 * MPU_RLAR EN LL_MPU_ConfigRegion\n
766 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
767 * @param Region This parameter can be one of the following values:
768 * @arg @ref LL_MPU_REGION_NUMBER0
769 * @arg @ref LL_MPU_REGION_NUMBER1
770 * @arg @ref LL_MPU_REGION_NUMBER2
771 * @arg @ref LL_MPU_REGION_NUMBER3
772 * @arg @ref LL_MPU_REGION_NUMBER4
773 * @arg @ref LL_MPU_REGION_NUMBER5
774 * @arg @ref LL_MPU_REGION_NUMBER6
775 * @arg @ref LL_MPU_REGION_NUMBER7
776 * @param Attributes This parameter can be a combination of the following values:
777 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
778 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
779 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
780 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
781 * or @ref LL_MPU_REGION_ALL_RO
782 * @param AttrIndx This parameter can be one of the following values:
783 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
784 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
785 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
786 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
787 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
788 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
789 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
790 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
791 * @param BaseAddress Value of region base address
792 * @param LimitAddress Value of region limit address
793 * @note cortex-M33 supports 8 secure and 8 non secure regions.
794 * @retval None
795 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)796 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
797 uint32_t LimitAddress)
798 {
799 /* Set region index */
800 WRITE_REG(MPU->RNR, Region);
801
802 /* Set region base address and region access attributes */
803 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
804
805 /* Set region limit address, memory attributes index and enable region */
806 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
807 }
808
809 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
810 /**
811 * @brief Configure and enable a non-secure MPU region
812 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
813 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
814 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
815 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
816 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
817 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
818 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
819 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
820 * @param Region This parameter can be one of the following values:
821 * @arg @ref LL_MPU_REGION_NUMBER0
822 * @arg @ref LL_MPU_REGION_NUMBER1
823 * @arg @ref LL_MPU_REGION_NUMBER2
824 * @arg @ref LL_MPU_REGION_NUMBER3
825 * @arg @ref LL_MPU_REGION_NUMBER4
826 * @arg @ref LL_MPU_REGION_NUMBER5
827 * @arg @ref LL_MPU_REGION_NUMBER6
828 * @arg @ref LL_MPU_REGION_NUMBER7
829 * @param Attributes This parameter can be a combination of the following values:
830 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
831 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
832 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
833 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
834 * or @ref LL_MPU_REGION_ALL_RO
835 * @param AttrIndx This parameter can be one of the following values:
836 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
837 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
838 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
839 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
840 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
841 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
842 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
843 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
844 * @param BaseAddress Value of region base address
845 * @param LimitAddress Value of region limit address
846 * @note cortex-M33 supports 8 secure and 8 non secure regions.
847 * @retval None
848 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)849 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
850 uint32_t BaseAddress, uint32_t LimitAddress)
851 {
852 /* Set Region number */
853 WRITE_REG(MPU_NS->RNR, Region);
854
855 /* Set region base address and region access attributes */
856 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
857
858 /* Set region limit address, memory attributes index and enable region */
859 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
860 }
861 #endif /* __ARM_FEATURE_CMSE */
862
863 /**
864 * @brief Configure a MPU region address range
865 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
866 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
867 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
868 * @param Region This parameter can be one of the following values:
869 * @arg @ref LL_MPU_REGION_NUMBER0
870 * @arg @ref LL_MPU_REGION_NUMBER1
871 * @arg @ref LL_MPU_REGION_NUMBER2
872 * @arg @ref LL_MPU_REGION_NUMBER3
873 * @arg @ref LL_MPU_REGION_NUMBER4
874 * @arg @ref LL_MPU_REGION_NUMBER5
875 * @arg @ref LL_MPU_REGION_NUMBER6
876 * @arg @ref LL_MPU_REGION_NUMBER7
877 * @param BaseAddress Value of region base address
878 * @param LimitAddress Value of region limit address
879 * @note cortex-M33 supports 8 secure and 8 non secure regions.
880 * @retval None
881 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)882 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
883 {
884 /* Set Region number */
885 WRITE_REG(MPU->RNR, Region);
886
887 /* Modify region base address */
888 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
889
890 /* Modify region limit address */
891 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
892 }
893
894 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
895 /**
896 * @brief Configure a non-secure MPU region address range
897 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
898 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
899 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
900 * @param Region This parameter can be one of the following values:
901 * @arg @ref LL_MPU_REGION_NUMBER0
902 * @arg @ref LL_MPU_REGION_NUMBER1
903 * @arg @ref LL_MPU_REGION_NUMBER2
904 * @arg @ref LL_MPU_REGION_NUMBER3
905 * @arg @ref LL_MPU_REGION_NUMBER4
906 * @arg @ref LL_MPU_REGION_NUMBER5
907 * @arg @ref LL_MPU_REGION_NUMBER6
908 * @arg @ref LL_MPU_REGION_NUMBER7
909 * @param BaseAddress Value of region base address
910 * @param LimitAddress Value of region limit address
911 * @note cortex-M33 supports 8 secure and 8 non secure regions.
912 * @retval None
913 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)914 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
915 {
916 /* Set Region number */
917 WRITE_REG(MPU_NS->RNR, Region);
918
919 /* Set base address */
920 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
921
922 /* Set limit address */
923 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
924 }
925 #endif /* __ARM_FEATURE_CMSE */
926
927 /**
928 * @brief Configure a MPU attributes index
929 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
930 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
931 * @param AttIndex This parameter can be one of the following values:
932 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
933 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
934 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
935 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
936 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
937 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
938 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
939 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
940 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
941 * @retval None
942 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)943 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
944 {
945 /* When selected index is in range [0;3] */
946 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
947 {
948 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
949 MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
950 }
951 /* When selected index is in range [4;7] */
952 else
953 {
954 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
955 MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
956 }
957 }
958
959 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
960 /**
961 * @brief Configure a non-secure MPU attributes index
962 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
963 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
964 * @param AttIndex This parameter can be one of the following values:
965 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
966 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
967 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
968 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
969 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
970 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
971 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
972 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
973 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
974 * @retval None
975 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)976 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
977 {
978 /* When selected index is in range [0;3] */
979 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
980 {
981 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
982 MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
983 }
984 /* When selected index is in range [4;7] */
985 else
986 {
987 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
988 MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
989 }
990 }
991 #endif /* __ARM_FEATURE_CMSE */
992
993 /**
994 * @brief Configure a MPU region limit address
995 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
996 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
997 * @param Region This parameter can be one of the following values:
998 * @arg @ref LL_MPU_REGION_NUMBER0
999 * @arg @ref LL_MPU_REGION_NUMBER1
1000 * @arg @ref LL_MPU_REGION_NUMBER2
1001 * @arg @ref LL_MPU_REGION_NUMBER3
1002 * @arg @ref LL_MPU_REGION_NUMBER4
1003 * @arg @ref LL_MPU_REGION_NUMBER5
1004 * @arg @ref LL_MPU_REGION_NUMBER6
1005 * @arg @ref LL_MPU_REGION_NUMBER7
1006 * @param LimitAddress Value of region limit address
1007 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1008 * @retval None
1009 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)1010 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
1011 {
1012 /* Set Region number */
1013 WRITE_REG(MPU->RNR, Region);
1014
1015 /* Set limit address */
1016 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1017 }
1018
1019 /**
1020 * @brief Get a MPU region limit address
1021 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
1022 * @param Region This parameter can be one of the following values:
1023 * @arg @ref LL_MPU_REGION_NUMBER0
1024 * @arg @ref LL_MPU_REGION_NUMBER1
1025 * @arg @ref LL_MPU_REGION_NUMBER2
1026 * @arg @ref LL_MPU_REGION_NUMBER3
1027 * @arg @ref LL_MPU_REGION_NUMBER4
1028 * @arg @ref LL_MPU_REGION_NUMBER5
1029 * @arg @ref LL_MPU_REGION_NUMBER6
1030 * @arg @ref LL_MPU_REGION_NUMBER7
1031 * @retval None
1032 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)1033 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
1034 {
1035 /* Set Region number */
1036 WRITE_REG(MPU->RNR, Region);
1037
1038 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
1039 }
1040
1041 /**
1042 * @brief Configure a MPU region base address
1043 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1044 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
1045 * @param Region This parameter can be one of the following values:
1046 * @arg @ref LL_MPU_REGION_NUMBER0
1047 * @arg @ref LL_MPU_REGION_NUMBER1
1048 * @arg @ref LL_MPU_REGION_NUMBER2
1049 * @arg @ref LL_MPU_REGION_NUMBER3
1050 * @arg @ref LL_MPU_REGION_NUMBER4
1051 * @arg @ref LL_MPU_REGION_NUMBER5
1052 * @arg @ref LL_MPU_REGION_NUMBER6
1053 * @arg @ref LL_MPU_REGION_NUMBER7
1054 * @param BaseAddress Value of region base address
1055 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1056 * @retval None
1057 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1058 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1059 {
1060 /* Set Region number */
1061 WRITE_REG(MPU->RNR, Region);
1062
1063 /* Set base address */
1064 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1065 }
1066
1067 /**
1068 * @brief Get a MPU region base address
1069 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1070 * @param Region This parameter can be one of the following values:
1071 * @arg @ref LL_MPU_REGION_NUMBER0
1072 * @arg @ref LL_MPU_REGION_NUMBER1
1073 * @arg @ref LL_MPU_REGION_NUMBER2
1074 * @arg @ref LL_MPU_REGION_NUMBER3
1075 * @arg @ref LL_MPU_REGION_NUMBER4
1076 * @arg @ref LL_MPU_REGION_NUMBER5
1077 * @arg @ref LL_MPU_REGION_NUMBER6
1078 * @arg @ref LL_MPU_REGION_NUMBER7
1079 * @retval None
1080 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1081 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1082 {
1083 /* Set Region number */
1084 WRITE_REG(MPU->RNR, Region);
1085
1086 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1087 }
1088
1089 /**
1090 * @brief Configure a MPU region access attributes and enable a region
1091 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1092 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1093 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1094 * MPU_RBAR SH LL_MPU_SetRegionAccess\n
1095 * @param Region This parameter can be one of the following values:
1096 * @arg @ref LL_MPU_REGION_NUMBER0
1097 * @arg @ref LL_MPU_REGION_NUMBER1
1098 * @arg @ref LL_MPU_REGION_NUMBER2
1099 * @arg @ref LL_MPU_REGION_NUMBER3
1100 * @arg @ref LL_MPU_REGION_NUMBER4
1101 * @arg @ref LL_MPU_REGION_NUMBER5
1102 * @arg @ref LL_MPU_REGION_NUMBER6
1103 * @arg @ref LL_MPU_REGION_NUMBER7
1104 * @param Attributes This parameter can be a combination of the following values:
1105 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1106 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1107 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1108 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1109 * or @ref LL_MPU_REGION_ALL_RO
1110 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1111 * @retval None
1112 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1113 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1114 {
1115 /* Set Region number */
1116 WRITE_REG(MPU->RNR, Region);
1117
1118 /* Set base address */
1119 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1120 }
1121
1122 /**
1123 * @brief Get a MPU region access attributes
1124 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1125 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1126 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1127 * MPU_RBAR SH LL_MPU_GetRegionAccess\n
1128 * @param Region This parameter can be one of the following values:
1129 * @arg @ref LL_MPU_REGION_NUMBER0
1130 * @arg @ref LL_MPU_REGION_NUMBER1
1131 * @arg @ref LL_MPU_REGION_NUMBER2
1132 * @arg @ref LL_MPU_REGION_NUMBER3
1133 * @arg @ref LL_MPU_REGION_NUMBER4
1134 * @arg @ref LL_MPU_REGION_NUMBER5
1135 * @arg @ref LL_MPU_REGION_NUMBER6
1136 * @arg @ref LL_MPU_REGION_NUMBER7
1137 * @retval None
1138 */
LL_MPU_GetRegionAccess(uint32_t Region)1139 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1140 {
1141 /* Set Region number */
1142 WRITE_REG(MPU->RNR, Region);
1143
1144 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1145 }
1146
1147 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1148 /**
1149 * @brief Configure a non-secure MPU region limit address
1150 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1151 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
1152 * @param Region This parameter can be one of the following values:
1153 * @arg @ref LL_MPU_REGION_NUMBER0
1154 * @arg @ref LL_MPU_REGION_NUMBER1
1155 * @arg @ref LL_MPU_REGION_NUMBER2
1156 * @arg @ref LL_MPU_REGION_NUMBER3
1157 * @arg @ref LL_MPU_REGION_NUMBER4
1158 * @arg @ref LL_MPU_REGION_NUMBER5
1159 * @arg @ref LL_MPU_REGION_NUMBER6
1160 * @arg @ref LL_MPU_REGION_NUMBER7
1161 * @param LimitAddress Value of region limit address
1162 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1163 * @retval None
1164 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1165 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1166 {
1167 /* Set Region number */
1168 WRITE_REG(MPU_NS->RNR, Region);
1169
1170 /* Set limit address */
1171 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1172 }
1173
1174 /**
1175 * @brief Get a non-secure MPU region limit address
1176 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1177 * @param Region This parameter can be one of the following values:
1178 * @arg @ref LL_MPU_REGION_NUMBER0
1179 * @arg @ref LL_MPU_REGION_NUMBER1
1180 * @arg @ref LL_MPU_REGION_NUMBER2
1181 * @arg @ref LL_MPU_REGION_NUMBER3
1182 * @arg @ref LL_MPU_REGION_NUMBER4
1183 * @arg @ref LL_MPU_REGION_NUMBER5
1184 * @arg @ref LL_MPU_REGION_NUMBER6
1185 * @arg @ref LL_MPU_REGION_NUMBER7
1186 * @retval None
1187 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1188 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1189 {
1190 /* Set Region number */
1191 WRITE_REG(MPU_NS->RNR, Region);
1192
1193 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1194 }
1195
1196 /**
1197 * @brief Configure a non-secure MPU region base address
1198 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1199 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
1200 * @param Region This parameter can be one of the following values:
1201 * @arg @ref LL_MPU_REGION_NUMBER0
1202 * @arg @ref LL_MPU_REGION_NUMBER1
1203 * @arg @ref LL_MPU_REGION_NUMBER2
1204 * @arg @ref LL_MPU_REGION_NUMBER3
1205 * @arg @ref LL_MPU_REGION_NUMBER4
1206 * @arg @ref LL_MPU_REGION_NUMBER5
1207 * @arg @ref LL_MPU_REGION_NUMBER6
1208 * @arg @ref LL_MPU_REGION_NUMBER7
1209 * @param BaseAddress Value of region base address
1210 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1211 * @retval None
1212 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1213 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1214 {
1215 /* Set Region number */
1216 WRITE_REG(MPU_NS->RNR, Region);
1217
1218 /* Set base address */
1219 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1220 }
1221
1222 /**
1223 * @brief Get a non-secure MPU region base address
1224 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1225 * @param Region This parameter can be one of the following values:
1226 * @arg @ref LL_MPU_REGION_NUMBER0
1227 * @arg @ref LL_MPU_REGION_NUMBER1
1228 * @arg @ref LL_MPU_REGION_NUMBER2
1229 * @arg @ref LL_MPU_REGION_NUMBER3
1230 * @arg @ref LL_MPU_REGION_NUMBER4
1231 * @arg @ref LL_MPU_REGION_NUMBER5
1232 * @arg @ref LL_MPU_REGION_NUMBER6
1233 * @arg @ref LL_MPU_REGION_NUMBER7
1234 * @retval None
1235 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1236 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1237 {
1238 /* Set Region number */
1239 WRITE_REG(MPU_NS->RNR, Region);
1240
1241 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1242 }
1243
1244 /**
1245 * @brief Configure a non-secure MPU region access attributes and enable a region
1246 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1247 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1248 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1249 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
1250 * @param Region This parameter can be one of the following values:
1251 * @arg @ref LL_MPU_REGION_NUMBER0
1252 * @arg @ref LL_MPU_REGION_NUMBER1
1253 * @arg @ref LL_MPU_REGION_NUMBER2
1254 * @arg @ref LL_MPU_REGION_NUMBER3
1255 * @arg @ref LL_MPU_REGION_NUMBER4
1256 * @arg @ref LL_MPU_REGION_NUMBER5
1257 * @arg @ref LL_MPU_REGION_NUMBER6
1258 * @arg @ref LL_MPU_REGION_NUMBER7
1259 * @param Attributes This parameter can be a combination of the following values:
1260 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1261 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1262 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1263 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1264 * or @ref LL_MPU_REGION_ALL_RO
1265 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1266 * @retval None
1267 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1268 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1269 {
1270 /* Set Region number */
1271 WRITE_REG(MPU_NS->RNR, Region);
1272
1273 /* Set base address Attributes */
1274 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1275 }
1276
1277 /**
1278 * @brief Get a non-secure MPU region access attributes
1279 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1280 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1281 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1282 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
1283 * @param Region This parameter can be one of the following values:
1284 * @arg @ref LL_MPU_REGION_NUMBER0
1285 * @arg @ref LL_MPU_REGION_NUMBER1
1286 * @arg @ref LL_MPU_REGION_NUMBER2
1287 * @arg @ref LL_MPU_REGION_NUMBER3
1288 * @arg @ref LL_MPU_REGION_NUMBER4
1289 * @arg @ref LL_MPU_REGION_NUMBER5
1290 * @arg @ref LL_MPU_REGION_NUMBER6
1291 * @arg @ref LL_MPU_REGION_NUMBER7
1292 * @retval None
1293 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1294 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1295 {
1296 /* Set Region number */
1297 WRITE_REG(MPU_NS->RNR, Region);
1298
1299 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1300 }
1301 #endif /* __ARM_FEATURE_CMSE */
1302
1303 /**
1304 * @}
1305 */
1306
1307 /**
1308 * @}
1309 */
1310
1311 /**
1312 * @}
1313 */
1314
1315 /**
1316 * @}
1317 */
1318
1319 #ifdef __cplusplus
1320 }
1321 #endif
1322
1323 #endif /* STM32WBAxx_LL_CORTEX_H */
1324
