1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_TSC_H 21 #define STM32WBAxx_HAL_TSC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 31 /** @addtogroup STM32WBAxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TSC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TSC_Exported_Types TSC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TSC state structure definition 46 */ 47 typedef enum 48 { 49 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 50 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 51 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 52 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 53 } HAL_TSC_StateTypeDef; 54 55 /** 56 * @brief TSC group status structure definition 57 */ 58 typedef enum 59 { 60 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 61 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 62 } TSC_GroupStatusTypeDef; 63 64 /** 65 * @brief TSC init structure definition 66 */ 67 typedef struct 68 { 69 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 70 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 71 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 72 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 73 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 74 This parameter can be set to ENABLE or DISABLE. */ 75 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 76 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 77 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 78 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 79 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 80 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 81 uint32_t MaxCountValue; /*!< Max count value 82 This parameter can be a value of @ref TSC_MaxCount_Value */ 83 uint32_t IODefaultMode; /*!< IO default mode 84 This parameter can be a value of @ref TSC_IO_Default_Mode */ 85 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 86 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 87 uint32_t AcquisitionMode; /*!< Acquisition mode 88 This parameter can be a value of @ref TSC_Acquisition_Mode */ 89 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 90 This parameter can be set to ENABLE or DISABLE. */ 91 uint32_t ChannelIOs; /*!< Channel IOs mask */ 92 uint32_t ShieldIOs; /*!< Shield IOs mask */ 93 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 94 } TSC_InitTypeDef; 95 96 /** 97 * @brief TSC IOs configuration structure definition 98 */ 99 typedef struct 100 { 101 uint32_t ChannelIOs; /*!< Channel IOs mask */ 102 uint32_t ShieldIOs; /*!< Shield IOs mask */ 103 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 104 } TSC_IOConfigTypeDef; 105 106 /** 107 * @brief TSC handle Structure definition 108 */ 109 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 110 typedef struct __TSC_HandleTypeDef 111 #else 112 typedef struct 113 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 114 { 115 TSC_TypeDef *Instance; /*!< Register base address */ 116 TSC_InitTypeDef Init; /*!< Initialization parameters */ 117 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 118 HAL_LockTypeDef Lock; /*!< Lock feature */ 119 __IO uint32_t ErrorCode; /*!< TSC Error code */ 120 121 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 122 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 123 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 124 125 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 126 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 127 128 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 129 } TSC_HandleTypeDef; 130 131 enum 132 { 133 TSC_GROUP1_IDX = 0x00UL, 134 TSC_GROUP2_IDX, 135 TSC_GROUP3_IDX, 136 TSC_GROUP4_IDX, 137 TSC_GROUP5_IDX, 138 TSC_GROUP6_IDX, 139 #if defined(TSC_IOCCR_G7_IO1) 140 TSC_GROUP7_IDX, 141 #endif /* TSC_IOCCR_G7_IO1 */ 142 #if defined(TSC_IOCCR_G8_IO1) 143 TSC_GROUP8_IDX, 144 #endif /* TSC_IOCCR_G8_IO1 */ 145 TSC_NB_OF_GROUPS 146 }; 147 148 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 149 /** 150 * @brief HAL TSC Callback ID enumeration definition 151 */ 152 typedef enum 153 { 154 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 155 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 156 157 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 158 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 159 160 } HAL_TSC_CallbackIDTypeDef; 161 162 /** 163 * @brief HAL TSC Callback pointer definition 164 */ 165 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 166 167 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 168 169 /** 170 * @} 171 */ 172 173 /* Exported constants --------------------------------------------------------*/ 174 /** @defgroup TSC_Exported_Constants TSC Exported Constants 175 * @{ 176 */ 177 178 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 179 * @brief TSC Error Code definition 180 * @{ 181 */ 182 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 183 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 184 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 185 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 186 /** 187 * @} 188 */ 189 190 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 191 * @{ 192 */ 193 #define TSC_CTPH_1CYCLE 0x00000000UL 194 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 195 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 196 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 197 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 198 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 199 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 200 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 201 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 202 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 203 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 204 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 205 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 206 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 207 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 208 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 209 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 210 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 211 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 212 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 213 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 214 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 215 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 216 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 217 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 218 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 219 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 220 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 221 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 222 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 223 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 224 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 230 * @{ 231 */ 232 #define TSC_CTPL_1CYCLE 0x00000000UL 233 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 234 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 235 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 236 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 237 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 238 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 239 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 240 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 241 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 242 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 243 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 244 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 245 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 246 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 247 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 248 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 249 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 250 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 251 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 252 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 253 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 254 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 255 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 256 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 257 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 258 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 259 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 260 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 261 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 262 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 263 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 264 /** 265 * @} 266 */ 267 268 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 269 * @{ 270 */ 271 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 272 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 278 * @{ 279 */ 280 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 281 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 282 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 283 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 284 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 285 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 286 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 287 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup TSC_MaxCount_Value Max Count Value 293 * @{ 294 */ 295 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 296 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 297 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 298 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 299 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 300 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 301 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 302 /** 303 * @} 304 */ 305 306 /** @defgroup TSC_IO_Default_Mode IO Default Mode 307 * @{ 308 */ 309 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 310 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 311 /** 312 * @} 313 */ 314 315 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 316 * @{ 317 */ 318 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 319 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 325 * @{ 326 */ 327 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 328 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 329 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 330 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 331 when the selected signal is detected on the SYNC input pin) */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup TSC_interrupts_definition Interrupts definition 337 * @{ 338 */ 339 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 340 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup TSC_flags_definition Flags definition 346 * @{ 347 */ 348 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 349 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup TSC_Group_definition Group definition 355 * @{ 356 */ 357 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 358 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 359 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 360 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 361 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 362 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 363 #if defined(TSC_IOCCR_G7_IO1) 364 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 365 #endif /* TSC_IOCCR_G7_IO1 */ 366 #if defined(TSC_IOCCR_G8_IO1) 367 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 368 #endif /* TSC_IOCCR_G8_IO1 */ 369 370 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ 371 372 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 373 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 374 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 375 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 376 377 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 378 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 379 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 380 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 381 382 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 383 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 384 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 385 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 386 387 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 388 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 389 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 390 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 391 392 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 393 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 394 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 395 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 396 397 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 398 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 399 #if defined(TSC_IOCCR_G6_IO3) 400 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 401 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 402 #else 403 #define TSC_GROUP6_IO3 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group6 IO3 not supported */ 404 #define TSC_GROUP6_IO4 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group6 IO4 not supported */ 405 #endif /* TSC_IOCCR_G6_IO3 */ 406 #if defined(TSC_IOCCR_G7_IO1) 407 408 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 409 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 410 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 411 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 412 #else 413 414 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ 415 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ 416 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ 417 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ 418 #endif /* TSC_IOCCR_G7_IO1 */ 419 #if defined(TSC_IOCCR_G8_IO1) 420 421 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 422 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 423 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 424 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 425 #else 426 427 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 428 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 429 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 430 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 431 #endif /* TSC_IOCCR_G8_IO1 */ 432 /** 433 * @} 434 */ 435 436 /** 437 * @} 438 */ 439 440 /* Exported macros -----------------------------------------------------------*/ 441 442 /** @defgroup TSC_Exported_Macros TSC Exported Macros 443 * @{ 444 */ 445 446 /** @brief Reset TSC handle state. 447 * @param __HANDLE__ TSC handle 448 * @retval None 449 */ 450 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 451 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 452 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 453 (__HANDLE__)->MspInitCallback = NULL; \ 454 (__HANDLE__)->MspDeInitCallback = NULL; \ 455 } while(0) 456 #else 457 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 458 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 459 460 /** 461 * @brief Enable the TSC peripheral. 462 * @param __HANDLE__ TSC handle 463 * @retval None 464 */ 465 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 466 467 /** 468 * @brief Disable the TSC peripheral. 469 * @param __HANDLE__ TSC handle 470 * @retval None 471 */ 472 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 473 474 /** 475 * @brief Start acquisition. 476 * @param __HANDLE__ TSC handle 477 * @retval None 478 */ 479 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 480 481 /** 482 * @brief Stop acquisition. 483 * @param __HANDLE__ TSC handle 484 * @retval None 485 */ 486 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 487 488 /** 489 * @brief Set IO default mode to output push-pull low. 490 * @param __HANDLE__ TSC handle 491 * @retval None 492 */ 493 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 494 495 /** 496 * @brief Set IO default mode to input floating. 497 * @param __HANDLE__ TSC handle 498 * @retval None 499 */ 500 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 501 502 /** 503 * @brief Set synchronization polarity to falling edge. 504 * @param __HANDLE__ TSC handle 505 * @retval None 506 */ 507 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 508 509 /** 510 * @brief Set synchronization polarity to rising edge and high level. 511 * @param __HANDLE__ TSC handle 512 * @retval None 513 */ 514 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 515 516 /** 517 * @brief Enable TSC interrupt. 518 * @param __HANDLE__ TSC handle 519 * @param __INTERRUPT__ TSC interrupt 520 * @retval None 521 */ 522 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 523 524 /** 525 * @brief Disable TSC interrupt. 526 * @param __HANDLE__ TSC handle 527 * @param __INTERRUPT__ TSC interrupt 528 * @retval None 529 */ 530 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 531 532 /** @brief Check whether the specified TSC interrupt source is enabled or not. 533 * @param __HANDLE__ TSC Handle 534 * @param __INTERRUPT__ TSC interrupt 535 * @retval SET or RESET 536 */ 537 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 538 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 539 RESET) 540 541 /** 542 * @brief Check whether the specified TSC flag is set or not. 543 * @param __HANDLE__ TSC handle 544 * @param __FLAG__ TSC flag 545 * @retval SET or RESET 546 */ 547 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 548 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 549 550 /** 551 * @brief Clear the TSC's pending flag. 552 * @param __HANDLE__ TSC handle 553 * @param __FLAG__ TSC flag 554 * @retval None 555 */ 556 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 557 558 /** 559 * @brief Enable schmitt trigger hysteresis on a group of IOs. 560 * @param __HANDLE__ TSC handle 561 * @param __GX_IOY_MASK__ IOs mask 562 * @retval None 563 */ 564 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 565 566 /** 567 * @brief Disable schmitt trigger hysteresis on a group of IOs. 568 * @param __HANDLE__ TSC handle 569 * @param __GX_IOY_MASK__ IOs mask 570 * @retval None 571 */ 572 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 573 &= (~(__GX_IOY_MASK__))) 574 575 /** 576 * @brief Open analog switch on a group of IOs. 577 * @param __HANDLE__ TSC handle 578 * @param __GX_IOY_MASK__ IOs mask 579 * @retval None 580 */ 581 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 582 &= (~(__GX_IOY_MASK__))) 583 584 /** 585 * @brief Close analog switch on a group of IOs. 586 * @param __HANDLE__ TSC handle 587 * @param __GX_IOY_MASK__ IOs mask 588 * @retval None 589 */ 590 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 591 592 /** 593 * @brief Enable a group of IOs in channel mode. 594 * @param __HANDLE__ TSC handle 595 * @param __GX_IOY_MASK__ IOs mask 596 * @retval None 597 */ 598 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 599 600 /** 601 * @brief Disable a group of channel IOs. 602 * @param __HANDLE__ TSC handle 603 * @param __GX_IOY_MASK__ IOs mask 604 * @retval None 605 */ 606 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 607 &= (~(__GX_IOY_MASK__))) 608 609 /** 610 * @brief Enable a group of IOs in sampling mode. 611 * @param __HANDLE__ TSC handle 612 * @param __GX_IOY_MASK__ IOs mask 613 * @retval None 614 */ 615 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 616 617 /** 618 * @brief Disable a group of sampling IOs. 619 * @param __HANDLE__ TSC handle 620 * @param __GX_IOY_MASK__ IOs mask 621 * @retval None 622 */ 623 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 624 625 /** 626 * @brief Enable acquisition groups. 627 * @param __HANDLE__ TSC handle 628 * @param __GX_MASK__ Groups mask 629 * @retval None 630 */ 631 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 632 633 /** 634 * @brief Disable acquisition groups. 635 * @param __HANDLE__ TSC handle 636 * @param __GX_MASK__ Groups mask 637 * @retval None 638 */ 639 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 640 641 /** @brief Gets acquisition group status. 642 * @param __HANDLE__ TSC Handle 643 * @param __GX_INDEX__ Group index 644 * @retval SET or RESET 645 */ 646 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 647 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 648 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 649 650 /** 651 * @} 652 */ 653 654 /* Private macros ------------------------------------------------------------*/ 655 656 /** @defgroup TSC_Private_Macros TSC Private Macros 657 * @{ 658 */ 659 660 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 661 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 662 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 663 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 664 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 665 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 666 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 667 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 668 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 669 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 670 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 671 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 672 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 673 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 674 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 675 ((__VALUE__) == TSC_CTPH_16CYCLES)) 676 677 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 678 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 679 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 680 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 681 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 682 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 683 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 684 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 685 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 686 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 687 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 688 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 689 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 690 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 691 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 692 ((__VALUE__) == TSC_CTPL_16CYCLES)) 693 694 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 695 || ((FunctionalState)(__VALUE__) == ENABLE)) 696 697 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 698 699 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 700 701 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 702 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 703 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 704 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 705 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 706 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 707 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 708 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 709 710 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 711 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 712 ((__CTPL__) > TSC_CTPL_2CYCLES))) || \ 713 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 714 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 715 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 716 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 717 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 718 719 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 720 ((__VALUE__) == TSC_MCV_511) || \ 721 ((__VALUE__) == TSC_MCV_1023) || \ 722 ((__VALUE__) == TSC_MCV_2047) || \ 723 ((__VALUE__) == TSC_MCV_4095) || \ 724 ((__VALUE__) == TSC_MCV_8191) || \ 725 ((__VALUE__) == TSC_MCV_16383)) 726 727 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 728 729 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 730 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 731 732 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 733 734 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 735 || ((FunctionalState)(__VALUE__) == ENABLE)) 736 737 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 738 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 739 740 741 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 742 (((__VALUE__) == 0UL) ||\ 743 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 744 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 745 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 746 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 747 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 748 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 749 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 750 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 751 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 752 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 753 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 754 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 755 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 756 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 757 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 758 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 759 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 760 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 761 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 762 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 763 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 764 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 765 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 766 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 767 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 768 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 769 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 770 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 771 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 772 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 773 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 774 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 775 776 /** 777 * @} 778 */ 779 780 /* Exported functions --------------------------------------------------------*/ 781 /** @addtogroup TSC_Exported_Functions 782 * @{ 783 */ 784 785 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 786 * @{ 787 */ 788 /* Initialization and de-initialization functions *****************************/ 789 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 790 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 791 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 792 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 793 794 /* Callbacks Register/UnRegister functions ***********************************/ 795 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 796 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 797 pTSC_CallbackTypeDef pCallback); 798 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 799 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 800 /** 801 * @} 802 */ 803 804 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 805 * @{ 806 */ 807 /* IO operation functions *****************************************************/ 808 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 809 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 810 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 811 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 812 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 813 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 814 uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 815 /** 816 * @} 817 */ 818 819 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 820 * @{ 821 */ 822 /* Peripheral Control functions ***********************************************/ 823 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); 824 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 825 /** 826 * @} 827 */ 828 829 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 830 * @{ 831 */ 832 /* Peripheral State and Error functions ***************************************/ 833 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 834 /** 835 * @} 836 */ 837 838 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 839 * @{ 840 */ 841 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 842 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 843 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 844 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 845 /** 846 * @} 847 */ 848 849 /** 850 * @} 851 */ 852 853 /** 854 * @} 855 */ 856 857 /** 858 * @} 859 */ 860 861 #ifdef __cplusplus 862 } 863 #endif 864 865 #endif /* STM32WBAxx_HAL_TSC_H */ 866
