1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32WBAxx_HAL_CORTEX_H 21 #define __STM32WBAxx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 40 * @{ 41 */ 42 43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 44 * @{ 45 */ 46 typedef struct 47 { 48 uint8_t Enable; /*!< Specifies the status of the region. 49 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 50 uint8_t Number; /*!< Specifies the number of the region to protect. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 52 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 53 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 54 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 55 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 56 uint8_t AccessPermission; /*!< Specifies the region access permission type. 57 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 58 uint8_t DisableExec; /*!< Specifies the instruction access status. 59 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 60 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 61 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 62 } MPU_Region_InitTypeDef; 63 /** 64 * @} 65 */ 66 67 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition 68 * @{ 69 */ 70 typedef struct 71 { 72 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 73 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 74 75 uint8_t Attributes; /*!< Specifies the memory attributes vue. 76 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 77 78 } MPU_Attributes_InitTypeDef; 79 /** 80 * @} 81 */ 82 83 /** 84 * @} 85 */ 86 87 /* Exported constants --------------------------------------------------------*/ 88 89 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 90 * @{ 91 */ 92 93 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 94 * @{ 95 */ 96 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority, 97 4 bits for subpriority */ 98 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority, 99 3 bits for subpriority */ 100 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, 101 2 bits for subpriority */ 102 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, 103 1 bit for subpriority */ 104 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority, 105 0 bit for subpriority */ 106 /** 107 * @} 108 */ 109 110 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 111 * @{ 112 */ 113 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source */ 114 #define SYSTICK_CLKSOURCE_LSI 0x00000001U /*!< LSI clock selected as SysTick clock source */ 115 #define SYSTICK_CLKSOURCE_LSE 0x00000002U /*!< LSE clock selected as SysTick clock source */ 116 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /*!< AHB clock selected as SysTick clock source */ 117 /** 118 * @} 119 */ 120 121 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 122 * @{ 123 */ 124 #define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 125 #define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 126 #define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 127 #define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 128 /** 129 * @} 130 */ 131 132 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 133 * @{ 134 */ 135 #define MPU_REGION_ENABLE 1U /*!< Enable region */ 136 #define MPU_REGION_DISABLE 0U /*!< Disable region */ 137 /** 138 * @} 139 */ 140 141 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 142 * @{ 143 */ 144 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ 145 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ 146 /** 147 * @} 148 */ 149 150 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 151 * @{ 152 */ 153 #define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ 154 #define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ 155 #define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ 156 /** 157 * @} 158 */ 159 160 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 161 * @{ 162 */ 163 #define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ 164 #define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ 165 #define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ 166 #define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ 167 /** 168 * @} 169 */ 170 171 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 172 * @{ 173 */ 174 #define MPU_REGION_NUMBER0 0U 175 #define MPU_REGION_NUMBER1 1U 176 #define MPU_REGION_NUMBER2 2U 177 #define MPU_REGION_NUMBER3 3U 178 #define MPU_REGION_NUMBER4 4U 179 #define MPU_REGION_NUMBER5 5U 180 #define MPU_REGION_NUMBER6 6U 181 #define MPU_REGION_NUMBER7 7U 182 /** 183 * @} 184 */ 185 186 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 187 * @{ 188 */ 189 #define MPU_ATTRIBUTES_NUMBER0 0U 190 #define MPU_ATTRIBUTES_NUMBER1 1U 191 #define MPU_ATTRIBUTES_NUMBER2 2U 192 #define MPU_ATTRIBUTES_NUMBER3 3U 193 #define MPU_ATTRIBUTES_NUMBER4 4U 194 #define MPU_ATTRIBUTES_NUMBER5 5U 195 #define MPU_ATTRIBUTES_NUMBER6 6U 196 #define MPU_ATTRIBUTES_NUMBER7 7U 197 /** 198 * @} 199 */ 200 201 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 202 * @{ 203 */ 204 /* Device memory attributes */ 205 #define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ 206 #define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ 207 #define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ 208 #define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ 209 210 /* Normal memory attributes */ 211 /* To set with INNER_OUTER() macro for both inner/outer cache attributes */ 212 213 /* Non-cacheable memory attribute */ 214 #define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ 215 216 /* Cacheable memory attributes: combination of cache write policy, transient and allocation */ 217 /* - cache write policy */ 218 #define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ 219 #define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ 220 /* - transient mode attribute */ 221 #define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ 222 #define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ 223 /* - allocation attribute */ 224 #define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ 225 #define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ 226 #define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ 227 #define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ 228 /** 229 * @} 230 */ 231 232 /** 233 * @} 234 */ 235 236 /* Exported macros -----------------------------------------------------------*/ 237 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 238 * @{ 239 */ 240 241 /** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes 242 * @{ 243 */ 244 /* __ATTR__ being a combination of MPU Normal memory attributes */ 245 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 246 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 247 /** 248 * @} 249 */ 250 251 /** 252 * @} 253 */ 254 255 /* Exported functions --------------------------------------------------------*/ 256 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 257 * @{ 258 */ 259 260 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 261 * @brief Initialization and Configuration functions 262 * @{ 263 */ 264 /* Initialization and Configuration functions *****************************/ 265 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 266 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 267 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 268 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 269 void HAL_NVIC_SystemReset(void); 270 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 271 /** 272 * @} 273 */ 274 275 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 276 * @brief Cortex control functions 277 * @{ 278 */ 279 /* Peripheral Control functions ***********************************************/ 280 uint32_t HAL_NVIC_GetPriorityGrouping(void); 281 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); 282 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 283 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 284 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 285 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 286 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 287 uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); 288 void HAL_SYSTICK_IRQHandler(void); 289 void HAL_SYSTICK_Callback(void); 290 291 void HAL_MPU_Enable(uint32_t MPU_Control); 292 void HAL_MPU_Disable(void); 293 void HAL_MPU_EnableRegion(uint32_t RegionNumber); 294 void HAL_MPU_DisableRegion(uint32_t RegionNumber); 295 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); 296 void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); 297 #ifdef MPU_NS 298 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 299 void HAL_MPU_Disable_NS(void); 300 void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); 301 void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); 302 void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); 303 void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); 304 #endif /* MPU_NS */ 305 /** 306 * @} 307 */ 308 309 /** 310 * @} 311 */ 312 313 /* Private types -------------------------------------------------------------*/ 314 /* Private variables ---------------------------------------------------------*/ 315 /* Private constants ---------------------------------------------------------*/ 316 /* Private macros ------------------------------------------------------------*/ 317 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 318 * @{ 319 */ 320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 321 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 322 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 323 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 324 ((GROUP) == NVIC_PRIORITYGROUP_4)) 325 326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY, GROUP) (((0x07U - (GROUP)) < __NVIC_PRIO_BITS) ?\ 327 ((PRIORITY) < (0x1UL << (0x07U - (GROUP)))) :\ 328 ((PRIORITY) < (0x1UL << __NVIC_PRIO_BITS))) 329 330 #define IS_NVIC_SUB_PRIORITY(PRIORITY, GROUP) (((GROUP) < (0x07U - __NVIC_PRIO_BITS)) ?\ 331 ((PRIORITY) < (0x1UL)): \ 332 ((PRIORITY) < (0x1UL << ((GROUP) - (0x07U - __NVIC_PRIO_BITS))))) 333 334 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 335 336 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ 337 ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ 338 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ 339 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 340 341 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 342 ((STATE) == MPU_REGION_DISABLE)) 343 344 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 345 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 346 347 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 348 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 349 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 350 351 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 352 ((TYPE) == MPU_REGION_ALL_RW) || \ 353 ((TYPE) == MPU_REGION_PRIV_RO) || \ 354 ((TYPE) == MPU_REGION_ALL_RO)) 355 356 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 357 ((NUMBER) == MPU_REGION_NUMBER1) || \ 358 ((NUMBER) == MPU_REGION_NUMBER2) || \ 359 ((NUMBER) == MPU_REGION_NUMBER3) || \ 360 ((NUMBER) == MPU_REGION_NUMBER4) || \ 361 ((NUMBER) == MPU_REGION_NUMBER5) || \ 362 ((NUMBER) == MPU_REGION_NUMBER6) || \ 363 ((NUMBER) == MPU_REGION_NUMBER7)) 364 365 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 366 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 367 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 368 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 369 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 370 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 371 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 372 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 373 374 /** 375 * @} 376 */ 377 378 /* Private functions ---------------------------------------------------------*/ 379 380 /** 381 * @} 382 */ 383 384 /** 385 * @} 386 */ 387 388 #ifdef __cplusplus 389 } 390 #endif 391 392 #endif /* __STM32WBAxx_HAL_CORTEX_H */ 393
