1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32WBAxx_HAL_H 22 #define __STM32WBAxx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbaxx_hal_conf.h" 30 31 /** @addtogroup STM32WBAxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup HAL_Exported_Constants HAL Exported Constants 75 * @{ 76 */ 77 78 /** 79 * @brief STM32WBAxx HAL Driver version number 80 */ 81 #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 82 #define __STM32WBAxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ 83 #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ 84 #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 85 #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ 86 |(__STM32WBAxx_HAL_VERSION_SUB1 << 16U)\ 87 |(__STM32WBAxx_HAL_VERSION_SUB2 << 8U )\ 88 |(__STM32WBAxx_HAL_VERSION_RC)) 89 90 /** 91 * @} 92 */ 93 94 /** @defgroup REV_ID device revision ID 95 * @{ 96 */ 97 #define REV_ID_A 0x1000U /*!< STM32WBA_2 rev.A */ 98 #define REV_ID_B 0x2000U /*!< STM32WBA_2 rev.B */ 99 /** 100 * @} 101 */ 102 103 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 104 * @{ 105 */ 106 107 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 108 * @{ 109 */ 110 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 111 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 112 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 113 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 114 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 115 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 116 #define SYSCFG_IT_FPU_ALL (SYSCFG_IT_FPU_IOC|SYSCFG_IT_FPU_DZC|SYSCFG_IT_FPU_UFC|SYSCFG_IT_FPU_OFC|SYSCFG_IT_FPU_IDC|SYSCFG_IT_FPU_IXC) /*!< All */ 117 118 /** 119 * @} 120 */ 121 122 /** @defgroup SYSCFG_Flags_Definition Flags 123 * @{ 124 */ 125 126 #define SYSCFG_FLAG_MCLR SYSCFG_MESR_MCLR /*!< Device memories erase status */ 127 #define SYSCFG_FLAG_IPMEE SYSCFG_MESR_IPMEE /*!< ICACHE and PKA SRAM erase status */ 128 129 /** 130 * @} 131 */ 132 133 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 134 * @{ 135 */ 136 137 /** @brief Fast-mode Plus driving capability on a specific GPIO 138 */ 139 #define SYSCFG_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast-mode Plus on PA6 */ 140 #define SYSCFG_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast-mode Plus on PA7 */ 141 #define SYSCFG_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast-mode Plus on PA15 */ 142 #define SYSCFG_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast-mode Plus on PB3 */ 143 #define SYSCFG_FASTMODEPLUS_ALL (SYSCFG_FASTMODEPLUS_PA6|SYSCFG_FASTMODEPLUS_PA7|SYSCFG_FASTMODEPLUS_PA15|SYSCFG_FASTMODEPLUS_PB3) /*!< All */ 144 145 /** 146 * @} 147 */ 148 149 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 150 * @brief SYSCFG items to set lock on 151 * @{ 152 */ 153 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 154 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 155 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 156 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 157 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 158 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 159 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 160 #else 161 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 162 #endif /* __ARM_FEATURE_CMSE */ 163 /** 164 * @} 165 */ 166 167 #if defined (SYSCFG_SECCFGR_SYSCFGSEC) 168 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 169 * @brief SYSCFG items to configure secure or non-secure attributes on 170 * @{ 171 */ 172 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 173 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 174 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 175 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ 176 /** 177 * @} 178 */ 179 #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ 180 181 /** @defgroup SYSCFG_attributes SYSCFG attributes 182 * @brief SYSCFG secure or non-secure attributes 183 * @{ 184 */ 185 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 186 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 187 /** 188 * @} 189 */ 190 191 /** 192 * @} 193 */ 194 195 /* Exported macros -----------------------------------------------------------*/ 196 197 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 198 * @{ 199 */ 200 201 /** @brief Freeze/Unfreeze Peripherals in Debug mode 202 */ 203 #if defined(DBGMCU_APB1LFZR_DBG_TIM2_STOP) 204 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM2_STOP) 205 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM2_STOP) 206 #endif /* DBGMCU_APB1LFZR_DBG_TIM2_STOP */ 207 208 #if defined(DBGMCU_APB1LFZR_DBG_TIM3_STOP) 209 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM3_STOP) 210 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM3_STOP) 211 #endif /* DBGMCU_APB1LFZR_DBG_TIM3_STOP */ 212 213 #if defined(DBGMCU_APB1LFZR_DBG_WWDG_STOP) 214 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_WWDG_STOP) 215 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_WWDG_STOP) 216 #endif /* DBGMCU_APB1LFZR_DBG_WWDG_STOP */ 217 218 #if defined(DBGMCU_APB1LFZR_DBG_IWDG_STOP) 219 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_IWDG_STOP) 220 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_IWDG_STOP) 221 #endif /* DBGMCU_APB1LFZR_DBG_IWDG_STOP */ 222 223 #if defined(DBGMCU_APB1LFZR_DBG_I2C1_STOP) 224 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_I2C1_STOP) 225 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_I2C1_STOP) 226 #endif /* DBGMCU_APB1LFZR_DBG_I2C1_STOP */ 227 228 #if defined(DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) 229 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1HFZR, DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) 230 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1HFZR, DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) 231 #endif /* DBGMCU_APB1HFZR_DBG_LPTIM2_STOP */ 232 233 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 234 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 235 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 236 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 237 238 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 239 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 240 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 241 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 242 243 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 244 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 245 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 246 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 247 248 #if defined(DBGMCU_APB7FZR_DBG_I2C3_STOP) 249 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_I2C3_STOP) 250 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_I2C3_STOP) 251 #endif /* DBGMCU_APB7FZR_DBG_I2C3_STOP */ 252 253 #if defined(DBGMCU_APB7FZR_DBG_LPTIM1_STOP) 254 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_LPTIM1_STOP) 255 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_LPTIM1_STOP) 256 #endif /* DBGMCU_APB7FZR_DBG_LPTIM1_STOP */ 257 258 #if defined(DBGMCU_APB7FZR_DBG_RTC_STOP) 259 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_RTC_STOP) 260 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_RTC_STOP) 261 #endif /* DBGMCU_APB7FZR_DBG_RTC_STOP */ 262 263 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 264 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 265 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 266 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ 267 268 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 269 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 270 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 271 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ 272 273 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 274 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 275 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 276 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ 277 278 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 279 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 280 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 281 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ 282 283 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 284 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 285 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 286 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ 287 288 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 289 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 290 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 291 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ 292 293 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 294 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 295 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 296 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ 297 298 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 299 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 300 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 301 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ 302 303 /** 304 * @} 305 */ 306 307 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 308 * @{ 309 */ 310 311 /** @brief Floating Point Unit interrupt enable/disable macros 312 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 313 */ 314 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 315 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 316 }while(0) 317 318 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 319 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 320 }while(0) 321 322 /** @brief SYSCFG Break ECC lock. 323 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 324 * @note The selected configuration is locked and can be unlocked only by system reset. 325 */ 326 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 327 328 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 329 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 330 * @note The selected configuration is locked and can be unlocked only by system reset. 331 */ 332 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 333 334 /** @brief SYSCFG Break PVD lock. 335 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in 336 * the PWR_CR2 register. 337 * @note The selected configuration is locked and can be unlocked only by system reset. 338 */ 339 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 340 341 /** @brief SYSCFG Break SRAM2 parity lock. 342 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 343 * @note The selected configuration is locked and can be unlocked by system reset. 344 */ 345 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 346 347 /** @brief Check SYSCFG flag is set or not. 348 * @param __FLAG__ specifies the flag to check. 349 * This parameter can be one of the following values: 350 * @arg @ref SYSCFG_FLAG_MCLR Device memories erase status flag 351 * @arg @ref SYSCFG_FLAG_IPMEE ICACHE and PKA SRAM erase status flag 352 * @retval The new state of __FLAG__ (TRUE or FALSE). 353 */ 354 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (READ_BIT(SYSCFG->MESR, (__FLAG__)) == (__FLAG__)) 355 356 /** @brief Clear SYSCFG flag. 357 * @param __FLAG__ specifies the flag(s) to clear. 358 * This parameter can be any combination of the following values: 359 * @arg @ref SYSCFG_FLAG_MCLR Device memories erase status flag 360 * @arg @ref SYSCFG_FLAG_IPMEE ICACHE and PKA SRAM erase status flag 361 */ 362 #define __HAL_SYSCFG_CLEAR_FLAG(__FLAG__) SET_BIT(SYSCFG->MESR, (__FLAG__)) 363 364 /** @brief Fast-mode Plus driving capability enable/disable macros 365 * @param __FASTMODEPLUS__: This parameter can be a value of : 366 * @arg @ref SYSCFG_FASTMODEPLUS_PA6 Fast-mode Plus driving capability activation on PA6 367 * @arg @ref SYSCFG_FASTMODEPLUS_PA7 Fast-mode Plus driving capability activation on PA7 368 * @arg @ref SYSCFG_FASTMODEPLUS_PA15 Fast-mode Plus driving capability activation on PA15 369 * @arg @ref SYSCFG_FASTMODEPLUS_PB3 Fast-mode Plus driving capability activation on PB3 370 */ 371 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 372 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 373 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 374 }while(0) 375 376 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 377 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 378 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 379 }while(0) 380 381 /** 382 * @} 383 */ 384 385 /* Private macros ------------------------------------------------------------*/ 386 387 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 388 * @{ 389 */ 390 391 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \ 392 (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U)) 393 394 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 395 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 396 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 397 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 398 399 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ 400 (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) 401 402 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 403 404 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 405 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 406 407 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_ALL) != 0x00U) && \ 408 (((__ITEM__) & ~SYSCFG_ALL) == 0x00U)) 409 410 #endif /* __ARM_FEATURE_CMSE */ 411 412 #if defined (SYSCFG_SECCFGR_SYSCFGSEC) 413 #define IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(__ITEM__) (((__ITEM__) == (SYSCFG_CLK)) || \ 414 ((__ITEM__) == (SYSCFG_CLASSB)) || \ 415 ((__ITEM__) == (SYSCFG_FPU))) 416 #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ 417 418 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \ 419 (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U)) 420 421 422 /** 423 * @} 424 */ 425 426 /* Exported functions --------------------------------------------------------*/ 427 428 /** @addtogroup HAL_Exported_Functions 429 * @{ 430 */ 431 432 /** @addtogroup HAL_Exported_Functions_Group1 433 * @{ 434 */ 435 436 /* Initialization and de-initialization functions ******************************/ 437 HAL_StatusTypeDef HAL_Init(void); 438 HAL_StatusTypeDef HAL_DeInit(void); 439 void HAL_MspInit(void); 440 void HAL_MspDeInit(void); 441 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 442 443 /** 444 * @} 445 */ 446 447 /** @addtogroup HAL_Exported_Functions_Group2 448 * @{ 449 */ 450 451 /* Peripheral Control functions ************************************************/ 452 void HAL_IncTick(void); 453 void HAL_Delay(uint32_t Delay); 454 uint32_t HAL_GetTick(void); 455 uint32_t HAL_GetTickPrio(void); 456 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 457 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 458 void HAL_SuspendTick(void); 459 void HAL_ResumeTick(void); 460 uint32_t HAL_GetHalVersion(void); 461 uint32_t HAL_GetREVID(void); 462 uint32_t HAL_GetDEVID(void); 463 uint32_t HAL_GetUIDw0(void); 464 uint32_t HAL_GetUIDw1(void); 465 uint32_t HAL_GetUIDw2(void); 466 467 /** 468 * @} 469 */ 470 471 /** @addtogroup HAL_Exported_Functions_Group3 472 * @{ 473 */ 474 475 /* DBGMCU Peripheral Control functions *****************************************/ 476 void HAL_DBGMCU_EnableDBGStopMode(void); 477 void HAL_DBGMCU_DisableDBGStopMode(void); 478 void HAL_DBGMCU_EnableDBGStandbyMode(void); 479 void HAL_DBGMCU_DisableDBGStandbyMode(void); 480 481 /** 482 * @} 483 */ 484 485 /** @addtogroup HAL_Exported_Functions_Group4 486 * @{ 487 */ 488 489 /* SYSCFG Control functions ****************************************************/ 490 void HAL_SYSCFG_SRAM2Erase(void); 491 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 492 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 493 494 /** 495 * @} 496 */ 497 498 /** @addtogroup HAL_Exported_Functions_Group5 499 * @{ 500 */ 501 502 /* SYSCFG Lock functions ********************************************/ 503 void HAL_SYSCFG_Lock(uint32_t Item); 504 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 505 506 /** 507 * @} 508 */ 509 510 /** @addtogroup HAL_Exported_Functions_Group6 511 * @{ 512 */ 513 514 #if defined (SYSCFG_SECCFGR_SYSCFGSEC) 515 /* SYSCFG Attributes functions ********************************************/ 516 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 517 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 518 #endif /* __ARM_FEATURE_CMSE */ 519 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 520 #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ 521 522 /** 523 * @} 524 */ 525 526 /** 527 * @} 528 */ 529 530 /** 531 * @} 532 */ 533 534 /** 535 * @} 536 */ 537 538 #ifdef __cplusplus 539 } 540 #endif 541 542 #endif /* __STM32WBAxx_HAL_H */ 543
