1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WB0x_LL_TIM_H
21 #define __STM32WB0x_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wb0x.h"
29
30 /** @addtogroup STM32WB0x_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_AF1 register */
122 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
123
124
125 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
126 #define DT_DELAY_1 ((uint8_t)0x7F)
127 #define DT_DELAY_2 ((uint8_t)0x3F)
128 #define DT_DELAY_3 ((uint8_t)0x1F)
129 #define DT_DELAY_4 ((uint8_t)0x1F)
130
131 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
132 #define DT_RANGE_1 ((uint8_t)0x00)
133 #define DT_RANGE_2 ((uint8_t)0x80)
134 #define DT_RANGE_3 ((uint8_t)0xC0)
135 #define DT_RANGE_4 ((uint8_t)0xE0)
136
137 /** Legacy definitions for compatibility purpose
138 @cond 0
139 */
140 /**
141 @endcond
142 */
143
144 /**
145 * @}
146 */
147
148 /* Private macros ------------------------------------------------------------*/
149 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
150 * @{
151 */
152 /** @brief Convert channel id into channel index.
153 * @param __CHANNEL__ This parameter can be one of the following values:
154 * @arg @ref LL_TIM_CHANNEL_CH1
155 * @arg @ref LL_TIM_CHANNEL_CH1N
156 * @arg @ref LL_TIM_CHANNEL_CH2
157 * @arg @ref LL_TIM_CHANNEL_CH2N
158 * @arg @ref LL_TIM_CHANNEL_CH3
159 * @arg @ref LL_TIM_CHANNEL_CH3N
160 * @arg @ref LL_TIM_CHANNEL_CH4
161 * @arg @ref LL_TIM_CHANNEL_CH5
162 * @arg @ref LL_TIM_CHANNEL_CH6
163 * @retval none
164 */
165 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E)
166 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
167 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
173 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
174 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
175 #else
176 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
177 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
181 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E*/
182
183 /** @brief Calculate the deadtime sampling period(in ps).
184 * @param __TIMCLK__ timer input clock frequency (in Hz).
185 * @param __CKD__ This parameter can be one of the following values:
186 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
187 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
188 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
189 * @retval none
190 */
191 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
192 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
193 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
194 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
195 /**
196 * @}
197 */
198
199
200 /* Exported types ------------------------------------------------------------*/
201 #if defined(USE_FULL_LL_DRIVER)
202 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
203 * @{
204 */
205
206 /**
207 * @brief TIM Time Base configuration structure definition.
208 */
209 typedef struct
210 {
211 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
212 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
213
214 This feature can be modified afterwards using unitary function
215 @ref LL_TIM_SetPrescaler().*/
216
217 uint32_t CounterMode; /*!< Specifies the counter mode.
218 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
219
220 This feature can be modified afterwards using unitary function
221 @ref LL_TIM_SetCounterMode().*/
222
223 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
224 Auto-Reload Register at the next update event.
225 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
226 Some timer instances may support 32 bits counters. In that case this parameter must
227 be a number between 0x0000 and 0xFFFFFFFF.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetAutoReload().*/
231
232 uint32_t ClockDivision; /*!< Specifies the clock division.
233 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
234
235 This feature can be modified afterwards using unitary function
236 @ref LL_TIM_SetClockDivision().*/
237
238 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
239 reaches zero, an update event is generated and counting restarts
240 from the RCR value (N).
241 This means in PWM mode that (N+1) corresponds to:
242 - the number of PWM periods in edge-aligned mode
243 - the number of half PWM period in center-aligned mode
244 GP timers: this parameter must be a number between Min_Data = 0x00 and
245 Max_Data = 0xFF.
246 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
247 Max_Data = 0xFFFF.
248
249 This feature can be modified afterwards using unitary function
250 @ref LL_TIM_SetRepetitionCounter().*/
251 } LL_TIM_InitTypeDef;
252
253 /**
254 * @brief TIM Output Compare configuration structure definition.
255 */
256 typedef struct
257 {
258 uint32_t OCMode; /*!< Specifies the output mode.
259 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
260
261 This feature can be modified afterwards using unitary function
262 @ref LL_TIM_OC_SetMode().*/
263
264 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
265 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
266
267 This feature can be modified afterwards using unitary functions
268 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
269
270 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
271 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
272
273 This feature can be modified afterwards using unitary functions
274 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
275
276 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
277 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
278
279 This feature can be modified afterwards using unitary function
280 LL_TIM_OC_SetCompareCHx (x=1..6).*/
281
282 uint32_t OCPolarity; /*!< Specifies the output polarity.
283 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
284
285 This feature can be modified afterwards using unitary function
286 @ref LL_TIM_OC_SetPolarity().*/
287
288 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
289 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
290
291 This feature can be modified afterwards using unitary function
292 @ref LL_TIM_OC_SetPolarity().*/
293
294
295 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
296 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
297
298 This feature can be modified afterwards using unitary function
299 @ref LL_TIM_OC_SetIdleState().*/
300
301 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
302 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
303
304 This feature can be modified afterwards using unitary function
305 @ref LL_TIM_OC_SetIdleState().*/
306 } LL_TIM_OC_InitTypeDef;
307
308 /**
309 * @brief TIM Input Capture configuration structure definition.
310 */
311
312 typedef struct
313 {
314
315 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
316 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
317
318 This feature can be modified afterwards using unitary function
319 @ref LL_TIM_IC_SetPolarity().*/
320
321 uint32_t ICActiveInput; /*!< Specifies the input.
322 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
323
324 This feature can be modified afterwards using unitary function
325 @ref LL_TIM_IC_SetActiveInput().*/
326
327 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
328 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
329
330 This feature can be modified afterwards using unitary function
331 @ref LL_TIM_IC_SetPrescaler().*/
332
333 uint32_t ICFilter; /*!< Specifies the input capture filter.
334 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
335
336 This feature can be modified afterwards using unitary function
337 @ref LL_TIM_IC_SetFilter().*/
338 } LL_TIM_IC_InitTypeDef;
339
340
341 /**
342 * @brief TIM Encoder interface configuration structure definition.
343 */
344 typedef struct
345 {
346 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
347 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
348
349 This feature can be modified afterwards using unitary function
350 @ref LL_TIM_SetEncoderMode().*/
351
352 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
353 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
354
355 This feature can be modified afterwards using unitary function
356 @ref LL_TIM_IC_SetPolarity().*/
357
358 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
359 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
360
361 This feature can be modified afterwards using unitary function
362 @ref LL_TIM_IC_SetActiveInput().*/
363
364 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
365 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
366
367 This feature can be modified afterwards using unitary function
368 @ref LL_TIM_IC_SetPrescaler().*/
369
370 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
371 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
372
373 This feature can be modified afterwards using unitary function
374 @ref LL_TIM_IC_SetFilter().*/
375
376 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
377 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
378
379 This feature can be modified afterwards using unitary function
380 @ref LL_TIM_IC_SetPolarity().*/
381
382 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
383 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
384
385 This feature can be modified afterwards using unitary function
386 @ref LL_TIM_IC_SetActiveInput().*/
387
388 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
389 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
390
391 This feature can be modified afterwards using unitary function
392 @ref LL_TIM_IC_SetPrescaler().*/
393
394 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
395 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
396
397 This feature can be modified afterwards using unitary function
398 @ref LL_TIM_IC_SetFilter().*/
399
400 } LL_TIM_ENCODER_InitTypeDef;
401
402
403 /**
404 * @brief BDTR (Break and Dead Time) structure definition
405 */
406 typedef struct
407 {
408 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
409 This parameter can be a value of @ref TIM_LL_EC_OSSR
410
411 This feature can be modified afterwards using unitary function
412 @ref LL_TIM_SetOffStates()
413
414 @note This bit-field cannot be modified as long as LOCK level 2 has been
415 programmed. */
416
417 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
418 This parameter can be a value of @ref TIM_LL_EC_OSSI
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_SetOffStates()
422
423 @note This bit-field cannot be modified as long as LOCK level 2 has been
424 programmed. */
425
426 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
427 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
428
429 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
430 register has been written, their content is frozen until the next reset.*/
431
432 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
433 switching-on of the outputs.
434 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
435
436 This feature can be modified afterwards using unitary function
437 @ref LL_TIM_OC_SetDeadTime()
438
439 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
440 programmed. */
441
442 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
443 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
444
445 This feature can be modified afterwards using unitary functions
446 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
447
448 @note This bit-field can not be modified as long as LOCK level 1 has been
449 programmed. */
450
451 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
452 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
453
454 This feature can be modified afterwards using unitary function
455 @ref LL_TIM_ConfigBRK()
456
457 @note This bit-field can not be modified as long as LOCK level 1 has been
458 programmed. */
459
460 #if defined(TIM_BDTR_BKF)
461 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
462 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
463
464 This feature can be modified afterwards using unitary function
465 @ref LL_TIM_ConfigBRK()
466
467 @note This bit-field can not be modified as long as LOCK level 1 has been
468 programmed. */
469
470 #endif /* TIM_BDTR_BKF */
471 #if defined(TIM_BDTR_BKBID)
472 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
473 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
474
475 This feature can be modified afterwards using unitary functions
476 @ref LL_TIM_ConfigBRK()
477
478 @note Bidirectional break input is only supported by advanced timers instances.
479
480 @note This bit-field can not be modified as long as LOCK level 1 has been
481 programmed. */
482
483 #endif /*TIM_BDTR_BKBID */
484 #if defined(TIM_BDTR_BK2E)
485 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
486 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
487
488 This feature can be modified afterwards using unitary functions
489 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
490
491 @note This bit-field can not be modified as long as LOCK level 1 has been
492 programmed. */
493
494 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
495 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
496
497 This feature can be modified afterwards using unitary function
498 @ref LL_TIM_ConfigBRK2()
499
500 @note This bit-field can not be modified as long as LOCK level 1 has been
501 programmed. */
502
503 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
504 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
505
506 This feature can be modified afterwards using unitary function
507 @ref LL_TIM_ConfigBRK2()
508
509 @note This bit-field can not be modified as long as LOCK level 1 has been
510 programmed. */
511
512 #endif /* TIM_BDTR_BK2E */
513 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
514 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
515
516 This feature can be modified afterwards using unitary functions
517 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
518
519 @note This bit-field can not be modified as long as LOCK level 1 has been
520 programmed. */
521 } LL_TIM_BDTR_InitTypeDef;
522
523 /**
524 * @}
525 */
526 #endif /* USE_FULL_LL_DRIVER */
527
528 /* Exported constants --------------------------------------------------------*/
529 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
530 * @{
531 */
532
533 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
534 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
535 * @{
536 */
537 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
538 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
539 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
540 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
541 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
542 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
543 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
544 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
545 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
546 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
547 #if defined(TIM_SR_B2IF)
548 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
549 #endif /* TIM_SR_B2IF */
550 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
551 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
552 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
553 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
554 /**
555 * @}
556 */
557
558 #if defined(USE_FULL_LL_DRIVER)
559 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
560 * @{
561 */
562 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
563 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
564 /**
565 * @}
566 */
567 #if defined(TIM_BDTR_BK2E)
568
569 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
570 * @{
571 */
572 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
573 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
574 /**
575 * @}
576 */
577 #endif /* TIM_BDTR_BK2E */
578
579 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
580 * @{
581 */
582 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
583 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
584 /**
585 * @}
586 */
587 #endif /* USE_FULL_LL_DRIVER */
588
589 /** @defgroup TIM_LL_EC_IT IT Defines
590 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
591 * @{
592 */
593 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
594 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
595 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
596 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
597 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
598 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
599 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
600 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
601 /**
602 * @}
603 */
604
605 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
606 * @{
607 */
608 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
609 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
615 * @{
616 */
617 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
618 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
624 * @{
625 */
626 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
627 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
628 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
629 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
630 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
636 * @{
637 */
638 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
639 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
640 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
641 /**
642 * @}
643 */
644
645 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
646 * @{
647 */
648 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
649 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
650 /**
651 * @}
652 */
653
654 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
655 * @{
656 */
657 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
658 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
659 /**
660 * @}
661 */
662
663 #if defined(TIM_DMA_SUPPORT)
664 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
665 * @{
666 */
667 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
668 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
669 /**
670 * @}
671 */
672 #endif /* TIM_DMA_SUPPORT */
673
674 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
675 * @{
676 */
677 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
678 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
679 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
680 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
681 /**
682 * @}
683 */
684
685 /** @defgroup TIM_LL_EC_CHANNEL Channel
686 * @{
687 */
688 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
689 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
690 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
691 #if defined(TIM_CCER_CC2NE)
692 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
693 #endif /* TIM_CCER_CC2NE */
694 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
695 #if defined(TIM_CCER_CC3NE)
696 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
697 #endif /* TIM_CCER_CC3NE */
698 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
699 #if defined(TIM_CCER_CC5E)
700 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
701 #endif /* TIM_CCER_CC5E */
702 #if defined(TIM_CCER_CC6E)
703 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
704 #endif /* TIM_CCER_CC6E */
705 /**
706 * @}
707 */
708
709 #if defined(USE_FULL_LL_DRIVER)
710 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
711 * @{
712 */
713 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
714 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
715 /**
716 * @}
717 */
718 #endif /* USE_FULL_LL_DRIVER */
719
720 /** Legacy definitions for compatibility purpose
721 @cond 0
722 */
723 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
724 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
725 /**
726 @endcond
727 */
728
729 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
730 * @{
731 */
732 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
733 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
734 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
735 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
736 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
737 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
738 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
739 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
740 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
741 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
742 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
743 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
744 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
745 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
746 /**
747 * @}
748 */
749
750 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
751 * @{
752 */
753 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
754 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
755 /**
756 * @}
757 */
758
759 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
760 * @{
761 */
762 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
763 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
764 /**
765 * @}
766 */
767
768 #if defined(TIM_CCR5_CCR5)
769 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
770 * @{
771 */
772 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
773 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
774 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
775 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
776 /**
777 * @}
778 */
779 #endif /* TIM_CCR5_CCR5 */
780
781 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
782 * @{
783 */
784 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
785 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
786 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
792 * @{
793 */
794 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
795 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
796 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
797 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
803 * @{
804 */
805 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
806 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
807 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
808 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
809 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
810 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
811 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
812 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
813 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
814 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
815 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
816 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
817 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
818 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
819 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
820 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
821 /**
822 * @}
823 */
824
825 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
826 * @{
827 */
828 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
829 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
830 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
831 /**
832 * @}
833 */
834
835 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
836 * @{
837 */
838 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
839 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
840 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
841 /**
842 * @}
843 */
844
845 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
846 * @{
847 */
848 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
849 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
850 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
856 * @{
857 */
858 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
859 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
860 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
861 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
862 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
863 /**
864 * @}
865 */
866
867 /** @defgroup TIM_LL_EC_TS Trigger Selection
868 * @{
869 */
870 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
871 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
872 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
873 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
874 /**
875 * @}
876 */
877
878 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
879 * @{
880 */
881 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
882 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
883 /**
884 * @}
885 */
886
887 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
888 * @{
889 */
890 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
891 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
892 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
893 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
894 /**
895 * @}
896 */
897
898 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
899 * @{
900 */
901 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
902 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
903 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
904 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
905 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
906 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
907 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
908 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
909 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
910 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
911 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
912 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
913 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
914 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
915 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
916 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
917 /**
918 * @}
919 */
920
921
922 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
923 * @{
924 */
925 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
926 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
927 /**
928 * @}
929 */
930
931 #if defined(TIM_BDTR_BKF)
932 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
933 * @{
934 */
935 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
936 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
937 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
938 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
939 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
940 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
941 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
942 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
943 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
944 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
945 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
946 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
947 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
948 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
949 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
950 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
951 /**
952 * @}
953 */
954 #endif /* TIM_BDTR_BKF */
955
956 #if defined(TIM_BDTR_BK2P)
957 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
958 * @{
959 */
960 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
961 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
962 /**
963 * @}
964 */
965 #endif /* TIM_BDTR_BK2P */
966
967 #if defined(TIM_BDTR_BK2F)
968 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
969 * @{
970 */
971 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
972 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
973 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
974 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
975 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
976 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
977 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
978 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
979 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
980 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
981 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
982 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
983 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
984 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
985 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
986 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
987 /**
988 * @}
989 */
990 #endif /* TIM_BDTR_BK2F */
991
992 /** @defgroup TIM_LL_EC_OSSI OSSI
993 * @{
994 */
995 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
996 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
997 /**
998 * @}
999 */
1000
1001 /** @defgroup TIM_LL_EC_OSSR OSSR
1002 * @{
1003 */
1004 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1005 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1011 * @{
1012 */
1013 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1014 #if defined(TIM_BDTR_BK2E)
1015 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1016 #endif /* TIM_BDTR_BK2E */
1017 /**
1018 * @}
1019 */
1020
1021 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1022 * @{
1023 */
1024 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1030 * @{
1031 */
1032 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1033 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1034 /**
1035 * @}
1036 */
1037
1038 #if defined(TIM_BDTR_BKBID)
1039 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1040 * @{
1041 */
1042 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1043 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1044 /**
1045 * @}
1046 */
1047
1048 #endif /*TIM_BDTR_BKBID */
1049 #if defined(TIM_DMA_SUPPORT)
1050 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1051 * @{
1052 */
1053 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1054 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1055 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1056 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1057 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1058 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1059 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1060 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1061 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1062 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1063 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1064 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1065 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1066 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1068 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1069 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1070 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1071 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1072 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1073 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1074 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1075 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1076 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1077 /**
1078 * @}
1079 */
1080
1081 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1082 * @{
1083 */
1084 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1085 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1086 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1087 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1088 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1089 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1090 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1091 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1092 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1093 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1094 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1095 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1096 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1097 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1098 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1099 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1100 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1101 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1102 /**
1103 * @}
1104 */
1105 #endif /* TIM_DMA_SUPPORT */
1106
1107 #if defined(TIM17)
1108 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1109 * @{
1110 */
1111 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
1112 #define LL_TIM_TIM17_TI1_RMP_LCO TIM_OR1_TI1_RMP_0 /*!< TIM17_TI1 is connected to LCO */
1113 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_OR1_TI1_RMP_1 /*!< TIM17_TI1 is connected to MCO */
1114 /**
1115 * @}
1116 */
1117 #endif /* TIM17 */
1118
1119 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1120 * @{
1121 */
1122 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1123 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1124 /**
1125 * @}
1126 */
1127
1128
1129 /**
1130 * @}
1131 */
1132
1133 /* Exported macro ------------------------------------------------------------*/
1134 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1135 * @{
1136 */
1137
1138 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1139 * @{
1140 */
1141 /**
1142 * @brief Write a value in TIM register.
1143 * @param __INSTANCE__ TIM Instance
1144 * @param __REG__ Register to be written
1145 * @param __VALUE__ Value to be written in the register
1146 * @retval None
1147 */
1148 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1149
1150 /**
1151 * @brief Read a value in TIM register.
1152 * @param __INSTANCE__ TIM Instance
1153 * @param __REG__ Register to be read
1154 * @retval Register value
1155 */
1156 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1157 /**
1158 * @}
1159 */
1160
1161 /**
1162 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1163 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1164 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1165 * to TIMx_CNT register bit 31)
1166 * @param __CNT__ Counter value
1167 * @retval UIF status bit
1168 */
1169 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1170 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1171
1172 /**
1173 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1174 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1175 * @param __TIMCLK__ timer input clock frequency (in Hz)
1176 * @param __CKD__ This parameter can be one of the following values:
1177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1178 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1179 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1180 * @param __DT__ deadtime duration (in ns)
1181 * @retval DTG[0:7]
1182 */
1183 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1184 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1185 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1186 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1187 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1188 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1189 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1190 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1191 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1192 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1193 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1194 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1195 0U)
1196
1197 /**
1198 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1199 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1200 * @param __TIMCLK__ timer input clock frequency (in Hz)
1201 * @param __CNTCLK__ counter clock frequency (in Hz)
1202 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1203 */
1204 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1205 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1206
1207 /**
1208 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1209 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1210 * @param __TIMCLK__ timer input clock frequency (in Hz)
1211 * @param __PSC__ prescaler
1212 * @param __FREQ__ output signal frequency (in Hz)
1213 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1214 */
1215 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1216 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1217
1218 /**
1219 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1220 * active/inactive delay.
1221 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1222 * @param __TIMCLK__ timer input clock frequency (in Hz)
1223 * @param __PSC__ prescaler
1224 * @param __DELAY__ timer output compare active/inactive delay (in us)
1225 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1226 */
1227 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1228 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1229 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1230
1231 /**
1232 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1233 * (when the timer operates in one pulse mode).
1234 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1235 * @param __TIMCLK__ timer input clock frequency (in Hz)
1236 * @param __PSC__ prescaler
1237 * @param __DELAY__ timer output compare active/inactive delay (in us)
1238 * @param __PULSE__ pulse duration (in us)
1239 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1240 */
1241 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1242 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1243 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1244
1245 /**
1246 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1247 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1248 * @param __ICPSC__ This parameter can be one of the following values:
1249 * @arg @ref LL_TIM_ICPSC_DIV1
1250 * @arg @ref LL_TIM_ICPSC_DIV2
1251 * @arg @ref LL_TIM_ICPSC_DIV4
1252 * @arg @ref LL_TIM_ICPSC_DIV8
1253 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1254 */
1255 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1256 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1257
1258
1259 /**
1260 * @}
1261 */
1262
1263 /* Exported functions --------------------------------------------------------*/
1264 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1265 * @{
1266 */
1267
1268 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1269 * @{
1270 */
1271 /**
1272 * @brief Enable timer counter.
1273 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1274 * @param TIMx Timer instance
1275 * @retval None
1276 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1277 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1278 {
1279 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1280 }
1281
1282 /**
1283 * @brief Disable timer counter.
1284 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1285 * @param TIMx Timer instance
1286 * @retval None
1287 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1288 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1289 {
1290 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1291 }
1292
1293 /**
1294 * @brief Indicates whether the timer counter is enabled.
1295 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1296 * @param TIMx Timer instance
1297 * @retval State of bit (1 or 0).
1298 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1299 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1300 {
1301 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1302 }
1303
1304 /**
1305 * @brief Enable update event generation.
1306 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1307 * @param TIMx Timer instance
1308 * @retval None
1309 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1310 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1311 {
1312 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1313 }
1314
1315 /**
1316 * @brief Disable update event generation.
1317 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1318 * @param TIMx Timer instance
1319 * @retval None
1320 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1321 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1322 {
1323 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1324 }
1325
1326 /**
1327 * @brief Indicates whether update event generation is enabled.
1328 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1329 * @param TIMx Timer instance
1330 * @retval Inverted state of bit (0 or 1).
1331 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1332 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1333 {
1334 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1335 }
1336
1337 /**
1338 * @brief Set update event source
1339 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1340 * generate an update interrupt or DMA request if enabled:
1341 * - Counter overflow/underflow
1342 * - Setting the UG bit
1343 * - Update generation through the slave mode controller
1344 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1345 * overflow/underflow generates an update interrupt or DMA request if enabled.
1346 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1347 * @param TIMx Timer instance
1348 * @param UpdateSource This parameter can be one of the following values:
1349 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1350 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1351 * @retval None
1352 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1353 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1354 {
1355 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1356 }
1357
1358 /**
1359 * @brief Get actual event update source
1360 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1361 * @param TIMx Timer instance
1362 * @retval Returned value can be one of the following values:
1363 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1364 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1365 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1366 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1367 {
1368 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1369 }
1370
1371 /**
1372 * @brief Set one pulse mode (one shot v.s. repetitive).
1373 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1374 * @param TIMx Timer instance
1375 * @param OnePulseMode This parameter can be one of the following values:
1376 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1377 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1378 * @retval None
1379 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1380 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1381 {
1382 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1383 }
1384
1385 /**
1386 * @brief Get actual one pulse mode.
1387 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1388 * @param TIMx Timer instance
1389 * @retval Returned value can be one of the following values:
1390 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1391 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1392 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1393 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1394 {
1395 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1396 }
1397
1398 /**
1399 * @brief Set the timer counter counting mode.
1400 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1401 * check whether or not the counter mode selection feature is supported
1402 * by a timer instance.
1403 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1404 * requires a timer reset to avoid unexpected direction
1405 * due to DIR bit readonly in center aligned mode.
1406 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1407 * CR1 CMS LL_TIM_SetCounterMode
1408 * @param TIMx Timer instance
1409 * @param CounterMode This parameter can be one of the following values:
1410 * @arg @ref LL_TIM_COUNTERMODE_UP
1411 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1412 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1413 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1414 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1415 * @retval None
1416 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1417 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1418 {
1419 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1420 }
1421
1422 /**
1423 * @brief Get actual counter mode.
1424 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1425 * check whether or not the counter mode selection feature is supported
1426 * by a timer instance.
1427 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1428 * CR1 CMS LL_TIM_GetCounterMode
1429 * @param TIMx Timer instance
1430 * @retval Returned value can be one of the following values:
1431 * @arg @ref LL_TIM_COUNTERMODE_UP
1432 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1433 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1434 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1435 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1436 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1437 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1438 {
1439 uint32_t counter_mode;
1440
1441 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1442
1443 if (counter_mode == 0U)
1444 {
1445 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1446 }
1447
1448 return counter_mode;
1449 }
1450
1451 /**
1452 * @brief Enable auto-reload (ARR) preload.
1453 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1454 * @param TIMx Timer instance
1455 * @retval None
1456 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1457 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1458 {
1459 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1460 }
1461
1462 /**
1463 * @brief Disable auto-reload (ARR) preload.
1464 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1465 * @param TIMx Timer instance
1466 * @retval None
1467 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1468 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1469 {
1470 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1471 }
1472
1473 /**
1474 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1475 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1476 * @param TIMx Timer instance
1477 * @retval State of bit (1 or 0).
1478 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1479 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1480 {
1481 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1482 }
1483
1484 /**
1485 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1486 * (when supported) and the digital filters.
1487 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1488 * whether or not the clock division feature is supported by the timer
1489 * instance.
1490 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1491 * @param TIMx Timer instance
1492 * @param ClockDivision This parameter can be one of the following values:
1493 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1494 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1495 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1496 * @retval None
1497 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1498 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1499 {
1500 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1501 }
1502
1503 /**
1504 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1505 * generators (when supported) and the digital filters.
1506 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1507 * whether or not the clock division feature is supported by the timer
1508 * instance.
1509 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1510 * @param TIMx Timer instance
1511 * @retval Returned value can be one of the following values:
1512 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1513 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1514 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1515 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1516 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1517 {
1518 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1519 }
1520
1521 /**
1522 * @brief Set the counter value.
1523 * @rmtoll CNT CNT LL_TIM_SetCounter
1524 * @param TIMx Timer instance
1525 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
1526 * @retval None
1527 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1528 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1529 {
1530 WRITE_REG(TIMx->CNT, Counter);
1531 }
1532
1533 /**
1534 * @brief Get the counter value.
1535 * @rmtoll CNT CNT LL_TIM_GetCounter
1536 * @param TIMx Timer instance
1537 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
1538 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1539 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1540 {
1541 return (uint32_t)(READ_REG(TIMx->CNT));
1542 }
1543
1544 /**
1545 * @brief Get the current direction of the counter
1546 * @rmtoll CR1 DIR LL_TIM_GetDirection
1547 * @param TIMx Timer instance
1548 * @retval Returned value can be one of the following values:
1549 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1550 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1551 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1552 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1553 {
1554 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1555 }
1556
1557 /**
1558 * @brief Set the prescaler value.
1559 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1560 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1561 * prescaler ratio is taken into account at the next update event.
1562 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1563 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1564 * @param TIMx Timer instance
1565 * @param Prescaler between Min_Data=0 and Max_Data=65535
1566 * @retval None
1567 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1568 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1569 {
1570 WRITE_REG(TIMx->PSC, Prescaler);
1571 }
1572
1573 /**
1574 * @brief Get the prescaler value.
1575 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1576 * @param TIMx Timer instance
1577 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1578 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1579 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1580 {
1581 return (uint32_t)(READ_REG(TIMx->PSC));
1582 }
1583
1584 /**
1585 * @brief Set the auto-reload value.
1586 * @note The counter is blocked while the auto-reload value is null.
1587 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1588 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1589 * @param TIMx Timer instance
1590 * @param AutoReload between Min_Data=0 and Max_Data=65535
1591 * @retval None
1592 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1593 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1594 {
1595 WRITE_REG(TIMx->ARR, AutoReload);
1596 }
1597
1598 /**
1599 * @brief Get the auto-reload value.
1600 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1601 * @param TIMx Timer instance
1602 * @retval Auto-reload value
1603 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1604 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1605 {
1606 return (uint32_t)(READ_REG(TIMx->ARR));
1607 }
1608
1609 /**
1610 * @brief Set the repetition counter value.
1611 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1612 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1613 * whether or not a timer instance supports a repetition counter.
1614 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1615 * @param TIMx Timer instance
1616 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1617 * @retval None
1618 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1619 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1620 {
1621 WRITE_REG(TIMx->RCR, RepetitionCounter);
1622 }
1623
1624 /**
1625 * @brief Get the repetition counter value.
1626 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1627 * whether or not a timer instance supports a repetition counter.
1628 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1629 * @param TIMx Timer instance
1630 * @retval Repetition counter value
1631 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1632 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1633 {
1634 return (uint32_t)(READ_REG(TIMx->RCR));
1635 }
1636
1637 /**
1638 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1639 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1640 * in an atomic way.
1641 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1642 * @param TIMx Timer instance
1643 * @retval None
1644 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1645 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1646 {
1647 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1648 }
1649
1650 /**
1651 * @brief Disable update interrupt flag (UIF) remapping.
1652 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1653 * @param TIMx Timer instance
1654 * @retval None
1655 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1656 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1657 {
1658 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1659 }
1660
1661 /**
1662 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1663 * @param Counter Counter value
1664 * @retval State of bit (1 or 0).
1665 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1666 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1667 {
1668 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1669 }
1670
1671 /**
1672 * @}
1673 */
1674
1675 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1676 * @{
1677 */
1678 /**
1679 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1680 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1681 * they are updated only when a commutation event (COM) occurs.
1682 * @note Only on channels that have a complementary output.
1683 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1684 * whether or not a timer instance is able to generate a commutation event.
1685 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1686 * @param TIMx Timer instance
1687 * @retval None
1688 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1689 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1690 {
1691 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1692 }
1693
1694 /**
1695 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1696 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1697 * whether or not a timer instance is able to generate a commutation event.
1698 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1699 * @param TIMx Timer instance
1700 * @retval None
1701 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1702 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1703 {
1704 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1705 }
1706
1707 /**
1708 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1709 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1710 * whether or not a timer instance is able to generate a commutation event.
1711 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1712 * @param TIMx Timer instance
1713 * @param CCUpdateSource This parameter can be one of the following values:
1714 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1715 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1716 * @retval None
1717 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1718 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1719 {
1720 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1721 }
1722
1723 #if defined(TIM_DMA_SUPPORT)
1724 /**
1725 * @brief Set the trigger of the capture/compare DMA request.
1726 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1727 * @param TIMx Timer instance
1728 * @param DMAReqTrigger This parameter can be one of the following values:
1729 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1730 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1731 * @retval None
1732 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1733 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1734 {
1735 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1736 }
1737
1738 /**
1739 * @brief Get actual trigger of the capture/compare DMA request.
1740 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1741 * @param TIMx Timer instance
1742 * @retval Returned value can be one of the following values:
1743 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1744 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1745 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1746 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1747 {
1748 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1749 }
1750 #endif /* TIM_DMA_SUPPORT */
1751
1752 /**
1753 * @brief Set the lock level to freeze the
1754 * configuration of several capture/compare parameters.
1755 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1756 * the lock mechanism is supported by a timer instance.
1757 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1758 * @param TIMx Timer instance
1759 * @param LockLevel This parameter can be one of the following values:
1760 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1761 * @arg @ref LL_TIM_LOCKLEVEL_1
1762 * @arg @ref LL_TIM_LOCKLEVEL_2
1763 * @arg @ref LL_TIM_LOCKLEVEL_3
1764 * @retval None
1765 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1766 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1767 {
1768 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1769 }
1770
1771 /**
1772 * @brief Enable capture/compare channels.
1773 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1774 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1775 * CCER CC2E LL_TIM_CC_EnableChannel\n
1776 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1777 * CCER CC3E LL_TIM_CC_EnableChannel\n
1778 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1779 * CCER CC4E LL_TIM_CC_EnableChannel\n
1780 * CCER CC5E LL_TIM_CC_EnableChannel\n
1781 * CCER CC6E LL_TIM_CC_EnableChannel
1782 * @param TIMx Timer instance
1783 * @param Channels This parameter can be a combination of the following values:
1784 * @arg @ref LL_TIM_CHANNEL_CH1
1785 * @arg @ref LL_TIM_CHANNEL_CH1N
1786 * @arg @ref LL_TIM_CHANNEL_CH2
1787 * @arg @ref LL_TIM_CHANNEL_CH2N
1788 * @arg @ref LL_TIM_CHANNEL_CH3
1789 * @arg @ref LL_TIM_CHANNEL_CH3N
1790 * @arg @ref LL_TIM_CHANNEL_CH4
1791 * @arg @ref LL_TIM_CHANNEL_CH5
1792 * @arg @ref LL_TIM_CHANNEL_CH6
1793 * @retval None
1794 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1795 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1796 {
1797 SET_BIT(TIMx->CCER, Channels);
1798 }
1799
1800 /**
1801 * @brief Disable capture/compare channels.
1802 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1803 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1804 * CCER CC2E LL_TIM_CC_DisableChannel\n
1805 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1806 * CCER CC3E LL_TIM_CC_DisableChannel\n
1807 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1808 * CCER CC4E LL_TIM_CC_DisableChannel\n
1809 * CCER CC5E LL_TIM_CC_DisableChannel\n
1810 * CCER CC6E LL_TIM_CC_DisableChannel
1811 * @param TIMx Timer instance
1812 * @param Channels This parameter can be a combination of the following values:
1813 * @arg @ref LL_TIM_CHANNEL_CH1
1814 * @arg @ref LL_TIM_CHANNEL_CH1N
1815 * @arg @ref LL_TIM_CHANNEL_CH2
1816 * @arg @ref LL_TIM_CHANNEL_CH2N
1817 * @arg @ref LL_TIM_CHANNEL_CH3
1818 * @arg @ref LL_TIM_CHANNEL_CH3N
1819 * @arg @ref LL_TIM_CHANNEL_CH4
1820 * @arg @ref LL_TIM_CHANNEL_CH5
1821 * @arg @ref LL_TIM_CHANNEL_CH6
1822 * @retval None
1823 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1824 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1825 {
1826 CLEAR_BIT(TIMx->CCER, Channels);
1827 }
1828
1829 /**
1830 * @brief Indicate whether channel(s) is(are) enabled.
1831 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1832 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1833 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1834 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1835 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1836 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1837 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1838 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1839 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1840 * @param TIMx Timer instance
1841 * @param Channels This parameter can be a combination of the following values:
1842 * @arg @ref LL_TIM_CHANNEL_CH1
1843 * @arg @ref LL_TIM_CHANNEL_CH1N
1844 * @arg @ref LL_TIM_CHANNEL_CH2
1845 * @arg @ref LL_TIM_CHANNEL_CH2N
1846 * @arg @ref LL_TIM_CHANNEL_CH3
1847 * @arg @ref LL_TIM_CHANNEL_CH3N
1848 * @arg @ref LL_TIM_CHANNEL_CH4
1849 * @arg @ref LL_TIM_CHANNEL_CH5
1850 * @arg @ref LL_TIM_CHANNEL_CH6
1851 * @retval State of bit (1 or 0).
1852 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1853 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1854 {
1855 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @}
1860 */
1861
1862 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1863 * @{
1864 */
1865 /**
1866 * @brief Configure an output channel.
1867 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1868 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1869 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1870 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1871 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1872 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1873 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1874 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1875 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1876 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1877 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1878 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1879 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1880 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1881 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1882 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
1883 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
1884 * CR2 OIS6 LL_TIM_OC_ConfigOutput
1885 * @param TIMx Timer instance
1886 * @param Channel This parameter can be one of the following values:
1887 * @arg @ref LL_TIM_CHANNEL_CH1
1888 * @arg @ref LL_TIM_CHANNEL_CH2
1889 * @arg @ref LL_TIM_CHANNEL_CH3
1890 * @arg @ref LL_TIM_CHANNEL_CH4
1891 * @arg @ref LL_TIM_CHANNEL_CH5
1892 * @arg @ref LL_TIM_CHANNEL_CH6
1893 * @param Configuration This parameter must be a combination of all the following values:
1894 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1895 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1896 * @retval None
1897 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1898 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1899 {
1900 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1901 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1902 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1903 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1904 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1905 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1906 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1907 }
1908
1909 /**
1910 * @brief Define the behavior of the output reference signal OCxREF from which
1911 * OCx and OCxN (when relevant) are derived.
1912 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1913 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1914 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1915 * CCMR2 OC4M LL_TIM_OC_SetMode\n
1916 * CCMR3 OC5M LL_TIM_OC_SetMode\n
1917 * CCMR3 OC6M LL_TIM_OC_SetMode
1918 * @param TIMx Timer instance
1919 * @param Channel This parameter can be one of the following values:
1920 * @arg @ref LL_TIM_CHANNEL_CH1
1921 * @arg @ref LL_TIM_CHANNEL_CH2
1922 * @arg @ref LL_TIM_CHANNEL_CH3
1923 * @arg @ref LL_TIM_CHANNEL_CH4
1924 * @arg @ref LL_TIM_CHANNEL_CH5
1925 * @arg @ref LL_TIM_CHANNEL_CH6
1926 * @param Mode This parameter can be one of the following values:
1927 * @arg @ref LL_TIM_OCMODE_FROZEN
1928 * @arg @ref LL_TIM_OCMODE_ACTIVE
1929 * @arg @ref LL_TIM_OCMODE_INACTIVE
1930 * @arg @ref LL_TIM_OCMODE_TOGGLE
1931 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1932 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1933 * @arg @ref LL_TIM_OCMODE_PWM1
1934 * @arg @ref LL_TIM_OCMODE_PWM2
1935 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
1936 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
1937 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
1938 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
1939 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
1940 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
1941 * @retval None
1942 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1943 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1944 {
1945 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1946 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1947 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1948 }
1949
1950 /**
1951 * @brief Get the output compare mode of an output channel.
1952 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1953 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1954 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1955 * CCMR2 OC4M LL_TIM_OC_GetMode\n
1956 * CCMR3 OC5M LL_TIM_OC_GetMode\n
1957 * CCMR3 OC6M LL_TIM_OC_GetMode
1958 * @param TIMx Timer instance
1959 * @param Channel This parameter can be one of the following values:
1960 * @arg @ref LL_TIM_CHANNEL_CH1
1961 * @arg @ref LL_TIM_CHANNEL_CH2
1962 * @arg @ref LL_TIM_CHANNEL_CH3
1963 * @arg @ref LL_TIM_CHANNEL_CH4
1964 * @arg @ref LL_TIM_CHANNEL_CH5
1965 * @arg @ref LL_TIM_CHANNEL_CH6
1966 * @retval Returned value can be one of the following values:
1967 * @arg @ref LL_TIM_OCMODE_FROZEN
1968 * @arg @ref LL_TIM_OCMODE_ACTIVE
1969 * @arg @ref LL_TIM_OCMODE_INACTIVE
1970 * @arg @ref LL_TIM_OCMODE_TOGGLE
1971 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1972 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1973 * @arg @ref LL_TIM_OCMODE_PWM1
1974 * @arg @ref LL_TIM_OCMODE_PWM2
1975 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
1976 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
1977 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
1978 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
1979 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
1980 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
1981 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)1982 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
1983 {
1984 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1985 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1986 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1987 }
1988
1989 /**
1990 * @brief Set the polarity of an output channel.
1991 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1992 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1993 * CCER CC2P LL_TIM_OC_SetPolarity\n
1994 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1995 * CCER CC3P LL_TIM_OC_SetPolarity\n
1996 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1997 * CCER CC4P LL_TIM_OC_SetPolarity\n
1998 * CCER CC5P LL_TIM_OC_SetPolarity\n
1999 * CCER CC6P LL_TIM_OC_SetPolarity
2000 * @param TIMx Timer instance
2001 * @param Channel This parameter can be one of the following values:
2002 * @arg @ref LL_TIM_CHANNEL_CH1
2003 * @arg @ref LL_TIM_CHANNEL_CH1N
2004 * @arg @ref LL_TIM_CHANNEL_CH2
2005 * @arg @ref LL_TIM_CHANNEL_CH2N
2006 * @arg @ref LL_TIM_CHANNEL_CH3
2007 * @arg @ref LL_TIM_CHANNEL_CH3N
2008 * @arg @ref LL_TIM_CHANNEL_CH4
2009 * @arg @ref LL_TIM_CHANNEL_CH5
2010 * @arg @ref LL_TIM_CHANNEL_CH6
2011 * @param Polarity This parameter can be one of the following values:
2012 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2013 * @arg @ref LL_TIM_OCPOLARITY_LOW
2014 * @retval None
2015 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2016 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2017 {
2018 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2019 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2020 }
2021
2022 /**
2023 * @brief Get the polarity of an output channel.
2024 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2025 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2026 * CCER CC2P LL_TIM_OC_GetPolarity\n
2027 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2028 * CCER CC3P LL_TIM_OC_GetPolarity\n
2029 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2030 * CCER CC4P LL_TIM_OC_GetPolarity\n
2031 * CCER CC5P LL_TIM_OC_GetPolarity\n
2032 * CCER CC6P LL_TIM_OC_GetPolarity
2033 * @param TIMx Timer instance
2034 * @param Channel This parameter can be one of the following values:
2035 * @arg @ref LL_TIM_CHANNEL_CH1
2036 * @arg @ref LL_TIM_CHANNEL_CH1N
2037 * @arg @ref LL_TIM_CHANNEL_CH2
2038 * @arg @ref LL_TIM_CHANNEL_CH2N
2039 * @arg @ref LL_TIM_CHANNEL_CH3
2040 * @arg @ref LL_TIM_CHANNEL_CH3N
2041 * @arg @ref LL_TIM_CHANNEL_CH4
2042 * @arg @ref LL_TIM_CHANNEL_CH5
2043 * @arg @ref LL_TIM_CHANNEL_CH6
2044 * @retval Returned value can be one of the following values:
2045 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2046 * @arg @ref LL_TIM_OCPOLARITY_LOW
2047 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2048 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2049 {
2050 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2051 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2052 }
2053
2054 /**
2055 * @brief Set the IDLE state of an output channel
2056 * @note This function is significant only for the timer instances
2057 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2058 * can be used to check whether or not a timer instance provides
2059 * a break input.
2060 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2061 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2062 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2063 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2064 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2065 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2066 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2067 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2068 * CR2 OIS6 LL_TIM_OC_SetIdleState
2069 * @param TIMx Timer instance
2070 * @param Channel This parameter can be one of the following values:
2071 * @arg @ref LL_TIM_CHANNEL_CH1
2072 * @arg @ref LL_TIM_CHANNEL_CH1N
2073 * @arg @ref LL_TIM_CHANNEL_CH2
2074 * @arg @ref LL_TIM_CHANNEL_CH2N
2075 * @arg @ref LL_TIM_CHANNEL_CH3
2076 * @arg @ref LL_TIM_CHANNEL_CH3N
2077 * @arg @ref LL_TIM_CHANNEL_CH4
2078 * @arg @ref LL_TIM_CHANNEL_CH5
2079 * @arg @ref LL_TIM_CHANNEL_CH6
2080 * @param IdleState This parameter can be one of the following values:
2081 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2082 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2083 * @retval None
2084 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2085 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2086 {
2087 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2088 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2089 }
2090
2091 /**
2092 * @brief Get the IDLE state of an output channel
2093 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2094 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2095 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2096 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2097 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2098 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2099 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2100 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2101 * CR2 OIS6 LL_TIM_OC_GetIdleState
2102 * @param TIMx Timer instance
2103 * @param Channel This parameter can be one of the following values:
2104 * @arg @ref LL_TIM_CHANNEL_CH1
2105 * @arg @ref LL_TIM_CHANNEL_CH1N
2106 * @arg @ref LL_TIM_CHANNEL_CH2
2107 * @arg @ref LL_TIM_CHANNEL_CH2N
2108 * @arg @ref LL_TIM_CHANNEL_CH3
2109 * @arg @ref LL_TIM_CHANNEL_CH3N
2110 * @arg @ref LL_TIM_CHANNEL_CH4
2111 * @arg @ref LL_TIM_CHANNEL_CH5
2112 * @arg @ref LL_TIM_CHANNEL_CH6
2113 * @retval Returned value can be one of the following values:
2114 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2115 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2116 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2117 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2118 {
2119 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2120 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2121 }
2122
2123 /**
2124 * @brief Enable fast mode for the output channel.
2125 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2126 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2127 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2128 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2129 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2130 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2131 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2132 * @param TIMx Timer instance
2133 * @param Channel This parameter can be one of the following values:
2134 * @arg @ref LL_TIM_CHANNEL_CH1
2135 * @arg @ref LL_TIM_CHANNEL_CH2
2136 * @arg @ref LL_TIM_CHANNEL_CH3
2137 * @arg @ref LL_TIM_CHANNEL_CH4
2138 * @arg @ref LL_TIM_CHANNEL_CH5
2139 * @arg @ref LL_TIM_CHANNEL_CH6
2140 * @retval None
2141 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2142 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2143 {
2144 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2145 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2146 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2147
2148 }
2149
2150 /**
2151 * @brief Disable fast mode for the output channel.
2152 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2153 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2154 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2155 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2156 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2157 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2158 * @param TIMx Timer instance
2159 * @param Channel This parameter can be one of the following values:
2160 * @arg @ref LL_TIM_CHANNEL_CH1
2161 * @arg @ref LL_TIM_CHANNEL_CH2
2162 * @arg @ref LL_TIM_CHANNEL_CH3
2163 * @arg @ref LL_TIM_CHANNEL_CH4
2164 * @arg @ref LL_TIM_CHANNEL_CH5
2165 * @arg @ref LL_TIM_CHANNEL_CH6
2166 * @retval None
2167 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2168 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2169 {
2170 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2171 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2172 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2173
2174 }
2175
2176 /**
2177 * @brief Indicates whether fast mode is enabled for the output channel.
2178 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2179 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2180 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2181 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2182 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2183 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2184 * @param TIMx Timer instance
2185 * @param Channel This parameter can be one of the following values:
2186 * @arg @ref LL_TIM_CHANNEL_CH1
2187 * @arg @ref LL_TIM_CHANNEL_CH2
2188 * @arg @ref LL_TIM_CHANNEL_CH3
2189 * @arg @ref LL_TIM_CHANNEL_CH4
2190 * @arg @ref LL_TIM_CHANNEL_CH5
2191 * @arg @ref LL_TIM_CHANNEL_CH6
2192 * @retval State of bit (1 or 0).
2193 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2194 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2195 {
2196 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2197 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2198 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2199 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2200 }
2201
2202 /**
2203 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2204 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2205 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2206 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2207 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2208 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2209 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2210 * @param TIMx Timer instance
2211 * @param Channel This parameter can be one of the following values:
2212 * @arg @ref LL_TIM_CHANNEL_CH1
2213 * @arg @ref LL_TIM_CHANNEL_CH2
2214 * @arg @ref LL_TIM_CHANNEL_CH3
2215 * @arg @ref LL_TIM_CHANNEL_CH4
2216 * @arg @ref LL_TIM_CHANNEL_CH5
2217 * @arg @ref LL_TIM_CHANNEL_CH6
2218 * @retval None
2219 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2220 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2221 {
2222 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2223 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2224 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2225 }
2226
2227 /**
2228 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2229 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2230 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2231 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2232 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2233 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2234 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2235 * @param TIMx Timer instance
2236 * @param Channel This parameter can be one of the following values:
2237 * @arg @ref LL_TIM_CHANNEL_CH1
2238 * @arg @ref LL_TIM_CHANNEL_CH2
2239 * @arg @ref LL_TIM_CHANNEL_CH3
2240 * @arg @ref LL_TIM_CHANNEL_CH4
2241 * @arg @ref LL_TIM_CHANNEL_CH5
2242 * @arg @ref LL_TIM_CHANNEL_CH6
2243 * @retval None
2244 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2245 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2246 {
2247 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2248 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2249 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2250 }
2251
2252 /**
2253 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2254 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2255 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2256 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2257 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2258 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2259 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2260 * @param TIMx Timer instance
2261 * @param Channel This parameter can be one of the following values:
2262 * @arg @ref LL_TIM_CHANNEL_CH1
2263 * @arg @ref LL_TIM_CHANNEL_CH2
2264 * @arg @ref LL_TIM_CHANNEL_CH3
2265 * @arg @ref LL_TIM_CHANNEL_CH4
2266 * @arg @ref LL_TIM_CHANNEL_CH5
2267 * @arg @ref LL_TIM_CHANNEL_CH6
2268 * @retval State of bit (1 or 0).
2269 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2270 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2271 {
2272 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2273 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2274 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2275 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2276 }
2277
2278 /**
2279 * @brief Enable clearing the output channel on an external event.
2280 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2281 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2282 * or not a timer instance can clear the OCxREF signal on an external event.
2283 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2284 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2285 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2286 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2287 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2288 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2289 * @param TIMx Timer instance
2290 * @param Channel This parameter can be one of the following values:
2291 * @arg @ref LL_TIM_CHANNEL_CH1
2292 * @arg @ref LL_TIM_CHANNEL_CH2
2293 * @arg @ref LL_TIM_CHANNEL_CH3
2294 * @arg @ref LL_TIM_CHANNEL_CH4
2295 * @arg @ref LL_TIM_CHANNEL_CH5
2296 * @arg @ref LL_TIM_CHANNEL_CH6
2297 * @retval None
2298 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2299 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2300 {
2301 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2302 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2303 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2304 }
2305
2306 /**
2307 * @brief Disable clearing the output channel on an external event.
2308 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2309 * or not a timer instance can clear the OCxREF signal on an external event.
2310 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2311 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2312 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2313 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2314 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2315 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2316 * @param TIMx Timer instance
2317 * @param Channel This parameter can be one of the following values:
2318 * @arg @ref LL_TIM_CHANNEL_CH1
2319 * @arg @ref LL_TIM_CHANNEL_CH2
2320 * @arg @ref LL_TIM_CHANNEL_CH3
2321 * @arg @ref LL_TIM_CHANNEL_CH4
2322 * @arg @ref LL_TIM_CHANNEL_CH5
2323 * @arg @ref LL_TIM_CHANNEL_CH6
2324 * @retval None
2325 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2326 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2327 {
2328 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2329 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2330 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2331 }
2332
2333 /**
2334 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2335 * @note This function enables clearing the output channel on an external event.
2336 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2337 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2338 * or not a timer instance can clear the OCxREF signal on an external event.
2339 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2340 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2341 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2342 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2343 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2344 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2345 * @param TIMx Timer instance
2346 * @param Channel This parameter can be one of the following values:
2347 * @arg @ref LL_TIM_CHANNEL_CH1
2348 * @arg @ref LL_TIM_CHANNEL_CH2
2349 * @arg @ref LL_TIM_CHANNEL_CH3
2350 * @arg @ref LL_TIM_CHANNEL_CH4
2351 * @arg @ref LL_TIM_CHANNEL_CH5
2352 * @arg @ref LL_TIM_CHANNEL_CH6
2353 * @retval State of bit (1 or 0).
2354 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2355 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2356 {
2357 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2358 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2359 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2360 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2361 }
2362
2363 /**
2364 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2365 * the Ocx and OCxN signals).
2366 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2367 * dead-time insertion feature is supported by a timer instance.
2368 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2369 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2370 * @param TIMx Timer instance
2371 * @param DeadTime between Min_Data=0 and Max_Data=255
2372 * @retval None
2373 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2374 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2375 {
2376 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2377 }
2378
2379 /**
2380 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2381 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2382 * output channel 1 is supported by a timer instance.
2383 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2384 * @param TIMx Timer instance
2385 * @param CompareValue between Min_Data=0 and Max_Data=65535
2386 * @retval None
2387 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2388 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2389 {
2390 WRITE_REG(TIMx->CCR1, CompareValue);
2391 }
2392
2393 /**
2394 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2395 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2396 * output channel 2 is supported by a timer instance.
2397 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2398 * @param TIMx Timer instance
2399 * @param CompareValue between Min_Data=0 and Max_Data=65535
2400 * @retval None
2401 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2402 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2403 {
2404 WRITE_REG(TIMx->CCR2, CompareValue);
2405 }
2406
2407 /**
2408 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2409 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2410 * output channel is supported by a timer instance.
2411 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2412 * @param TIMx Timer instance
2413 * @param CompareValue between Min_Data=0 and Max_Data=65535
2414 * @retval None
2415 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2416 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2417 {
2418 WRITE_REG(TIMx->CCR3, CompareValue);
2419 }
2420
2421 /**
2422 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2423 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2424 * output channel 4 is supported by a timer instance.
2425 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2426 * @param TIMx Timer instance
2427 * @param CompareValue between Min_Data=0 and Max_Data=65535
2428 * @retval None
2429 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2430 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2431 {
2432 WRITE_REG(TIMx->CCR4, CompareValue);
2433 }
2434
2435 #if defined(TIM_CCR5_CCR5)
2436 /**
2437 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2438 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2439 * output channel 5 is supported by a timer instance.
2440 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2441 * @param TIMx Timer instance
2442 * @param CompareValue between Min_Data=0 and Max_Data=65535
2443 * @retval None
2444 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2445 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2446 {
2447 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2448 }
2449
2450 #endif /* TIM_CCR5_CCR5 */
2451 #if defined(TIM_CCR6_CCR6)
2452 /**
2453 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2454 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2455 * output channel 6 is supported by a timer instance.
2456 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2457 * @param TIMx Timer instance
2458 * @param CompareValue between Min_Data=0 and Max_Data=65535
2459 * @retval None
2460 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2461 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2462 {
2463 WRITE_REG(TIMx->CCR6, CompareValue);
2464 }
2465
2466 #endif /* TIM_CCR6_CCR6 */
2467 /**
2468 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2469 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2470 * output channel 1 is supported by a timer instance.
2471 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2472 * @param TIMx Timer instance
2473 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2474 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2475 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2476 {
2477 return (uint32_t)(READ_REG(TIMx->CCR1));
2478 }
2479
2480 /**
2481 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2482 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2483 * output channel 2 is supported by a timer instance.
2484 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2485 * @param TIMx Timer instance
2486 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2487 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2488 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2489 {
2490 return (uint32_t)(READ_REG(TIMx->CCR2));
2491 }
2492
2493 /**
2494 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2495 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2496 * output channel 3 is supported by a timer instance.
2497 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2498 * @param TIMx Timer instance
2499 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2500 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2501 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2502 {
2503 return (uint32_t)(READ_REG(TIMx->CCR3));
2504 }
2505
2506 /**
2507 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2508 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2509 * output channel 4 is supported by a timer instance.
2510 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2511 * @param TIMx Timer instance
2512 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2513 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2514 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2515 {
2516 return (uint32_t)(READ_REG(TIMx->CCR4));
2517 }
2518
2519 #if defined(TIM_CCR5_CCR5)
2520 /**
2521 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2522 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2523 * output channel 5 is supported by a timer instance.
2524 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2525 * @param TIMx Timer instance
2526 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2527 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2528 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2529 {
2530 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2531 }
2532
2533 #endif /* TIM_CCR5_CCR5 */
2534 #if defined(TIM_CCR6_CCR6)
2535 /**
2536 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2537 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2538 * output channel 6 is supported by a timer instance.
2539 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2540 * @param TIMx Timer instance
2541 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2542 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2543 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2544 {
2545 return (uint32_t)(READ_REG(TIMx->CCR6));
2546 }
2547
2548 #endif /* TIM_CCR6_CCR6 */
2549 #if defined(TIM_CCR5_CCR5)
2550 /**
2551 * @brief Select on which reference signal the OC5REF is combined to.
2552 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2553 * whether or not a timer instance supports the combined 3-phase PWM mode.
2554 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2555 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2556 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2557 * @param TIMx Timer instance
2558 * @param GroupCH5 This parameter can be a combination of the following values:
2559 * @arg @ref LL_TIM_GROUPCH5_NONE
2560 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2561 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2562 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2563 * @retval None
2564 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2565 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2566 {
2567 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2568 }
2569
2570 #endif /* TIM_CCR5_CCR5 */
2571 /**
2572 * @}
2573 */
2574
2575 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2576 * @{
2577 */
2578 /**
2579 * @brief Configure input channel.
2580 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2581 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2582 * CCMR1 IC1F LL_TIM_IC_Config\n
2583 * CCMR1 CC2S LL_TIM_IC_Config\n
2584 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2585 * CCMR1 IC2F LL_TIM_IC_Config\n
2586 * CCMR2 CC3S LL_TIM_IC_Config\n
2587 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2588 * CCMR2 IC3F LL_TIM_IC_Config\n
2589 * CCMR2 CC4S LL_TIM_IC_Config\n
2590 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2591 * CCMR2 IC4F LL_TIM_IC_Config\n
2592 * CCER CC1P LL_TIM_IC_Config\n
2593 * CCER CC1NP LL_TIM_IC_Config\n
2594 * CCER CC2P LL_TIM_IC_Config\n
2595 * CCER CC2NP LL_TIM_IC_Config\n
2596 * CCER CC3P LL_TIM_IC_Config\n
2597 * CCER CC3NP LL_TIM_IC_Config\n
2598 * CCER CC4P LL_TIM_IC_Config\n
2599 * CCER CC4NP LL_TIM_IC_Config
2600 * @param TIMx Timer instance
2601 * @param Channel This parameter can be one of the following values:
2602 * @arg @ref LL_TIM_CHANNEL_CH1
2603 * @arg @ref LL_TIM_CHANNEL_CH2
2604 * @arg @ref LL_TIM_CHANNEL_CH3
2605 * @arg @ref LL_TIM_CHANNEL_CH4
2606 * @param Configuration This parameter must be a combination of all the following values:
2607 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2608 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2609 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2610 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2611 * @retval None
2612 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2613 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2614 {
2615 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2616 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2617 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2618 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2619 << SHIFT_TAB_ICxx[iChannel]);
2620 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2621 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2622 }
2623
2624 /**
2625 * @brief Set the active input.
2626 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2627 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2628 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2629 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2630 * @param TIMx Timer instance
2631 * @param Channel This parameter can be one of the following values:
2632 * @arg @ref LL_TIM_CHANNEL_CH1
2633 * @arg @ref LL_TIM_CHANNEL_CH2
2634 * @arg @ref LL_TIM_CHANNEL_CH3
2635 * @arg @ref LL_TIM_CHANNEL_CH4
2636 * @param ICActiveInput This parameter can be one of the following values:
2637 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2638 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2639 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2640 * @retval None
2641 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2642 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2643 {
2644 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2645 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2646 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2647 }
2648
2649 /**
2650 * @brief Get the current active input.
2651 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2652 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2653 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2654 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2655 * @param TIMx Timer instance
2656 * @param Channel This parameter can be one of the following values:
2657 * @arg @ref LL_TIM_CHANNEL_CH1
2658 * @arg @ref LL_TIM_CHANNEL_CH2
2659 * @arg @ref LL_TIM_CHANNEL_CH3
2660 * @arg @ref LL_TIM_CHANNEL_CH4
2661 * @retval Returned value can be one of the following values:
2662 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2663 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2664 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2665 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2666 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2667 {
2668 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2669 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2670 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2671 }
2672
2673 /**
2674 * @brief Set the prescaler of input channel.
2675 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2676 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2677 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2678 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2679 * @param TIMx Timer instance
2680 * @param Channel This parameter can be one of the following values:
2681 * @arg @ref LL_TIM_CHANNEL_CH1
2682 * @arg @ref LL_TIM_CHANNEL_CH2
2683 * @arg @ref LL_TIM_CHANNEL_CH3
2684 * @arg @ref LL_TIM_CHANNEL_CH4
2685 * @param ICPrescaler This parameter can be one of the following values:
2686 * @arg @ref LL_TIM_ICPSC_DIV1
2687 * @arg @ref LL_TIM_ICPSC_DIV2
2688 * @arg @ref LL_TIM_ICPSC_DIV4
2689 * @arg @ref LL_TIM_ICPSC_DIV8
2690 * @retval None
2691 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2692 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2693 {
2694 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2695 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2696 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2697 }
2698
2699 /**
2700 * @brief Get the current prescaler value acting on an input channel.
2701 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2702 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2703 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2704 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2705 * @param TIMx Timer instance
2706 * @param Channel This parameter can be one of the following values:
2707 * @arg @ref LL_TIM_CHANNEL_CH1
2708 * @arg @ref LL_TIM_CHANNEL_CH2
2709 * @arg @ref LL_TIM_CHANNEL_CH3
2710 * @arg @ref LL_TIM_CHANNEL_CH4
2711 * @retval Returned value can be one of the following values:
2712 * @arg @ref LL_TIM_ICPSC_DIV1
2713 * @arg @ref LL_TIM_ICPSC_DIV2
2714 * @arg @ref LL_TIM_ICPSC_DIV4
2715 * @arg @ref LL_TIM_ICPSC_DIV8
2716 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2717 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2718 {
2719 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2720 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2721 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2722 }
2723
2724 /**
2725 * @brief Set the input filter duration.
2726 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2727 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2728 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2729 * CCMR2 IC4F LL_TIM_IC_SetFilter
2730 * @param TIMx Timer instance
2731 * @param Channel This parameter can be one of the following values:
2732 * @arg @ref LL_TIM_CHANNEL_CH1
2733 * @arg @ref LL_TIM_CHANNEL_CH2
2734 * @arg @ref LL_TIM_CHANNEL_CH3
2735 * @arg @ref LL_TIM_CHANNEL_CH4
2736 * @param ICFilter This parameter can be one of the following values:
2737 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2738 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2739 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2740 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2741 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2742 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2743 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2744 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2745 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2746 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2747 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2748 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2749 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2750 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2751 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2752 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2753 * @retval None
2754 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2755 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2756 {
2757 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2759 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2760 }
2761
2762 /**
2763 * @brief Get the input filter duration.
2764 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2765 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2766 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2767 * CCMR2 IC4F LL_TIM_IC_GetFilter
2768 * @param TIMx Timer instance
2769 * @param Channel This parameter can be one of the following values:
2770 * @arg @ref LL_TIM_CHANNEL_CH1
2771 * @arg @ref LL_TIM_CHANNEL_CH2
2772 * @arg @ref LL_TIM_CHANNEL_CH3
2773 * @arg @ref LL_TIM_CHANNEL_CH4
2774 * @retval Returned value can be one of the following values:
2775 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2776 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2777 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2778 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2779 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2780 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2781 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2782 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2783 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2784 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2785 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2786 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2787 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2788 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2789 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2790 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2791 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2792 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2793 {
2794 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2795 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2796 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2797 }
2798
2799 /**
2800 * @brief Set the input channel polarity.
2801 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2802 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2803 * CCER CC2P LL_TIM_IC_SetPolarity\n
2804 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2805 * CCER CC3P LL_TIM_IC_SetPolarity\n
2806 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2807 * CCER CC4P LL_TIM_IC_SetPolarity\n
2808 * CCER CC4NP LL_TIM_IC_SetPolarity
2809 * @param TIMx Timer instance
2810 * @param Channel This parameter can be one of the following values:
2811 * @arg @ref LL_TIM_CHANNEL_CH1
2812 * @arg @ref LL_TIM_CHANNEL_CH2
2813 * @arg @ref LL_TIM_CHANNEL_CH3
2814 * @arg @ref LL_TIM_CHANNEL_CH4
2815 * @param ICPolarity This parameter can be one of the following values:
2816 * @arg @ref LL_TIM_IC_POLARITY_RISING
2817 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2818 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2819 * @retval None
2820 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2821 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2822 {
2823 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2824 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2825 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2826 }
2827
2828 /**
2829 * @brief Get the current input channel polarity.
2830 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2831 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2832 * CCER CC2P LL_TIM_IC_GetPolarity\n
2833 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2834 * CCER CC3P LL_TIM_IC_GetPolarity\n
2835 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2836 * CCER CC4P LL_TIM_IC_GetPolarity\n
2837 * CCER CC4NP LL_TIM_IC_GetPolarity
2838 * @param TIMx Timer instance
2839 * @param Channel This parameter can be one of the following values:
2840 * @arg @ref LL_TIM_CHANNEL_CH1
2841 * @arg @ref LL_TIM_CHANNEL_CH2
2842 * @arg @ref LL_TIM_CHANNEL_CH3
2843 * @arg @ref LL_TIM_CHANNEL_CH4
2844 * @retval Returned value can be one of the following values:
2845 * @arg @ref LL_TIM_IC_POLARITY_RISING
2846 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2847 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2848 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2849 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2850 {
2851 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2852 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2853 SHIFT_TAB_CCxP[iChannel]);
2854 }
2855
2856 /**
2857 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2858 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2859 * a timer instance provides an XOR input.
2860 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2861 * @param TIMx Timer instance
2862 * @retval None
2863 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2864 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2865 {
2866 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2867 }
2868
2869 /**
2870 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2871 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2872 * a timer instance provides an XOR input.
2873 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2874 * @param TIMx Timer instance
2875 * @retval None
2876 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2877 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2878 {
2879 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2880 }
2881
2882 /**
2883 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2884 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2885 * a timer instance provides an XOR input.
2886 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2887 * @param TIMx Timer instance
2888 * @retval State of bit (1 or 0).
2889 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2890 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2891 {
2892 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2893 }
2894
2895 /**
2896 * @brief Get captured value for input channel 1.
2897 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2898 * input channel 1 is supported by a timer instance.
2899 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2900 * @param TIMx Timer instance
2901 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2902 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2903 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2904 {
2905 return (uint32_t)(READ_REG(TIMx->CCR1));
2906 }
2907
2908 /**
2909 * @brief Get captured value for input channel 2.
2910 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2911 * input channel 2 is supported by a timer instance.
2912 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2913 * @param TIMx Timer instance
2914 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2915 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2916 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2917 {
2918 return (uint32_t)(READ_REG(TIMx->CCR2));
2919 }
2920
2921 /**
2922 * @brief Get captured value for input channel 3.
2923 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2924 * input channel 3 is supported by a timer instance.
2925 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2926 * @param TIMx Timer instance
2927 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2928 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2929 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2930 {
2931 return (uint32_t)(READ_REG(TIMx->CCR3));
2932 }
2933
2934 /**
2935 * @brief Get captured value for input channel 4.
2936 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2937 * input channel 4 is supported by a timer instance.
2938 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2939 * @param TIMx Timer instance
2940 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2941 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)2942 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
2943 {
2944 return (uint32_t)(READ_REG(TIMx->CCR4));
2945 }
2946
2947 /**
2948 * @}
2949 */
2950
2951 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2952 * @{
2953 */
2954 /**
2955 * @brief Enable external clock mode 2.
2956 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2957 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2958 * whether or not a timer instance supports external clock mode2.
2959 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2960 * @param TIMx Timer instance
2961 * @retval None
2962 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2963 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2964 {
2965 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2966 }
2967
2968 /**
2969 * @brief Disable external clock mode 2.
2970 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2971 * whether or not a timer instance supports external clock mode2.
2972 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2973 * @param TIMx Timer instance
2974 * @retval None
2975 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2976 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2977 {
2978 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2979 }
2980
2981 /**
2982 * @brief Indicate whether external clock mode 2 is enabled.
2983 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2984 * whether or not a timer instance supports external clock mode2.
2985 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2986 * @param TIMx Timer instance
2987 * @retval State of bit (1 or 0).
2988 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)2989 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
2990 {
2991 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2992 }
2993
2994 /**
2995 * @brief Set the clock source of the counter clock.
2996 * @note when selected clock source is external clock mode 1, the timer input
2997 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2998 * function. This timer input must be configured by calling
2999 * the @ref LL_TIM_IC_Config() function.
3000 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3001 * whether or not a timer instance supports external clock mode1.
3002 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3003 * whether or not a timer instance supports external clock mode2.
3004 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3005 * SMCR ECE LL_TIM_SetClockSource
3006 * @param TIMx Timer instance
3007 * @param ClockSource This parameter can be one of the following values:
3008 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3009 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3010 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3011 * @retval None
3012 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3013 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3014 {
3015 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3016 }
3017
3018 /**
3019 * @brief Set the encoder interface mode.
3020 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3021 * whether or not a timer instance supports the encoder mode.
3022 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3023 * @param TIMx Timer instance
3024 * @param EncoderMode This parameter can be one of the following values:
3025 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3026 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3027 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3028 * @retval None
3029 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3030 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3031 {
3032 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3033 }
3034
3035 /**
3036 * @}
3037 */
3038
3039 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3040 * @{
3041 */
3042
3043 /**
3044 * @brief Set the synchronization mode of a slave timer.
3045 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3046 * a timer instance can operate as a slave timer.
3047 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3048 * @param TIMx Timer instance
3049 * @param SlaveMode This parameter can be one of the following values:
3050 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3051 * @arg @ref LL_TIM_SLAVEMODE_RESET
3052 * @arg @ref LL_TIM_SLAVEMODE_GATED
3053 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3054 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3055 * @retval None
3056 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3057 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3058 {
3059 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3060 }
3061
3062 /**
3063 * @brief Set the selects the trigger input to be used to synchronize the counter.
3064 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3065 * a timer instance can operate as a slave timer.
3066 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3067 * @param TIMx Timer instance
3068 * @param TriggerInput This parameter can be one of the following values:
3069 * @arg @ref LL_TIM_TS_TI1F_ED
3070 * @arg @ref LL_TIM_TS_TI1FP1
3071 * @arg @ref LL_TIM_TS_TI2FP2
3072 * @arg @ref LL_TIM_TS_ETRF
3073 * @retval None
3074 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3075 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3076 {
3077 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3078 }
3079
3080
3081 /**
3082 * @brief Configure the external trigger (ETR) input.
3083 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3084 * a timer instance provides an external trigger input.
3085 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3086 * SMCR ETPS LL_TIM_ConfigETR\n
3087 * SMCR ETF LL_TIM_ConfigETR
3088 * @param TIMx Timer instance
3089 * @param ETRPolarity This parameter can be one of the following values:
3090 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3091 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3092 * @param ETRPrescaler This parameter can be one of the following values:
3093 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3094 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3095 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3096 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3097 * @param ETRFilter This parameter can be one of the following values:
3098 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3099 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3100 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3101 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3102 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3103 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3104 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3105 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3106 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3107 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3108 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3109 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3110 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3111 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3112 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3113 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3114 * @retval None
3115 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3116 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3117 uint32_t ETRFilter)
3118 {
3119 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3120 }
3121
3122 /**
3123 * @}
3124 */
3125
3126 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3127 * @{
3128 */
3129 /**
3130 * @brief Enable the break function.
3131 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3132 * a timer instance provides a break input.
3133 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3134 * @param TIMx Timer instance
3135 * @retval None
3136 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3137 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3138 {
3139 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3140 }
3141
3142 /**
3143 * @brief Disable the break function.
3144 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3145 * @param TIMx Timer instance
3146 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3147 * a timer instance provides a break input.
3148 * @retval None
3149 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3150 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3151 {
3152 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3153 }
3154
3155 /**
3156 * @brief Configure the break input.
3157 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3158 * a timer instance provides a break input.
3159 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3160 * in input mode and in open drain output mode. Any active Break event will
3161 * assert a low logic level on the Break input to indicate an internal break
3162 * event to external devices.
3163 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3164 * BDTR BKF LL_TIM_ConfigBRK\n
3165 * BDTR BKBID LL_TIM_ConfigBRK
3166 * @param TIMx Timer instance
3167 * @param BreakPolarity This parameter can be one of the following values:
3168 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3169 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3170 * @param BreakFilter This parameter can be one of the following values:
3171 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3172 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3173 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3174 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3175 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3176 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3177 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3178 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3179 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3180 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3181 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3182 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3183 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3184 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3185 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3186 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3187 * @param BreakAFMode This parameter can be one of the following values:
3188 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3189 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3190 * @retval None
3191 */
3192 #if defined(TIM_BDTR_BKBID)
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakAFMode)3193 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakAFMode)
3194 {
3195 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKBID, BreakPolarity | BreakAFMode);
3196 }
3197 #else
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3198 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
3199 {
3200 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3201 }
3202 #endif /* TIM_BDTR_BKBID */
3203
3204 #if defined(TIM_BDTR_BKBID)
3205 /**
3206 * @brief Disarm the break input (when it operates in bidirectional mode).
3207 * @note The break input can be disarmed only when it is configured in
3208 * bidirectional mode and when when MOE is reset.
3209 * @note Purpose is to be able to have the input voltage back to high-state,
3210 * whatever the time constant on the output .
3211 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3212 * @param TIMx Timer instance
3213 * @retval None
3214 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3215 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3216 {
3217 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3218 }
3219
3220 /**
3221 * @brief Re-arm the break input (when it operates in bidirectional mode).
3222 * @note The Break input is automatically armed as soon as MOE bit is set.
3223 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3224 * @param TIMx Timer instance
3225 * @retval None
3226 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3227 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3228 {
3229 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3230 }
3231
3232 #endif /*TIM_BDTR_BKBID */
3233 #if defined(TIM_BDTR_BK2E)
3234 /**
3235 * @brief Enable the break 2 function.
3236 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3237 * a timer instance provides a second break input.
3238 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3239 * @param TIMx Timer instance
3240 * @retval None
3241 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3242 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3243 {
3244 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3245 }
3246
3247 /**
3248 * @brief Disable the break 2 function.
3249 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3250 * a timer instance provides a second break input.
3251 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3252 * @param TIMx Timer instance
3253 * @retval None
3254 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3255 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3256 {
3257 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3258 }
3259
3260 #if defined(TIM_BDTR_BKBID)
3261 /**
3262 * @brief Configure the break 2 input.
3263 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3264 * a timer instance provides a second break input.
3265 * @note Bidirectional mode is only supported by advanced timer instances.
3266 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3267 * a timer instance is an advanced-control timer.
3268 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3269 * in input mode and in open drain output mode. Any active Break event will
3270 * assert a low logic level on the Break 2 input to indicate an internal break
3271 * event to external devices.
3272 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3273 * LL_TIM_BREAK2_AFMODE_INPUT.
3274 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3275 * BDTR BK2F LL_TIM_ConfigBRK2\n
3276 * BDTR BK2BID LL_TIM_ConfigBRK2
3277 * @param TIMx Timer instance
3278 * @param Break2Polarity This parameter can be one of the following values:
3279 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3280 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3281 * @param Break2Filter This parameter can be one of the following values:
3282 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3283 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3284 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3285 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3286 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3287 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3288 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3289 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3290 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3291 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3292 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3293 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3294 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3295 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3296 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3297 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3298 * @param Break2AFMode This parameter can be one of the following values:
3299 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3300 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3301 * @retval None
3302 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3303 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3304 uint32_t Break2AFMode)
3305 {
3306 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3307 }
3308
3309 #else
3310 /**
3311 * @brief Configure the break 2 input.
3312 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3313 * a timer instance provides a second break input.
3314 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3315 * BDTR BK2F LL_TIM_ConfigBRK2
3316 * @param TIMx Timer instance
3317 * @param Break2Polarity This parameter can be one of the following values:
3318 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3319 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3320 * @param Break2Filter This parameter can be one of the following values:
3321 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3322 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3323 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3324 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3325 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3326 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3327 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3328 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3329 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3330 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3331 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3332 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3333 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3334 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3335 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3336 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3337 * @retval None
3338 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3339 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3340 {
3341 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3342 }
3343
3344 #endif /*TIM_BDTR_BKBID */
3345 #endif /* TIM_BDTR_BK2E */
3346
3347 /**
3348 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3349 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3350 * a timer instance provides a break input.
3351 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3352 * BDTR OSSR LL_TIM_SetOffStates
3353 * @param TIMx Timer instance
3354 * @param OffStateIdle This parameter can be one of the following values:
3355 * @arg @ref LL_TIM_OSSI_DISABLE
3356 * @arg @ref LL_TIM_OSSI_ENABLE
3357 * @param OffStateRun This parameter can be one of the following values:
3358 * @arg @ref LL_TIM_OSSR_DISABLE
3359 * @arg @ref LL_TIM_OSSR_ENABLE
3360 * @retval None
3361 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3362 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3363 {
3364 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3365 }
3366
3367 /**
3368 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3369 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3370 * a timer instance provides a break input.
3371 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3372 * @param TIMx Timer instance
3373 * @retval None
3374 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3375 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3376 {
3377 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3378 }
3379
3380 /**
3381 * @brief Disable automatic output (MOE can be set only by software).
3382 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3383 * a timer instance provides a break input.
3384 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3385 * @param TIMx Timer instance
3386 * @retval None
3387 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3388 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3389 {
3390 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3391 }
3392
3393 /**
3394 * @brief Indicate whether automatic output is enabled.
3395 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3396 * a timer instance provides a break input.
3397 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3398 * @param TIMx Timer instance
3399 * @retval State of bit (1 or 0).
3400 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3401 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3402 {
3403 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3404 }
3405
3406 /**
3407 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3408 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3409 * software and is reset in case of break or break2 event
3410 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3411 * a timer instance provides a break input.
3412 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3413 * @param TIMx Timer instance
3414 * @retval None
3415 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3416 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3417 {
3418 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3419 }
3420
3421 /**
3422 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3423 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3424 * software and is reset in case of break or break2 event.
3425 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3426 * a timer instance provides a break input.
3427 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3428 * @param TIMx Timer instance
3429 * @retval None
3430 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3431 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3432 {
3433 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3434 }
3435
3436 /**
3437 * @brief Indicates whether outputs are enabled.
3438 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3439 * a timer instance provides a break input.
3440 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3441 * @param TIMx Timer instance
3442 * @retval State of bit (1 or 0).
3443 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3444 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3445 {
3446 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3447 }
3448
3449 /**
3450 * @brief Enable the signals connected to the designated timer break input.
3451 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3452 * or not a timer instance allows for break input selection.
3453 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3454 * AF2 BK2INE LL_TIM_EnableBreakInputSource
3455 * @param TIMx Timer instance
3456 * @param BreakInput This parameter can be one of the following values:
3457 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3458 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3459 * @param Source This parameter can be one of the following values:
3460 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3461 * @retval None
3462 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3463 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3464 {
3465 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3466 SET_BIT(*pReg, Source);
3467 }
3468
3469 /**
3470 * @brief Disable the signals connected to the designated timer break input.
3471 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3472 * or not a timer instance allows for break input selection.
3473 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3474 * AF2 BK2INE LL_TIM_DisableBreakInputSource
3475 * @param TIMx Timer instance
3476 * @param BreakInput This parameter can be one of the following values:
3477 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3478 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3479 * @param Source This parameter can be one of the following values:
3480 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3481 * @retval None
3482 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3483 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3484 {
3485 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3486 CLEAR_BIT(*pReg, Source);
3487 }
3488
3489 /**
3490 * @brief Set the polarity of the break signal for the timer break input.
3491 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3492 * or not a timer instance allows for break input selection.
3493 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3494 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity
3495 * @param TIMx Timer instance
3496 * @param BreakInput This parameter can be one of the following values:
3497 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3498 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3499 * @param Source This parameter can be one of the following values:
3500 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3501 * @param Polarity This parameter can be one of the following values:
3502 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3503 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3504 * @retval None
3505 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3506 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3507 uint32_t Polarity)
3508 {
3509 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3510 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3511 }
3512 /**
3513 * @}
3514 */
3515
3516 #if defined(TIM_DMA_SUPPORT)
3517 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3518 * @{
3519 */
3520 /**
3521 * @brief Configures the timer DMA burst feature.
3522 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3523 * not a timer instance supports the DMA burst mode.
3524 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3525 * DCR DBA LL_TIM_ConfigDMABurst
3526 * @param TIMx Timer instance
3527 * @param DMABurstBaseAddress This parameter can be one of the following values:
3528 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3529 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3530 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3531 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3532 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3533 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3534 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3535 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3536 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3537 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3538 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3539 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3540 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3541 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3542 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3543 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3544 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3545 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3546 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3547 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3548 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3549 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3550 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3551 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3552 * @param DMABurstLength This parameter can be one of the following values:
3553 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3554 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3555 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3556 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3557 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3558 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3559 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3560 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3561 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3562 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3563 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3564 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3565 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3566 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3567 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3568 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3569 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3570 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3571 * @retval None
3572 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3573 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3574 {
3575 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3576 }
3577
3578 /**
3579 * @}
3580 */
3581 #endif /* TIM_DMA_SUPPORT */
3582
3583 #if defined(TIM17)
3584 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3585 * @{
3586 */
3587 /**
3588 * @brief Remap TIM inputs (input channel, internal/external triggers).
3589 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3590 * a some timer inputs can be remapped.
3591 * @rmtoll TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3592 * @param TIMx Timer instance
3593 * @param Remap This parameter can be one of the following values:
3594 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3595 * @arg @ref LL_TIM_TIM17_TI1_RMP_LCO
3596 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3597 *
3598 * @retval None
3599 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3600 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3601 {
3602 WRITE_REG(TIMx->OR1, Remap);
3603 }
3604
3605 /**
3606 * @}
3607 */
3608 #endif /* TIM17 */
3609
3610 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3611 * @{
3612 */
3613 /**
3614 * @brief Set the OCREF clear input source
3615 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3616 * @note This function can only be used in Output compare and PWM modes.
3617 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3618 * @param TIMx Timer instance
3619 * @param OCRefClearInputSource This parameter can be one of the following values:
3620 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3621 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3622 * @retval None
3623 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3624 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3625 {
3626 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
3627 }
3628 /**
3629 * @}
3630 */
3631
3632 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3633 * @{
3634 */
3635 /**
3636 * @brief Clear the update interrupt flag (UIF).
3637 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3638 * @param TIMx Timer instance
3639 * @retval None
3640 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3641 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3642 {
3643 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3644 }
3645
3646 /**
3647 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3648 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3649 * @param TIMx Timer instance
3650 * @retval State of bit (1 or 0).
3651 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3652 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3653 {
3654 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3655 }
3656
3657 /**
3658 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3659 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3660 * @param TIMx Timer instance
3661 * @retval None
3662 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3663 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3664 {
3665 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3666 }
3667
3668 /**
3669 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3670 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3671 * @param TIMx Timer instance
3672 * @retval State of bit (1 or 0).
3673 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3674 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3675 {
3676 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3677 }
3678
3679 /**
3680 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3681 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3682 * @param TIMx Timer instance
3683 * @retval None
3684 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3685 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3686 {
3687 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3688 }
3689
3690 /**
3691 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3692 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3693 * @param TIMx Timer instance
3694 * @retval State of bit (1 or 0).
3695 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3696 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3697 {
3698 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3699 }
3700
3701 /**
3702 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3703 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3704 * @param TIMx Timer instance
3705 * @retval None
3706 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3707 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3708 {
3709 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3710 }
3711
3712 /**
3713 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3714 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3715 * @param TIMx Timer instance
3716 * @retval State of bit (1 or 0).
3717 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3718 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3719 {
3720 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3721 }
3722
3723 /**
3724 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3725 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3726 * @param TIMx Timer instance
3727 * @retval None
3728 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3729 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3730 {
3731 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3732 }
3733
3734 /**
3735 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3736 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3737 * @param TIMx Timer instance
3738 * @retval State of bit (1 or 0).
3739 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3740 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3741 {
3742 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3743 }
3744
3745 #if defined (TIM_SR_CC5IF)
3746 /**
3747 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
3748 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
3749 * @param TIMx Timer instance
3750 * @retval None
3751 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)3752 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
3753 {
3754 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
3755 }
3756
3757 /**
3758 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
3759 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
3760 * @param TIMx Timer instance
3761 * @retval State of bit (1 or 0).
3762 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)3763 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
3764 {
3765 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
3766 }
3767
3768 #endif /* TIM_SR_CC5IF */
3769 #if defined (TIM_SR_CC6IF)
3770 /**
3771 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
3772 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
3773 * @param TIMx Timer instance
3774 * @retval None
3775 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)3776 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
3777 {
3778 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
3779 }
3780
3781 /**
3782 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
3783 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
3784 * @param TIMx Timer instance
3785 * @retval State of bit (1 or 0).
3786 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)3787 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
3788 {
3789 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
3790 }
3791
3792 #endif /* TIM_SR_CC6IF */
3793 /**
3794 * @brief Clear the commutation interrupt flag (COMIF).
3795 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3796 * @param TIMx Timer instance
3797 * @retval None
3798 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3799 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3800 {
3801 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3802 }
3803
3804 /**
3805 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3806 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3807 * @param TIMx Timer instance
3808 * @retval State of bit (1 or 0).
3809 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3810 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3811 {
3812 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3813 }
3814
3815 /**
3816 * @brief Clear the trigger interrupt flag (TIF).
3817 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3818 * @param TIMx Timer instance
3819 * @retval None
3820 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3821 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3822 {
3823 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3824 }
3825
3826 /**
3827 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3828 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3829 * @param TIMx Timer instance
3830 * @retval State of bit (1 or 0).
3831 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3832 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3833 {
3834 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3835 }
3836
3837 /**
3838 * @brief Clear the break interrupt flag (BIF).
3839 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3840 * @param TIMx Timer instance
3841 * @retval None
3842 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3843 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3844 {
3845 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3846 }
3847
3848 /**
3849 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3850 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3851 * @param TIMx Timer instance
3852 * @retval State of bit (1 or 0).
3853 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3854 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3855 {
3856 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3857 }
3858
3859 #if defined(TIM_SR_B2IF)
3860 /**
3861 * @brief Clear the break 2 interrupt flag (B2IF).
3862 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
3863 * @param TIMx Timer instance
3864 * @retval None
3865 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)3866 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
3867 {
3868 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
3869 }
3870
3871 /**
3872 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
3873 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
3874 * @param TIMx Timer instance
3875 * @retval State of bit (1 or 0).
3876 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)3877 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
3878 {
3879 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
3880 }
3881
3882 #endif /* TIM_SR_B2IF */
3883 /**
3884 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3885 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3886 * @param TIMx Timer instance
3887 * @retval None
3888 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3889 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3890 {
3891 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3892 }
3893
3894 /**
3895 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3896 * (Capture/Compare 1 interrupt is pending).
3897 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3898 * @param TIMx Timer instance
3899 * @retval State of bit (1 or 0).
3900 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3901 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3902 {
3903 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3904 }
3905
3906 /**
3907 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3908 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3909 * @param TIMx Timer instance
3910 * @retval None
3911 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3912 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3913 {
3914 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3915 }
3916
3917 /**
3918 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3919 * (Capture/Compare 2 over-capture interrupt is pending).
3920 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3921 * @param TIMx Timer instance
3922 * @retval State of bit (1 or 0).
3923 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)3924 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
3925 {
3926 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3927 }
3928
3929 /**
3930 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3931 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3932 * @param TIMx Timer instance
3933 * @retval None
3934 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3935 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3936 {
3937 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3938 }
3939
3940 /**
3941 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3942 * (Capture/Compare 3 over-capture interrupt is pending).
3943 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3944 * @param TIMx Timer instance
3945 * @retval State of bit (1 or 0).
3946 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)3947 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
3948 {
3949 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3950 }
3951
3952 /**
3953 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3954 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3955 * @param TIMx Timer instance
3956 * @retval None
3957 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3958 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3959 {
3960 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3961 }
3962
3963 /**
3964 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3965 * (Capture/Compare 4 over-capture interrupt is pending).
3966 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3967 * @param TIMx Timer instance
3968 * @retval State of bit (1 or 0).
3969 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)3970 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
3971 {
3972 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3973 }
3974
3975 /**
3976 * @}
3977 */
3978
3979 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3980 * @{
3981 */
3982 /**
3983 * @brief Enable update interrupt (UIE).
3984 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3985 * @param TIMx Timer instance
3986 * @retval None
3987 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3988 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3989 {
3990 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3991 }
3992
3993 /**
3994 * @brief Disable update interrupt (UIE).
3995 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3996 * @param TIMx Timer instance
3997 * @retval None
3998 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3999 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4000 {
4001 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4002 }
4003
4004 /**
4005 * @brief Indicates whether the update interrupt (UIE) is enabled.
4006 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4007 * @param TIMx Timer instance
4008 * @retval State of bit (1 or 0).
4009 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4010 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4011 {
4012 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4013 }
4014
4015 /**
4016 * @brief Enable capture/compare 1 interrupt (CC1IE).
4017 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4018 * @param TIMx Timer instance
4019 * @retval None
4020 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4021 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4022 {
4023 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4024 }
4025
4026 /**
4027 * @brief Disable capture/compare 1 interrupt (CC1IE).
4028 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4029 * @param TIMx Timer instance
4030 * @retval None
4031 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4032 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4033 {
4034 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4035 }
4036
4037 /**
4038 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4039 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4040 * @param TIMx Timer instance
4041 * @retval State of bit (1 or 0).
4042 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4043 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4044 {
4045 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4046 }
4047
4048 /**
4049 * @brief Enable capture/compare 2 interrupt (CC2IE).
4050 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4051 * @param TIMx Timer instance
4052 * @retval None
4053 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4054 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4055 {
4056 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4057 }
4058
4059 /**
4060 * @brief Disable capture/compare 2 interrupt (CC2IE).
4061 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4062 * @param TIMx Timer instance
4063 * @retval None
4064 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4065 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4066 {
4067 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4068 }
4069
4070 /**
4071 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4072 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4073 * @param TIMx Timer instance
4074 * @retval State of bit (1 or 0).
4075 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4076 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4077 {
4078 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4079 }
4080
4081 /**
4082 * @brief Enable capture/compare 3 interrupt (CC3IE).
4083 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4084 * @param TIMx Timer instance
4085 * @retval None
4086 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4087 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4088 {
4089 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4090 }
4091
4092 /**
4093 * @brief Disable capture/compare 3 interrupt (CC3IE).
4094 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4095 * @param TIMx Timer instance
4096 * @retval None
4097 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4098 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4099 {
4100 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4101 }
4102
4103 /**
4104 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4105 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4106 * @param TIMx Timer instance
4107 * @retval State of bit (1 or 0).
4108 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4109 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4110 {
4111 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4112 }
4113
4114 /**
4115 * @brief Enable capture/compare 4 interrupt (CC4IE).
4116 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4117 * @param TIMx Timer instance
4118 * @retval None
4119 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4120 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4121 {
4122 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4123 }
4124
4125 /**
4126 * @brief Disable capture/compare 4 interrupt (CC4IE).
4127 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4128 * @param TIMx Timer instance
4129 * @retval None
4130 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4131 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4132 {
4133 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4134 }
4135
4136 /**
4137 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4138 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4139 * @param TIMx Timer instance
4140 * @retval State of bit (1 or 0).
4141 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4142 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4143 {
4144 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4145 }
4146
4147 /**
4148 * @brief Enable commutation interrupt (COMIE).
4149 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4150 * @param TIMx Timer instance
4151 * @retval None
4152 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4153 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4154 {
4155 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4156 }
4157
4158 /**
4159 * @brief Disable commutation interrupt (COMIE).
4160 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4161 * @param TIMx Timer instance
4162 * @retval None
4163 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4164 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4165 {
4166 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4167 }
4168
4169 /**
4170 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4171 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4172 * @param TIMx Timer instance
4173 * @retval State of bit (1 or 0).
4174 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4175 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4176 {
4177 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4178 }
4179
4180 /**
4181 * @brief Enable trigger interrupt (TIE).
4182 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4183 * @param TIMx Timer instance
4184 * @retval None
4185 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4186 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4187 {
4188 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4189 }
4190
4191 /**
4192 * @brief Disable trigger interrupt (TIE).
4193 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4194 * @param TIMx Timer instance
4195 * @retval None
4196 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4197 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4198 {
4199 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4200 }
4201
4202 /**
4203 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4204 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4205 * @param TIMx Timer instance
4206 * @retval State of bit (1 or 0).
4207 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4208 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4209 {
4210 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4211 }
4212
4213 /**
4214 * @brief Enable break interrupt (BIE).
4215 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4216 * @param TIMx Timer instance
4217 * @retval None
4218 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4219 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4220 {
4221 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4222 }
4223
4224 /**
4225 * @brief Disable break interrupt (BIE).
4226 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4227 * @param TIMx Timer instance
4228 * @retval None
4229 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4230 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4231 {
4232 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4233 }
4234
4235 /**
4236 * @brief Indicates whether the break interrupt (BIE) is enabled.
4237 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4238 * @param TIMx Timer instance
4239 * @retval State of bit (1 or 0).
4240 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4241 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4242 {
4243 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4244 }
4245
4246 /**
4247 * @}
4248 */
4249
4250 #if defined(TIM_DMA_SUPPORT)
4251 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4252 * @{
4253 */
4254 /**
4255 * @brief Enable update DMA request (UDE).
4256 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4257 * @param TIMx Timer instance
4258 * @retval None
4259 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4260 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4261 {
4262 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4263 }
4264
4265 /**
4266 * @brief Disable update DMA request (UDE).
4267 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4268 * @param TIMx Timer instance
4269 * @retval None
4270 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4271 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4272 {
4273 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4274 }
4275
4276 /**
4277 * @brief Indicates whether the update DMA request (UDE) is enabled.
4278 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4279 * @param TIMx Timer instance
4280 * @retval State of bit (1 or 0).
4281 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4282 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4283 {
4284 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4285 }
4286
4287 /**
4288 * @brief Enable capture/compare 1 DMA request (CC1DE).
4289 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4290 * @param TIMx Timer instance
4291 * @retval None
4292 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4293 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4294 {
4295 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4296 }
4297
4298 /**
4299 * @brief Disable capture/compare 1 DMA request (CC1DE).
4300 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4301 * @param TIMx Timer instance
4302 * @retval None
4303 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4304 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4305 {
4306 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4307 }
4308
4309 /**
4310 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4311 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4312 * @param TIMx Timer instance
4313 * @retval State of bit (1 or 0).
4314 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4315 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4316 {
4317 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4318 }
4319
4320 /**
4321 * @brief Enable capture/compare 2 DMA request (CC2DE).
4322 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4323 * @param TIMx Timer instance
4324 * @retval None
4325 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4326 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4327 {
4328 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4329 }
4330
4331 /**
4332 * @brief Disable capture/compare 2 DMA request (CC2DE).
4333 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4334 * @param TIMx Timer instance
4335 * @retval None
4336 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4337 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4338 {
4339 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4340 }
4341
4342 /**
4343 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4344 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4345 * @param TIMx Timer instance
4346 * @retval State of bit (1 or 0).
4347 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4348 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4349 {
4350 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4351 }
4352
4353 /**
4354 * @brief Enable capture/compare 3 DMA request (CC3DE).
4355 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4356 * @param TIMx Timer instance
4357 * @retval None
4358 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4359 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4360 {
4361 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4362 }
4363
4364 /**
4365 * @brief Disable capture/compare 3 DMA request (CC3DE).
4366 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4367 * @param TIMx Timer instance
4368 * @retval None
4369 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4370 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4371 {
4372 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4373 }
4374
4375 /**
4376 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4377 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4378 * @param TIMx Timer instance
4379 * @retval State of bit (1 or 0).
4380 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4381 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4382 {
4383 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4384 }
4385
4386 /**
4387 * @brief Enable capture/compare 4 DMA request (CC4DE).
4388 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4389 * @param TIMx Timer instance
4390 * @retval None
4391 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4392 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4393 {
4394 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4395 }
4396
4397 /**
4398 * @brief Disable capture/compare 4 DMA request (CC4DE).
4399 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4400 * @param TIMx Timer instance
4401 * @retval None
4402 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4403 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4404 {
4405 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4406 }
4407
4408 /**
4409 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4410 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4411 * @param TIMx Timer instance
4412 * @retval State of bit (1 or 0).
4413 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4414 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4415 {
4416 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4417 }
4418
4419
4420 /**
4421 * @}
4422 */
4423 #endif /* TIM_DMA_SUPPORT */
4424
4425 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4426 * @{
4427 */
4428 /**
4429 * @brief Generate an update event.
4430 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4431 * @param TIMx Timer instance
4432 * @retval None
4433 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4434 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4435 {
4436 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4437 }
4438
4439 /**
4440 * @brief Generate Capture/Compare 1 event.
4441 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4442 * @param TIMx Timer instance
4443 * @retval None
4444 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4445 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4446 {
4447 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4448 }
4449
4450 /**
4451 * @brief Generate Capture/Compare 2 event.
4452 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4453 * @param TIMx Timer instance
4454 * @retval None
4455 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4456 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4457 {
4458 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4459 }
4460
4461 /**
4462 * @brief Generate Capture/Compare 3 event.
4463 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4464 * @param TIMx Timer instance
4465 * @retval None
4466 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4467 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4468 {
4469 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4470 }
4471
4472 /**
4473 * @brief Generate Capture/Compare 4 event.
4474 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4475 * @param TIMx Timer instance
4476 * @retval None
4477 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4478 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4479 {
4480 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4481 }
4482
4483 /**
4484 * @brief Generate commutation event.
4485 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4486 * @param TIMx Timer instance
4487 * @retval None
4488 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4489 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4490 {
4491 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4492 }
4493
4494 /**
4495 * @brief Generate trigger event.
4496 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4497 * @param TIMx Timer instance
4498 * @retval None
4499 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4500 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4501 {
4502 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4503 }
4504
4505 /**
4506 * @brief Generate break event.
4507 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4508 * @param TIMx Timer instance
4509 * @retval None
4510 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4511 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4512 {
4513 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4514 }
4515
4516 #if defined(TIM_EGR_B2G)
4517 /**
4518 * @brief Generate break 2 event.
4519 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4520 * @param TIMx Timer instance
4521 * @retval None
4522 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4523 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4524 {
4525 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4526 }
4527
4528 #endif /* TIM_EGR_B2G */
4529 /**
4530 * @}
4531 */
4532
4533 #if defined(USE_FULL_LL_DRIVER)
4534 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4535 * @{
4536 */
4537
4538 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4539 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4540 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4541 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4542 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4543 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4544 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4545 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4546 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4547 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4548 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4549 /**
4550 * @}
4551 */
4552 #endif /* USE_FULL_LL_DRIVER */
4553
4554 /**
4555 * @}
4556 */
4557
4558 /**
4559 * @}
4560 */
4561
4562 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
4563
4564 /**
4565 * @}
4566 */
4567
4568 #ifdef __cplusplus
4569 }
4570 #endif
4571
4572 #endif /* __STM32WB0x_LL_TIM_H */
4573
