1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WB0x_LL_LPUART_H
21 #define STM32WB0x_LL_LPUART_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wb0x.h"
29
30 /** @addtogroup STM32WB0x_LL_Driver
31 * @{
32 */
33
34 #if defined (LPUART1)
35
36 /** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
43 * @{
44 */
45 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
46 static const uint16_t LPUART_PRESCALER_TAB[] =
47 {
48 (uint16_t)1,
49 (uint16_t)2,
50 (uint16_t)4,
51 (uint16_t)6,
52 (uint16_t)8,
53 (uint16_t)10,
54 (uint16_t)12,
55 (uint16_t)16,
56 (uint16_t)32,
57 (uint16_t)64,
58 (uint16_t)128,
59 (uint16_t)256
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
67 * @{
68 */
69 /* Defines used in Baud Rate related macros and corresponding register setting computation */
70 #define LPUART_LPUARTDIV_FREQ_MUL 256U
71 #define LPUART_BRR_MASK 0x000FFFFFU
72 #define LPUART_BRR_MIN_VALUE 0x00000300U
73 /**
74 * @}
75 */
76
77
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
91 * @{
92 */
93
94 /**
95 * @brief LL LPUART Init Structure definition
96 */
97 typedef struct
98 {
99 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
100 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
101
102 This feature can be modified afterwards using unitary
103 function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary
108 function @ref LL_LPUART_SetBaudRate().*/
109
110 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
111 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
112
113 This feature can be modified afterwards using unitary
114 function @ref LL_LPUART_SetDataWidth().*/
115
116 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
117 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPUART_SetStopBitsLength().*/
121
122 uint32_t Parity; /*!< Specifies the parity mode.
123 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
124
125 This feature can be modified afterwards using unitary
126 function @ref LL_LPUART_SetParity().*/
127
128 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
129 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPUART_SetTransferDirection().*/
133
134 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
135 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
136
137 This feature can be modified afterwards using unitary
138 function @ref LL_LPUART_SetHWFlowCtrl().*/
139
140 } LL_LPUART_InitTypeDef;
141
142 /**
143 * @}
144 */
145 #endif /* USE_FULL_LL_DRIVER */
146
147 /* Exported constants --------------------------------------------------------*/
148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
149 * @{
150 */
151
152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
153 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
154 * @{
155 */
156 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
157 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
158 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
159 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
160 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
161 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
162 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
163 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
164 #if defined(USART_CR3_WUFIE)
165 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
166 #endif /* USART_CR3_WUFIE */
167 /**
168 * @}
169 */
170
171 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
172 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
173 * @{
174 */
175 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
176 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
177 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
178 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
179 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
180 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
181 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
182 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
183 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
184 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
185 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
186 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
187 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
188 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
189 #if defined(USART_CR3_WUFIE)
190 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
191 #endif /* USART_CR3_WUFIE */
192 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
193 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
194 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
195 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
196 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
197 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
198 /**
199 * @}
200 */
201
202 /** @defgroup LPUART_LL_EC_IT IT Defines
203 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
204 * @{
205 */
206 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
207 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
208 interrupt enable */
209 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
210 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
211 not full interrupt enable */
212 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
213 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
214 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
215 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
216 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
217 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
218 #if defined(USART_CR3_WUFIE)
219 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
220 #endif /* USART_CR3_WUFIE */
221 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
222 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
223 /**
224 * @}
225 */
226
227 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
228 * @{
229 */
230 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
231 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
232 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
233 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
234 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
235 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
236 /**
237 * @}
238 */
239
240 /** @defgroup LPUART_LL_EC_DIRECTION Direction
241 * @{
242 */
243 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
244 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
245 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
246 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
247 /**
248 * @}
249 */
250
251 /** @defgroup LPUART_LL_EC_PARITY Parity Control
252 * @{
253 */
254 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
255 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
256 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
257 /**
258 * @}
259 */
260
261 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
262 * @{
263 */
264 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
265 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
266 /**
267 * @}
268 */
269
270 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
271 * @{
272 */
273 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
274 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
275 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
276 /**
277 * @}
278 */
279
280 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
281 * @{
282 */
283 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
284 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
285 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
286 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
287 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
288 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
289 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
290 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
291 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
292 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
293 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
294 USART_PRESC_PRESCALER_1 |\
295 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
296 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
297 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
298 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
299 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
300 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
301 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
302 USART_PRESC_PRESCALER_1 |\
303 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
304 /**
305 * @}
306 */
307
308 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
309 * @{
310 */
311 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
312 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
313 /**
314 * @}
315 */
316
317 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
318 * @{
319 */
320 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
321 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
322 /**
323 * @}
324 */
325
326 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
327 * @{
328 */
329 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
330 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
331 /**
332 * @}
333 */
334
335 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
336 * @{
337 */
338 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
339 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
340 /**
341 * @}
342 */
343
344 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
345 * @{
346 */
347 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
348 in positive/direct logic. (1=H, 0=L) */
349 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
350 in negative/inverse logic. (1=L, 0=H).
351 The parity bit is also inverted. */
352 /**
353 * @}
354 */
355
356 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
357 * @{
358 */
359 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
360 following the start bit */
361 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
362 following the start bit */
363 /**
364 * @}
365 */
366
367 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
368 * @{
369 */
370 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
371 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
372 /**
373 * @}
374 */
375
376 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
377 * @{
378 */
379 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
380 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
381 when there is space in the receive buffer */
382 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
383 when the nCTS input is asserted (tied to 0)*/
384 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
385 /**
386 * @}
387 */
388
389 #if defined(USART_CR3_WUS)
390 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
391 * @{
392 */
393 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
394 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
395 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
396 /**
397 * @}
398 */
399
400 #endif /* USART_CR3_WUS */
401 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
402 * @{
403 */
404 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
405 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
406 /**
407 * @}
408 */
409
410 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
411 * @{
412 */
413 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
414 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
415 /**
416 * @}
417 */
418
419 /**
420 * @}
421 */
422
423 /* Exported macro ------------------------------------------------------------*/
424 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
425 * @{
426 */
427
428 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
429 * @{
430 */
431
432 /**
433 * @brief Write a value in LPUART register
434 * @param __INSTANCE__ LPUART Instance
435 * @param __REG__ Register to be written
436 * @param __VALUE__ Value to be written in the register
437 * @retval None
438 */
439 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
440
441 /**
442 * @brief Read a value in LPUART register
443 * @param __INSTANCE__ LPUART Instance
444 * @param __REG__ Register to be read
445 * @retval Register value
446 */
447 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
448 /**
449 * @}
450 */
451
452 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
453 * @{
454 */
455
456 /**
457 * @brief Compute LPUARTDIV value according to Peripheral Clock and
458 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
459 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
460 * @param __PRESCALER__ This parameter can be one of the following values:
461 * @arg @ref LL_LPUART_PRESCALER_DIV1
462 * @arg @ref LL_LPUART_PRESCALER_DIV2
463 * @arg @ref LL_LPUART_PRESCALER_DIV4
464 * @arg @ref LL_LPUART_PRESCALER_DIV6
465 * @arg @ref LL_LPUART_PRESCALER_DIV8
466 * @arg @ref LL_LPUART_PRESCALER_DIV10
467 * @arg @ref LL_LPUART_PRESCALER_DIV12
468 * @arg @ref LL_LPUART_PRESCALER_DIV16
469 * @arg @ref LL_LPUART_PRESCALER_DIV32
470 * @arg @ref LL_LPUART_PRESCALER_DIV64
471 * @arg @ref LL_LPUART_PRESCALER_DIV128
472 * @arg @ref LL_LPUART_PRESCALER_DIV256
473 * @param __BAUDRATE__ Baud Rate value to achieve
474 * @retval LPUARTDIV value to be used for BRR register filling
475 */
476 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
477 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
478 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
479
480 /**
481 * @}
482 */
483
484 /**
485 * @}
486 */
487
488 /* Exported functions --------------------------------------------------------*/
489 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
490 * @{
491 */
492
493 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
494 * @{
495 */
496
497 /**
498 * @brief LPUART Enable
499 * @rmtoll CR1 UE LL_LPUART_Enable
500 * @param LPUARTx LPUART Instance
501 * @retval None
502 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)503 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
504 {
505 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
506 }
507
508 /**
509 * @brief LPUART Disable
510 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
511 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
512 * flags, in the LPUARTx_ISR are set to their default values.
513 * @note In order to go into low-power mode without generating errors on the line,
514 * the TE bit must be reset before and the software must wait
515 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
516 * The DMA requests are also reset when UE = 0 so the DMA channel must
517 * be disabled before resetting the UE bit.
518 * @rmtoll CR1 UE LL_LPUART_Disable
519 * @param LPUARTx LPUART Instance
520 * @retval None
521 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)522 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
523 {
524 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
525 }
526
527 /**
528 * @brief Indicate if LPUART is enabled
529 * @rmtoll CR1 UE LL_LPUART_IsEnabled
530 * @param LPUARTx LPUART Instance
531 * @retval State of bit (1 or 0).
532 */
LL_LPUART_IsEnabled(const USART_TypeDef * LPUARTx)533 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
534 {
535 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
536 }
537
538 /**
539 * @brief FIFO Mode Enable
540 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
541 * @param LPUARTx LPUART Instance
542 * @retval None
543 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)544 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
545 {
546 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
547 }
548
549 /**
550 * @brief FIFO Mode Disable
551 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
552 * @param LPUARTx LPUART Instance
553 * @retval None
554 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)555 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
556 {
557 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
558 }
559
560 /**
561 * @brief Indicate if FIFO Mode is enabled
562 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
563 * @param LPUARTx LPUART Instance
564 * @retval State of bit (1 or 0).
565 */
LL_LPUART_IsEnabledFIFO(const USART_TypeDef * LPUARTx)566 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
567 {
568 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
569 }
570
571 /**
572 * @brief Configure TX FIFO Threshold
573 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
574 * @param LPUARTx LPUART Instance
575 * @param Threshold This parameter can be one of the following values:
576 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
577 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
578 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
579 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
580 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
581 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
582 * @retval None
583 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)584 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
585 {
586 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
587 }
588
589 /**
590 * @brief Return TX FIFO Threshold Configuration
591 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
592 * @param LPUARTx LPUART Instance
593 * @retval Returned value can be one of the following values:
594 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
595 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
596 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
597 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
598 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
599 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
600 */
LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef * LPUARTx)601 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
602 {
603 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
604 }
605
606 /**
607 * @brief Configure RX FIFO Threshold
608 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
609 * @param LPUARTx LPUART Instance
610 * @param Threshold This parameter can be one of the following values:
611 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
612 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
613 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
614 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
615 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
616 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
617 * @retval None
618 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)619 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
620 {
621 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
622 }
623
624 /**
625 * @brief Return RX FIFO Threshold Configuration
626 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
627 * @param LPUARTx LPUART Instance
628 * @retval Returned value can be one of the following values:
629 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
630 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
631 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
632 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
633 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
634 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
635 */
LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef * LPUARTx)636 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
637 {
638 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
639 }
640
641 /**
642 * @brief Configure TX and RX FIFOs Threshold
643 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
644 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
645 * @param LPUARTx LPUART Instance
646 * @param TXThreshold This parameter can be one of the following values:
647 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
648 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
649 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
650 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
651 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
652 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
653 * @param RXThreshold This parameter can be one of the following values:
654 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
655 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
656 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
657 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
658 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
659 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
660 * @retval None
661 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)662 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
663 {
664 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
665 (RXThreshold << USART_CR3_RXFTCFG_Pos));
666 }
667
668 #if defined(USART_CR1_UESM)
669 /**
670 * @brief LPUART enabled in STOP Mode
671 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
672 * LPUART clock selection is HSI or LSE in RCC.
673 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
674 * @param LPUARTx LPUART Instance
675 * @retval None
676 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)677 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
678 {
679 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
680 }
681
682 /**
683 * @brief LPUART disabled in STOP Mode
684 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
685 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
686 * @param LPUARTx LPUART Instance
687 * @retval None
688 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)689 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
690 {
691 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
692 }
693
694 /**
695 * @brief Indicate if LPUART is enabled in STOP Mode
696 * (able to wake up MCU from Stop mode or not)
697 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
698 * @param LPUARTx LPUART Instance
699 * @retval State of bit (1 or 0).
700 */
LL_LPUART_IsEnabledInStopMode(const USART_TypeDef * LPUARTx)701 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
702 {
703 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
704 }
705
706 #endif /* USART_CR1_UESM */
707 /**
708 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
709 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
710 * @param LPUARTx LPUART Instance
711 * @retval None
712 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)713 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
714 {
715 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
716 }
717
718 /**
719 * @brief Receiver Disable
720 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
721 * @param LPUARTx LPUART Instance
722 * @retval None
723 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)724 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
725 {
726 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
727 }
728
729 /**
730 * @brief Transmitter Enable
731 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
732 * @param LPUARTx LPUART Instance
733 * @retval None
734 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)735 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
736 {
737 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
738 }
739
740 /**
741 * @brief Transmitter Disable
742 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
743 * @param LPUARTx LPUART Instance
744 * @retval None
745 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)746 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
747 {
748 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
749 }
750
751 /**
752 * @brief Configure simultaneously enabled/disabled states
753 * of Transmitter and Receiver
754 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
755 * CR1 TE LL_LPUART_SetTransferDirection
756 * @param LPUARTx LPUART Instance
757 * @param TransferDirection This parameter can be one of the following values:
758 * @arg @ref LL_LPUART_DIRECTION_NONE
759 * @arg @ref LL_LPUART_DIRECTION_RX
760 * @arg @ref LL_LPUART_DIRECTION_TX
761 * @arg @ref LL_LPUART_DIRECTION_TX_RX
762 * @retval None
763 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)764 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
765 {
766 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
767 }
768
769 /**
770 * @brief Return enabled/disabled states of Transmitter and Receiver
771 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
772 * CR1 TE LL_LPUART_GetTransferDirection
773 * @param LPUARTx LPUART Instance
774 * @retval Returned value can be one of the following values:
775 * @arg @ref LL_LPUART_DIRECTION_NONE
776 * @arg @ref LL_LPUART_DIRECTION_RX
777 * @arg @ref LL_LPUART_DIRECTION_TX
778 * @arg @ref LL_LPUART_DIRECTION_TX_RX
779 */
LL_LPUART_GetTransferDirection(const USART_TypeDef * LPUARTx)780 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
781 {
782 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
783 }
784
785 /**
786 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
787 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
788 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
789 * (depending on data width) and parity is checked on the received data.
790 * @rmtoll CR1 PS LL_LPUART_SetParity\n
791 * CR1 PCE LL_LPUART_SetParity
792 * @param LPUARTx LPUART Instance
793 * @param Parity This parameter can be one of the following values:
794 * @arg @ref LL_LPUART_PARITY_NONE
795 * @arg @ref LL_LPUART_PARITY_EVEN
796 * @arg @ref LL_LPUART_PARITY_ODD
797 * @retval None
798 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)799 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
800 {
801 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
802 }
803
804 /**
805 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
806 * @rmtoll CR1 PS LL_LPUART_GetParity\n
807 * CR1 PCE LL_LPUART_GetParity
808 * @param LPUARTx LPUART Instance
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_LPUART_PARITY_NONE
811 * @arg @ref LL_LPUART_PARITY_EVEN
812 * @arg @ref LL_LPUART_PARITY_ODD
813 */
LL_LPUART_GetParity(const USART_TypeDef * LPUARTx)814 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
815 {
816 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
817 }
818
819 /**
820 * @brief Set Receiver Wake Up method from Mute mode.
821 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
822 * @param LPUARTx LPUART Instance
823 * @param Method This parameter can be one of the following values:
824 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
825 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
826 * @retval None
827 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)828 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
829 {
830 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
831 }
832
833 /**
834 * @brief Return Receiver Wake Up method from Mute mode
835 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
836 * @param LPUARTx LPUART Instance
837 * @retval Returned value can be one of the following values:
838 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
839 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
840 */
LL_LPUART_GetWakeUpMethod(const USART_TypeDef * LPUARTx)841 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
842 {
843 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
844 }
845
846 /**
847 * @brief Set Word length (nb of data bits, excluding start and stop bits)
848 * @rmtoll CR1 M LL_LPUART_SetDataWidth
849 * @param LPUARTx LPUART Instance
850 * @param DataWidth This parameter can be one of the following values:
851 * @arg @ref LL_LPUART_DATAWIDTH_7B
852 * @arg @ref LL_LPUART_DATAWIDTH_8B
853 * @arg @ref LL_LPUART_DATAWIDTH_9B
854 * @retval None
855 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)856 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
857 {
858 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
859 }
860
861 /**
862 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
863 * @rmtoll CR1 M LL_LPUART_GetDataWidth
864 * @param LPUARTx LPUART Instance
865 * @retval Returned value can be one of the following values:
866 * @arg @ref LL_LPUART_DATAWIDTH_7B
867 * @arg @ref LL_LPUART_DATAWIDTH_8B
868 * @arg @ref LL_LPUART_DATAWIDTH_9B
869 */
LL_LPUART_GetDataWidth(const USART_TypeDef * LPUARTx)870 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
871 {
872 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
873 }
874
875 /**
876 * @brief Allow switch between Mute Mode and Active mode
877 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
878 * @param LPUARTx LPUART Instance
879 * @retval None
880 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)881 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
882 {
883 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
884 }
885
886 /**
887 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
888 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
889 * @param LPUARTx LPUART Instance
890 * @retval None
891 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)892 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
893 {
894 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
895 }
896
897 /**
898 * @brief Indicate if switch between Mute Mode and Active mode is allowed
899 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
900 * @param LPUARTx LPUART Instance
901 * @retval State of bit (1 or 0).
902 */
LL_LPUART_IsEnabledMuteMode(const USART_TypeDef * LPUARTx)903 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
904 {
905 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
906 }
907
908 /**
909 * @brief Configure Clock source prescaler for baudrate generator and oversampling
910 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
911 * @param LPUARTx LPUART Instance
912 * @param PrescalerValue This parameter can be one of the following values:
913 * @arg @ref LL_LPUART_PRESCALER_DIV1
914 * @arg @ref LL_LPUART_PRESCALER_DIV2
915 * @arg @ref LL_LPUART_PRESCALER_DIV4
916 * @arg @ref LL_LPUART_PRESCALER_DIV6
917 * @arg @ref LL_LPUART_PRESCALER_DIV8
918 * @arg @ref LL_LPUART_PRESCALER_DIV10
919 * @arg @ref LL_LPUART_PRESCALER_DIV12
920 * @arg @ref LL_LPUART_PRESCALER_DIV16
921 * @arg @ref LL_LPUART_PRESCALER_DIV32
922 * @arg @ref LL_LPUART_PRESCALER_DIV64
923 * @arg @ref LL_LPUART_PRESCALER_DIV128
924 * @arg @ref LL_LPUART_PRESCALER_DIV256
925 * @retval None
926 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)927 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
928 {
929 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
930 }
931
932 /**
933 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
934 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
935 * @param LPUARTx LPUART Instance
936 * @retval Returned value can be one of the following values:
937 * @arg @ref LL_LPUART_PRESCALER_DIV1
938 * @arg @ref LL_LPUART_PRESCALER_DIV2
939 * @arg @ref LL_LPUART_PRESCALER_DIV4
940 * @arg @ref LL_LPUART_PRESCALER_DIV6
941 * @arg @ref LL_LPUART_PRESCALER_DIV8
942 * @arg @ref LL_LPUART_PRESCALER_DIV10
943 * @arg @ref LL_LPUART_PRESCALER_DIV12
944 * @arg @ref LL_LPUART_PRESCALER_DIV16
945 * @arg @ref LL_LPUART_PRESCALER_DIV32
946 * @arg @ref LL_LPUART_PRESCALER_DIV64
947 * @arg @ref LL_LPUART_PRESCALER_DIV128
948 * @arg @ref LL_LPUART_PRESCALER_DIV256
949 */
LL_LPUART_GetPrescaler(const USART_TypeDef * LPUARTx)950 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
951 {
952 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
953 }
954
955 /**
956 * @brief Set the length of the stop bits
957 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
958 * @param LPUARTx LPUART Instance
959 * @param StopBits This parameter can be one of the following values:
960 * @arg @ref LL_LPUART_STOPBITS_1
961 * @arg @ref LL_LPUART_STOPBITS_2
962 * @retval None
963 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)964 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
965 {
966 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
967 }
968
969 /**
970 * @brief Retrieve the length of the stop bits
971 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
972 * @param LPUARTx LPUART Instance
973 * @retval Returned value can be one of the following values:
974 * @arg @ref LL_LPUART_STOPBITS_1
975 * @arg @ref LL_LPUART_STOPBITS_2
976 */
LL_LPUART_GetStopBitsLength(const USART_TypeDef * LPUARTx)977 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
978 {
979 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
980 }
981
982 /**
983 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
984 * @note Call of this function is equivalent to following function call sequence :
985 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
986 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
987 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
988 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
989 * CR1 PCE LL_LPUART_ConfigCharacter\n
990 * CR1 M LL_LPUART_ConfigCharacter\n
991 * CR2 STOP LL_LPUART_ConfigCharacter
992 * @param LPUARTx LPUART Instance
993 * @param DataWidth This parameter can be one of the following values:
994 * @arg @ref LL_LPUART_DATAWIDTH_7B
995 * @arg @ref LL_LPUART_DATAWIDTH_8B
996 * @arg @ref LL_LPUART_DATAWIDTH_9B
997 * @param Parity This parameter can be one of the following values:
998 * @arg @ref LL_LPUART_PARITY_NONE
999 * @arg @ref LL_LPUART_PARITY_EVEN
1000 * @arg @ref LL_LPUART_PARITY_ODD
1001 * @param StopBits This parameter can be one of the following values:
1002 * @arg @ref LL_LPUART_STOPBITS_1
1003 * @arg @ref LL_LPUART_STOPBITS_2
1004 * @retval None
1005 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)1006 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1007 uint32_t StopBits)
1008 {
1009 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1010 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1011 }
1012
1013 /**
1014 * @brief Configure TX/RX pins swapping setting.
1015 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1016 * @param LPUARTx LPUART Instance
1017 * @param SwapConfig This parameter can be one of the following values:
1018 * @arg @ref LL_LPUART_TXRX_STANDARD
1019 * @arg @ref LL_LPUART_TXRX_SWAPPED
1020 * @retval None
1021 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1022 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1023 {
1024 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1025 }
1026
1027 /**
1028 * @brief Retrieve TX/RX pins swapping configuration.
1029 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1030 * @param LPUARTx LPUART Instance
1031 * @retval Returned value can be one of the following values:
1032 * @arg @ref LL_LPUART_TXRX_STANDARD
1033 * @arg @ref LL_LPUART_TXRX_SWAPPED
1034 */
LL_LPUART_GetTXRXSwap(const USART_TypeDef * LPUARTx)1035 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1036 {
1037 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1038 }
1039
1040 /**
1041 * @brief Configure RX pin active level logic
1042 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1043 * @param LPUARTx LPUART Instance
1044 * @param PinInvMethod This parameter can be one of the following values:
1045 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1046 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1047 * @retval None
1048 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1049 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1050 {
1051 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1052 }
1053
1054 /**
1055 * @brief Retrieve RX pin active level logic configuration
1056 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1057 * @param LPUARTx LPUART Instance
1058 * @retval Returned value can be one of the following values:
1059 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1060 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1061 */
LL_LPUART_GetRXPinLevel(const USART_TypeDef * LPUARTx)1062 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1063 {
1064 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1065 }
1066
1067 /**
1068 * @brief Configure TX pin active level logic
1069 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1070 * @param LPUARTx LPUART Instance
1071 * @param PinInvMethod This parameter can be one of the following values:
1072 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1073 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1074 * @retval None
1075 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1076 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1077 {
1078 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1079 }
1080
1081 /**
1082 * @brief Retrieve TX pin active level logic configuration
1083 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1084 * @param LPUARTx LPUART Instance
1085 * @retval Returned value can be one of the following values:
1086 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1087 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1088 */
LL_LPUART_GetTXPinLevel(const USART_TypeDef * LPUARTx)1089 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1090 {
1091 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1092 }
1093
1094 /**
1095 * @brief Configure Binary data logic.
1096 *
1097 * @note Allow to define how Logical data from the data register are send/received :
1098 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1099 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1100 * @param LPUARTx LPUART Instance
1101 * @param DataLogic This parameter can be one of the following values:
1102 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1103 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1104 * @retval None
1105 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1106 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1107 {
1108 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1109 }
1110
1111 /**
1112 * @brief Retrieve Binary data configuration
1113 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1114 * @param LPUARTx LPUART Instance
1115 * @retval Returned value can be one of the following values:
1116 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1117 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1118 */
LL_LPUART_GetBinaryDataLogic(const USART_TypeDef * LPUARTx)1119 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1120 {
1121 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1122 }
1123
1124 /**
1125 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1126 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1127 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1128 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1129 * @param LPUARTx LPUART Instance
1130 * @param BitOrder This parameter can be one of the following values:
1131 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1132 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1133 * @retval None
1134 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1135 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1136 {
1137 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1138 }
1139
1140 /**
1141 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1142 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1143 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1144 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1145 * @param LPUARTx LPUART Instance
1146 * @retval Returned value can be one of the following values:
1147 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1148 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1149 */
LL_LPUART_GetTransferBitOrder(const USART_TypeDef * LPUARTx)1150 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1151 {
1152 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1153 }
1154
1155 /**
1156 * @brief Set Address of the LPUART node.
1157 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1158 * for wake up with address mark detection.
1159 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1160 * (b7-b4 should be set to 0)
1161 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1162 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1163 * for wake up with 7-bit address mark detection.
1164 * The MSB of the character sent by the transmitter should be equal to 1.
1165 * It may also be used for character detection during normal reception,
1166 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1167 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1168 * value and CMF flag is set on match)
1169 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1170 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1171 * @param LPUARTx LPUART Instance
1172 * @param AddressLen This parameter can be one of the following values:
1173 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1174 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1175 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1176 * @retval None
1177 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1178 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1179 {
1180 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1181 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1182 }
1183
1184 /**
1185 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1186 * @note If 4-bit Address Detection is selected in ADDM7,
1187 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1188 * If 7-bit Address Detection is selected in ADDM7,
1189 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1190 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1191 * @param LPUARTx LPUART Instance
1192 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1193 */
LL_LPUART_GetNodeAddress(const USART_TypeDef * LPUARTx)1194 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1195 {
1196 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1197 }
1198
1199 /**
1200 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1201 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1202 * @param LPUARTx LPUART Instance
1203 * @retval Returned value can be one of the following values:
1204 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1205 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1206 */
LL_LPUART_GetNodeAddressLen(const USART_TypeDef * LPUARTx)1207 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1208 {
1209 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1210 }
1211
1212 /**
1213 * @brief Enable RTS HW Flow Control
1214 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1215 * @param LPUARTx LPUART Instance
1216 * @retval None
1217 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1218 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1219 {
1220 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1221 }
1222
1223 /**
1224 * @brief Disable RTS HW Flow Control
1225 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1226 * @param LPUARTx LPUART Instance
1227 * @retval None
1228 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1229 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1230 {
1231 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1232 }
1233
1234 /**
1235 * @brief Enable CTS HW Flow Control
1236 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1237 * @param LPUARTx LPUART Instance
1238 * @retval None
1239 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1240 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1241 {
1242 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1243 }
1244
1245 /**
1246 * @brief Disable CTS HW Flow Control
1247 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1248 * @param LPUARTx LPUART Instance
1249 * @retval None
1250 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1251 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1252 {
1253 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1254 }
1255
1256 /**
1257 * @brief Configure HW Flow Control mode (both CTS and RTS)
1258 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1259 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1260 * @param LPUARTx LPUART Instance
1261 * @param HardwareFlowControl This parameter can be one of the following values:
1262 * @arg @ref LL_LPUART_HWCONTROL_NONE
1263 * @arg @ref LL_LPUART_HWCONTROL_RTS
1264 * @arg @ref LL_LPUART_HWCONTROL_CTS
1265 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1266 * @retval None
1267 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1268 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1269 {
1270 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1271 }
1272
1273 /**
1274 * @brief Return HW Flow Control configuration (both CTS and RTS)
1275 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1276 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1277 * @param LPUARTx LPUART Instance
1278 * @retval Returned value can be one of the following values:
1279 * @arg @ref LL_LPUART_HWCONTROL_NONE
1280 * @arg @ref LL_LPUART_HWCONTROL_RTS
1281 * @arg @ref LL_LPUART_HWCONTROL_CTS
1282 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1283 */
LL_LPUART_GetHWFlowCtrl(const USART_TypeDef * LPUARTx)1284 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1285 {
1286 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1287 }
1288
1289 /**
1290 * @brief Enable Overrun detection
1291 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1292 * @param LPUARTx LPUART Instance
1293 * @retval None
1294 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1295 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1296 {
1297 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1298 }
1299
1300 /**
1301 * @brief Disable Overrun detection
1302 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1303 * @param LPUARTx LPUART Instance
1304 * @retval None
1305 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1306 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1307 {
1308 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1309 }
1310
1311 /**
1312 * @brief Indicate if Overrun detection is enabled
1313 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1314 * @param LPUARTx LPUART Instance
1315 * @retval State of bit (1 or 0).
1316 */
LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef * LPUARTx)1317 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1318 {
1319 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1320 }
1321
1322 #if defined(USART_CR3_WUS)
1323 /**
1324 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1325 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1326 * @param LPUARTx LPUART Instance
1327 * @param Type This parameter can be one of the following values:
1328 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1329 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1330 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1331 * @retval None
1332 */
LL_LPUART_SetWKUPType(USART_TypeDef * LPUARTx,uint32_t Type)1333 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1334 {
1335 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1336 }
1337
1338 /**
1339 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1340 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1341 * @param LPUARTx LPUART Instance
1342 * @retval Returned value can be one of the following values:
1343 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1344 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1345 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1346 */
LL_LPUART_GetWKUPType(const USART_TypeDef * LPUARTx)1347 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
1348 {
1349 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1350 }
1351
1352 #endif /* USART_CR3_WUS */
1353 /**
1354 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1355 *
1356 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1357 * according to used Peripheral Clock and expected Baud Rate values
1358 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1359 * (Baud rate value != 0).
1360 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1361 * a care should be taken when generating high baud rates using high PeriphClk
1362 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1363 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1364 * @param LPUARTx LPUART Instance
1365 * @param PeriphClk Peripheral Clock
1366 * @param PrescalerValue This parameter can be one of the following values:
1367 * @arg @ref LL_LPUART_PRESCALER_DIV1
1368 * @arg @ref LL_LPUART_PRESCALER_DIV2
1369 * @arg @ref LL_LPUART_PRESCALER_DIV4
1370 * @arg @ref LL_LPUART_PRESCALER_DIV6
1371 * @arg @ref LL_LPUART_PRESCALER_DIV8
1372 * @arg @ref LL_LPUART_PRESCALER_DIV10
1373 * @arg @ref LL_LPUART_PRESCALER_DIV12
1374 * @arg @ref LL_LPUART_PRESCALER_DIV16
1375 * @arg @ref LL_LPUART_PRESCALER_DIV32
1376 * @arg @ref LL_LPUART_PRESCALER_DIV64
1377 * @arg @ref LL_LPUART_PRESCALER_DIV128
1378 * @arg @ref LL_LPUART_PRESCALER_DIV256
1379 * @param BaudRate Baud Rate
1380 * @retval None
1381 */
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1382 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1383 uint32_t BaudRate)
1384 {
1385 if (BaudRate != 0U)
1386 {
1387 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1388 }
1389 }
1390
1391 /**
1392 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1393 * (full BRR content), and to used Peripheral Clock values
1394 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1395 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1396 * @param LPUARTx LPUART Instance
1397 * @param PeriphClk Peripheral Clock
1398 * @param PrescalerValue This parameter can be one of the following values:
1399 * @arg @ref LL_LPUART_PRESCALER_DIV1
1400 * @arg @ref LL_LPUART_PRESCALER_DIV2
1401 * @arg @ref LL_LPUART_PRESCALER_DIV4
1402 * @arg @ref LL_LPUART_PRESCALER_DIV6
1403 * @arg @ref LL_LPUART_PRESCALER_DIV8
1404 * @arg @ref LL_LPUART_PRESCALER_DIV10
1405 * @arg @ref LL_LPUART_PRESCALER_DIV12
1406 * @arg @ref LL_LPUART_PRESCALER_DIV16
1407 * @arg @ref LL_LPUART_PRESCALER_DIV32
1408 * @arg @ref LL_LPUART_PRESCALER_DIV64
1409 * @arg @ref LL_LPUART_PRESCALER_DIV128
1410 * @arg @ref LL_LPUART_PRESCALER_DIV256
1411 * @retval Baud Rate
1412 */
LL_LPUART_GetBaudRate(const USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1413 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1414 uint32_t PrescalerValue)
1415 {
1416 uint32_t lpuartdiv;
1417 uint32_t brrresult;
1418 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1419
1420 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1421
1422 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1423 {
1424 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1425 }
1426 else
1427 {
1428 brrresult = 0x0UL;
1429 }
1430
1431 return (brrresult);
1432 }
1433
1434 /**
1435 * @}
1436 */
1437
1438 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1439 * @{
1440 */
1441
1442 /**
1443 * @brief Enable Single Wire Half-Duplex mode
1444 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1445 * @param LPUARTx LPUART Instance
1446 * @retval None
1447 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1448 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1449 {
1450 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1451 }
1452
1453 /**
1454 * @brief Disable Single Wire Half-Duplex mode
1455 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1456 * @param LPUARTx LPUART Instance
1457 * @retval None
1458 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1459 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1460 {
1461 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1462 }
1463
1464 /**
1465 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1466 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1467 * @param LPUARTx LPUART Instance
1468 * @retval State of bit (1 or 0).
1469 */
LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef * LPUARTx)1470 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1471 {
1472 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1480 * @{
1481 */
1482
1483 /**
1484 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1485 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1486 * @param LPUARTx LPUART Instance
1487 * @param Time Value between Min_Data=0 and Max_Data=31
1488 * @retval None
1489 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1490 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1491 {
1492 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1493 }
1494
1495 /**
1496 * @brief Return DEDT (Driver Enable De-Assertion Time)
1497 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1498 * @param LPUARTx LPUART Instance
1499 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1500 */
LL_LPUART_GetDEDeassertionTime(const USART_TypeDef * LPUARTx)1501 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1502 {
1503 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1504 }
1505
1506 /**
1507 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1508 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1509 * @param LPUARTx LPUART Instance
1510 * @param Time Value between Min_Data=0 and Max_Data=31
1511 * @retval None
1512 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1513 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1514 {
1515 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1516 }
1517
1518 /**
1519 * @brief Return DEAT (Driver Enable Assertion Time)
1520 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1521 * @param LPUARTx LPUART Instance
1522 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1523 */
LL_LPUART_GetDEAssertionTime(const USART_TypeDef * LPUARTx)1524 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1525 {
1526 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1527 }
1528
1529 /**
1530 * @brief Enable Driver Enable (DE) Mode
1531 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1532 * @param LPUARTx LPUART Instance
1533 * @retval None
1534 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1535 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1536 {
1537 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1538 }
1539
1540 /**
1541 * @brief Disable Driver Enable (DE) Mode
1542 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1543 * @param LPUARTx LPUART Instance
1544 * @retval None
1545 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1546 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1547 {
1548 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1549 }
1550
1551 /**
1552 * @brief Indicate if Driver Enable (DE) Mode is enabled
1553 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1554 * @param LPUARTx LPUART Instance
1555 * @retval State of bit (1 or 0).
1556 */
LL_LPUART_IsEnabledDEMode(const USART_TypeDef * LPUARTx)1557 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1558 {
1559 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1560 }
1561
1562 /**
1563 * @brief Select Driver Enable Polarity
1564 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1565 * @param LPUARTx LPUART Instance
1566 * @param Polarity This parameter can be one of the following values:
1567 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1568 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1569 * @retval None
1570 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1571 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1572 {
1573 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1574 }
1575
1576 /**
1577 * @brief Return Driver Enable Polarity
1578 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1579 * @param LPUARTx LPUART Instance
1580 * @retval Returned value can be one of the following values:
1581 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1582 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1583 */
LL_LPUART_GetDESignalPolarity(const USART_TypeDef * LPUARTx)1584 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1585 {
1586 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1587 }
1588
1589 /**
1590 * @}
1591 */
1592
1593 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1594 * @{
1595 */
1596
1597 /**
1598 * @brief Check if the LPUART Parity Error Flag is set or not
1599 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1600 * @param LPUARTx LPUART Instance
1601 * @retval State of bit (1 or 0).
1602 */
LL_LPUART_IsActiveFlag_PE(const USART_TypeDef * LPUARTx)1603 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1604 {
1605 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1606 }
1607
1608 /**
1609 * @brief Check if the LPUART Framing Error Flag is set or not
1610 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1611 * @param LPUARTx LPUART Instance
1612 * @retval State of bit (1 or 0).
1613 */
LL_LPUART_IsActiveFlag_FE(const USART_TypeDef * LPUARTx)1614 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1615 {
1616 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1617 }
1618
1619 /**
1620 * @brief Check if the LPUART Noise error detected Flag is set or not
1621 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1622 * @param LPUARTx LPUART Instance
1623 * @retval State of bit (1 or 0).
1624 */
LL_LPUART_IsActiveFlag_NE(const USART_TypeDef * LPUARTx)1625 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1626 {
1627 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1628 }
1629
1630 /**
1631 * @brief Check if the LPUART OverRun Error Flag is set or not
1632 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1633 * @param LPUARTx LPUART Instance
1634 * @retval State of bit (1 or 0).
1635 */
LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef * LPUARTx)1636 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1637 {
1638 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1639 }
1640
1641 /**
1642 * @brief Check if the LPUART IDLE line detected Flag is set or not
1643 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1644 * @param LPUARTx LPUART Instance
1645 * @retval State of bit (1 or 0).
1646 */
LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef * LPUARTx)1647 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1648 {
1649 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1650 }
1651
1652 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
1653
1654 /**
1655 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1656 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1657 * @param LPUARTx LPUART Instance
1658 * @retval State of bit (1 or 0).
1659 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef * LPUARTx)1660 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1661 {
1662 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1663 }
1664
1665 /**
1666 * @brief Check if the LPUART Transmission Complete Flag is set or not
1667 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1668 * @param LPUARTx LPUART Instance
1669 * @retval State of bit (1 or 0).
1670 */
LL_LPUART_IsActiveFlag_TC(const USART_TypeDef * LPUARTx)1671 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1672 {
1673 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1674 }
1675
1676 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
1677
1678 /**
1679 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1680 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1681 * @param LPUARTx LPUART Instance
1682 * @retval State of bit (1 or 0).
1683 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef * LPUARTx)1684 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1685 {
1686 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1687 }
1688
1689 /**
1690 * @brief Check if the LPUART CTS interrupt Flag is set or not
1691 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1692 * @param LPUARTx LPUART Instance
1693 * @retval State of bit (1 or 0).
1694 */
LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef * LPUARTx)1695 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1696 {
1697 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1698 }
1699
1700 /**
1701 * @brief Check if the LPUART CTS Flag is set or not
1702 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1703 * @param LPUARTx LPUART Instance
1704 * @retval State of bit (1 or 0).
1705 */
LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef * LPUARTx)1706 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1707 {
1708 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1709 }
1710
1711 /**
1712 * @brief Check if the LPUART Busy Flag is set or not
1713 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1714 * @param LPUARTx LPUART Instance
1715 * @retval State of bit (1 or 0).
1716 */
LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef * LPUARTx)1717 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1718 {
1719 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1720 }
1721
1722 /**
1723 * @brief Check if the LPUART Character Match Flag is set or not
1724 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1725 * @param LPUARTx LPUART Instance
1726 * @retval State of bit (1 or 0).
1727 */
LL_LPUART_IsActiveFlag_CM(const USART_TypeDef * LPUARTx)1728 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1729 {
1730 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1731 }
1732
1733 /**
1734 * @brief Check if the LPUART Send Break Flag is set or not
1735 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1736 * @param LPUARTx LPUART Instance
1737 * @retval State of bit (1 or 0).
1738 */
LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef * LPUARTx)1739 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1740 {
1741 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1742 }
1743
1744 /**
1745 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1746 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1747 * @param LPUARTx LPUART Instance
1748 * @retval State of bit (1 or 0).
1749 */
LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef * LPUARTx)1750 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1751 {
1752 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1753 }
1754
1755 #if defined(USART_CR3_WUFIE)
1756 /**
1757 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1758 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1759 * @param LPUARTx LPUART Instance
1760 * @retval State of bit (1 or 0).
1761 */
LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef * LPUARTx)1762 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
1763 {
1764 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1765 }
1766
1767 #endif /* USART_CR3_WUFIE */
1768 /**
1769 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1770 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1771 * @param LPUARTx LPUART Instance
1772 * @retval State of bit (1 or 0).
1773 */
LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef * LPUARTx)1774 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1775 {
1776 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1777 }
1778
1779 /**
1780 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1781 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1782 * @param LPUARTx LPUART Instance
1783 * @retval State of bit (1 or 0).
1784 */
LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef * LPUARTx)1785 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1786 {
1787 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1788 }
1789
1790 /**
1791 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1792 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1793 * @param LPUARTx LPUART Instance
1794 * @retval State of bit (1 or 0).
1795 */
LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef * LPUARTx)1796 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1797 {
1798 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1799 }
1800
1801 /**
1802 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1803 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1804 * @param LPUARTx LPUART Instance
1805 * @retval State of bit (1 or 0).
1806 */
LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef * LPUARTx)1807 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1808 {
1809 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1810 }
1811
1812 /**
1813 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1814 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1815 * @param LPUARTx LPUART Instance
1816 * @retval State of bit (1 or 0).
1817 */
LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef * LPUARTx)1818 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1819 {
1820 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1821 }
1822
1823 /**
1824 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1825 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1826 * @param LPUARTx LPUART Instance
1827 * @retval State of bit (1 or 0).
1828 */
LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef * LPUARTx)1829 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1830 {
1831 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1832 }
1833
1834 /**
1835 * @brief Clear Parity Error Flag
1836 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1837 * @param LPUARTx LPUART Instance
1838 * @retval None
1839 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1840 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1841 {
1842 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1843 }
1844
1845 /**
1846 * @brief Clear Framing Error Flag
1847 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1848 * @param LPUARTx LPUART Instance
1849 * @retval None
1850 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1851 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1852 {
1853 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1854 }
1855
1856 /**
1857 * @brief Clear Noise detected Flag
1858 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1859 * @param LPUARTx LPUART Instance
1860 * @retval None
1861 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1862 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1863 {
1864 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1865 }
1866
1867 /**
1868 * @brief Clear OverRun Error Flag
1869 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1870 * @param LPUARTx LPUART Instance
1871 * @retval None
1872 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1873 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1874 {
1875 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1876 }
1877
1878 /**
1879 * @brief Clear IDLE line detected Flag
1880 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1881 * @param LPUARTx LPUART Instance
1882 * @retval None
1883 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1884 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1885 {
1886 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1887 }
1888
1889 /**
1890 * @brief Clear Transmission Complete Flag
1891 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1892 * @param LPUARTx LPUART Instance
1893 * @retval None
1894 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1895 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1896 {
1897 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1898 }
1899
1900 /**
1901 * @brief Clear CTS Interrupt Flag
1902 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1903 * @param LPUARTx LPUART Instance
1904 * @retval None
1905 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)1906 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1907 {
1908 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1909 }
1910
1911 /**
1912 * @brief Clear Character Match Flag
1913 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1914 * @param LPUARTx LPUART Instance
1915 * @retval None
1916 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)1917 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1918 {
1919 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1920 }
1921
1922 #if defined(USART_CR3_WUFIE)
1923 /**
1924 * @brief Clear Wake Up from stop mode Flag
1925 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1926 * @param LPUARTx LPUART Instance
1927 * @retval None
1928 */
LL_LPUART_ClearFlag_WKUP(USART_TypeDef * LPUARTx)1929 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1930 {
1931 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1932 }
1933
1934 #endif /* USART_CR3_WUFIE */
1935 /**
1936 * @}
1937 */
1938
1939 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1940 * @{
1941 */
1942
1943 /**
1944 * @brief Enable IDLE Interrupt
1945 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1946 * @param LPUARTx LPUART Instance
1947 * @retval None
1948 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)1949 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1950 {
1951 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1952 }
1953
1954 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
1955
1956 /**
1957 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1958 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1959 * @param LPUARTx LPUART Instance
1960 * @retval None
1961 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)1962 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1963 {
1964 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1965 }
1966
1967 /**
1968 * @brief Enable Transmission Complete Interrupt
1969 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1970 * @param LPUARTx LPUART Instance
1971 * @retval None
1972 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)1973 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1974 {
1975 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1976 }
1977
1978 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
1979
1980 /**
1981 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1982 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1983 * @param LPUARTx LPUART Instance
1984 * @retval None
1985 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)1986 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1987 {
1988 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1989 }
1990
1991 /**
1992 * @brief Enable Parity Error Interrupt
1993 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1994 * @param LPUARTx LPUART Instance
1995 * @retval None
1996 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)1997 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1998 {
1999 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2000 }
2001
2002 /**
2003 * @brief Enable Character Match Interrupt
2004 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
2005 * @param LPUARTx LPUART Instance
2006 * @retval None
2007 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)2008 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
2009 {
2010 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2011 }
2012
2013 /**
2014 * @brief Enable TX FIFO Empty Interrupt
2015 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
2016 * @param LPUARTx LPUART Instance
2017 * @retval None
2018 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)2019 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2020 {
2021 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2022 }
2023
2024 /**
2025 * @brief Enable RX FIFO Full Interrupt
2026 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
2027 * @param LPUARTx LPUART Instance
2028 * @retval None
2029 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)2030 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2031 {
2032 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2033 }
2034
2035 /**
2036 * @brief Enable Error Interrupt
2037 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2038 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2039 * - 0: Interrupt is inhibited
2040 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2041 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2042 * @param LPUARTx LPUART Instance
2043 * @retval None
2044 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)2045 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2046 {
2047 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2048 }
2049
2050 /**
2051 * @brief Enable CTS Interrupt
2052 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2053 * @param LPUARTx LPUART Instance
2054 * @retval None
2055 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2056 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2057 {
2058 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2059 }
2060
2061 #if defined(USART_CR3_WUFIE)
2062 /**
2063 * @brief Enable Wake Up from Stop Mode Interrupt
2064 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2065 * @param LPUARTx LPUART Instance
2066 * @retval None
2067 */
LL_LPUART_EnableIT_WKUP(USART_TypeDef * LPUARTx)2068 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2069 {
2070 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2071 }
2072
2073 #endif /* USART_CR3_WUFIE */
2074 /**
2075 * @brief Enable TX FIFO Threshold Interrupt
2076 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2077 * @param LPUARTx LPUART Instance
2078 * @retval None
2079 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2080 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2081 {
2082 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2083 }
2084
2085 /**
2086 * @brief Enable RX FIFO Threshold Interrupt
2087 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2088 * @param LPUARTx LPUART Instance
2089 * @retval None
2090 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2091 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2092 {
2093 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2094 }
2095
2096 /**
2097 * @brief Disable IDLE Interrupt
2098 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2099 * @param LPUARTx LPUART Instance
2100 * @retval None
2101 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2102 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2103 {
2104 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2105 }
2106
2107 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2108
2109 /**
2110 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2111 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2112 * @param LPUARTx LPUART Instance
2113 * @retval None
2114 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2115 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2116 {
2117 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2118 }
2119
2120 /**
2121 * @brief Disable Transmission Complete Interrupt
2122 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2123 * @param LPUARTx LPUART Instance
2124 * @retval None
2125 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2126 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2127 {
2128 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2129 }
2130
2131 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
2132
2133 /**
2134 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2135 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2136 * @param LPUARTx LPUART Instance
2137 * @retval None
2138 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2139 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2140 {
2141 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2142 }
2143
2144 /**
2145 * @brief Disable Parity Error Interrupt
2146 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2147 * @param LPUARTx LPUART Instance
2148 * @retval None
2149 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2150 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2151 {
2152 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2153 }
2154
2155 /**
2156 * @brief Disable Character Match Interrupt
2157 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2158 * @param LPUARTx LPUART Instance
2159 * @retval None
2160 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2161 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2162 {
2163 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2164 }
2165
2166 /**
2167 * @brief Disable TX FIFO Empty Interrupt
2168 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2169 * @param LPUARTx LPUART Instance
2170 * @retval None
2171 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2172 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2173 {
2174 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2175 }
2176
2177 /**
2178 * @brief Disable RX FIFO Full Interrupt
2179 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2180 * @param LPUARTx LPUART Instance
2181 * @retval None
2182 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2183 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2184 {
2185 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2186 }
2187
2188 /**
2189 * @brief Disable Error Interrupt
2190 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2191 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2192 * - 0: Interrupt is inhibited
2193 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2194 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2195 * @param LPUARTx LPUART Instance
2196 * @retval None
2197 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2198 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2199 {
2200 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2201 }
2202
2203 /**
2204 * @brief Disable CTS Interrupt
2205 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2206 * @param LPUARTx LPUART Instance
2207 * @retval None
2208 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2209 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2210 {
2211 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2212 }
2213
2214 #if defined(USART_CR3_WUFIE)
2215 /**
2216 * @brief Disable Wake Up from Stop Mode Interrupt
2217 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2218 * @param LPUARTx LPUART Instance
2219 * @retval None
2220 */
LL_LPUART_DisableIT_WKUP(USART_TypeDef * LPUARTx)2221 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2222 {
2223 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2224 }
2225
2226 #endif /* USART_CR3_WUFIE */
2227 /**
2228 * @brief Disable TX FIFO Threshold Interrupt
2229 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2230 * @param LPUARTx LPUART Instance
2231 * @retval None
2232 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2233 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2234 {
2235 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2236 }
2237
2238 /**
2239 * @brief Disable RX FIFO Threshold Interrupt
2240 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2241 * @param LPUARTx LPUART Instance
2242 * @retval None
2243 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2244 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2245 {
2246 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2247 }
2248
2249 /**
2250 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2251 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2252 * @param LPUARTx LPUART Instance
2253 * @retval State of bit (1 or 0).
2254 */
LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef * LPUARTx)2255 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2256 {
2257 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2258 }
2259
2260 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2261
2262 /**
2263 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2264 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2265 * @param LPUARTx LPUART Instance
2266 * @retval State of bit (1 or 0).
2267 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef * LPUARTx)2268 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2269 {
2270 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2271 }
2272
2273 /**
2274 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2275 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2276 * @param LPUARTx LPUART Instance
2277 * @retval State of bit (1 or 0).
2278 */
LL_LPUART_IsEnabledIT_TC(const USART_TypeDef * LPUARTx)2279 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2280 {
2281 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2282 }
2283
2284 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
2285
2286 /**
2287 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2288 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2289 * @param LPUARTx LPUART Instance
2290 * @retval State of bit (1 or 0).
2291 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef * LPUARTx)2292 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2293 {
2294 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2295 }
2296
2297 /**
2298 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2299 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2300 * @param LPUARTx LPUART Instance
2301 * @retval State of bit (1 or 0).
2302 */
LL_LPUART_IsEnabledIT_PE(const USART_TypeDef * LPUARTx)2303 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2304 {
2305 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2306 }
2307
2308 /**
2309 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2310 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2311 * @param LPUARTx LPUART Instance
2312 * @retval State of bit (1 or 0).
2313 */
LL_LPUART_IsEnabledIT_CM(const USART_TypeDef * LPUARTx)2314 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2315 {
2316 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2317 }
2318
2319 /**
2320 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2321 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2322 * @param LPUARTx LPUART Instance
2323 * @retval State of bit (1 or 0).
2324 */
LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef * LPUARTx)2325 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2326 {
2327 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2328 }
2329
2330 /**
2331 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2332 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2333 * @param LPUARTx LPUART Instance
2334 * @retval State of bit (1 or 0).
2335 */
LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef * LPUARTx)2336 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2337 {
2338 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2339 }
2340
2341 /**
2342 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2343 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2344 * @param LPUARTx LPUART Instance
2345 * @retval State of bit (1 or 0).
2346 */
LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef * LPUARTx)2347 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2348 {
2349 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2350 }
2351
2352 /**
2353 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2354 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2355 * @param LPUARTx LPUART Instance
2356 * @retval State of bit (1 or 0).
2357 */
LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef * LPUARTx)2358 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2359 {
2360 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2361 }
2362
2363 #if defined(USART_CR3_WUFIE)
2364 /**
2365 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2366 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2367 * @param LPUARTx LPUART Instance
2368 * @retval State of bit (1 or 0).
2369 */
LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef * LPUARTx)2370 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
2371 {
2372 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2373 }
2374
2375 #endif /* USART_CR3_WUFIE */
2376 /**
2377 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2378 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2379 * @param LPUARTx LPUART Instance
2380 * @retval State of bit (1 or 0).
2381 */
LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef * LPUARTx)2382 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2383 {
2384 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2385 }
2386
2387 /**
2388 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2389 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2390 * @param LPUARTx LPUART Instance
2391 * @retval State of bit (1 or 0).
2392 */
LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef * LPUARTx)2393 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2394 {
2395 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2396 }
2397
2398 /**
2399 * @}
2400 */
2401
2402 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2403 * @{
2404 */
2405
2406 /**
2407 * @brief Enable DMA Mode for reception
2408 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2409 * @param LPUARTx LPUART Instance
2410 * @retval None
2411 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2412 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2413 {
2414 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2415 }
2416
2417 /**
2418 * @brief Disable DMA Mode for reception
2419 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2420 * @param LPUARTx LPUART Instance
2421 * @retval None
2422 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2423 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2424 {
2425 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2426 }
2427
2428 /**
2429 * @brief Check if DMA Mode is enabled for reception
2430 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2431 * @param LPUARTx LPUART Instance
2432 * @retval State of bit (1 or 0).
2433 */
LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef * LPUARTx)2434 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2435 {
2436 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2437 }
2438
2439 /**
2440 * @brief Enable DMA Mode for transmission
2441 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2442 * @param LPUARTx LPUART Instance
2443 * @retval None
2444 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2445 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2446 {
2447 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2448 }
2449
2450 /**
2451 * @brief Disable DMA Mode for transmission
2452 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2453 * @param LPUARTx LPUART Instance
2454 * @retval None
2455 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2456 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2457 {
2458 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2459 }
2460
2461 /**
2462 * @brief Check if DMA Mode is enabled for transmission
2463 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2464 * @param LPUARTx LPUART Instance
2465 * @retval State of bit (1 or 0).
2466 */
LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef * LPUARTx)2467 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2468 {
2469 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2470 }
2471
2472 /**
2473 * @brief Enable DMA Disabling on Reception Error
2474 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2475 * @param LPUARTx LPUART Instance
2476 * @retval None
2477 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2478 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2479 {
2480 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2481 }
2482
2483 /**
2484 * @brief Disable DMA Disabling on Reception Error
2485 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2486 * @param LPUARTx LPUART Instance
2487 * @retval None
2488 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2489 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2490 {
2491 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2492 }
2493
2494 /**
2495 * @brief Indicate if DMA Disabling on Reception Error is disabled
2496 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2497 * @param LPUARTx LPUART Instance
2498 * @retval State of bit (1 or 0).
2499 */
LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef * LPUARTx)2500 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2501 {
2502 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2503 }
2504
2505 /**
2506 * @brief Get the LPUART data register address used for DMA transfer
2507 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2508 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2509 * @param LPUARTx LPUART Instance
2510 * @param Direction This parameter can be one of the following values:
2511 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2512 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2513 * @retval Address of data register
2514 */
LL_LPUART_DMA_GetRegAddr(const USART_TypeDef * LPUARTx,uint32_t Direction)2515 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2516 {
2517 uint32_t data_reg_addr;
2518
2519 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2520 {
2521 /* return address of TDR register */
2522 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2523 }
2524 else
2525 {
2526 /* return address of RDR register */
2527 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2528 }
2529
2530 return data_reg_addr;
2531 }
2532
2533 /**
2534 * @}
2535 */
2536
2537 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2538 * @{
2539 */
2540
2541 /**
2542 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2543 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2544 * @param LPUARTx LPUART Instance
2545 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2546 */
LL_LPUART_ReceiveData8(const USART_TypeDef * LPUARTx)2547 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2548 {
2549 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2550 }
2551
2552 /**
2553 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2554 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2555 * @param LPUARTx LPUART Instance
2556 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2557 */
LL_LPUART_ReceiveData9(const USART_TypeDef * LPUARTx)2558 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2559 {
2560 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2561 }
2562
2563 /**
2564 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2565 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2566 * @param LPUARTx LPUART Instance
2567 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2568 * @retval None
2569 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2570 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2571 {
2572 LPUARTx->TDR = Value;
2573 }
2574
2575 /**
2576 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2577 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2578 * @param LPUARTx LPUART Instance
2579 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2580 * @retval None
2581 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2582 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2583 {
2584 LPUARTx->TDR = Value & 0x1FFUL;
2585 }
2586
2587 /**
2588 * @}
2589 */
2590
2591 /** @defgroup LPUART_LL_EF_Execution Execution
2592 * @{
2593 */
2594
2595 /**
2596 * @brief Request Break sending
2597 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2598 * @param LPUARTx LPUART Instance
2599 * @retval None
2600 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2601 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2602 {
2603 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2604 }
2605
2606 /**
2607 * @brief Put LPUART in mute mode and set the RWU flag
2608 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2609 * @param LPUARTx LPUART Instance
2610 * @retval None
2611 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2612 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2613 {
2614 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2615 }
2616
2617 /**
2618 * @brief Request a Receive Data and FIFO flush
2619 * @note Allows to discard the received data without reading them, and avoid an overrun
2620 * condition.
2621 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2622 * @param LPUARTx LPUART Instance
2623 * @retval None
2624 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2625 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2626 {
2627 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2628 }
2629
2630 /**
2631 * @brief Request a Transmit data FIFO flush
2632 * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
2633 * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
2634 * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
2635 * FIFO mode feature is supported by the USARTx instance.
2636 * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
2637 * @param LPUARTx LPUART Instance
2638 * @retval None
2639 */
LL_LPUART_RequestTxDataFlush(USART_TypeDef * LPUARTx)2640 __STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
2641 {
2642 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
2643 }
2644
2645 /**
2646 * @}
2647 */
2648
2649 #if defined(USE_FULL_LL_DRIVER)
2650 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2651 * @{
2652 */
2653 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2654 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2655 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2656 /**
2657 * @}
2658 */
2659 #endif /* USE_FULL_LL_DRIVER */
2660
2661 /**
2662 * @}
2663 */
2664
2665 /**
2666 * @}
2667 */
2668
2669 #endif /* LPUART1 */
2670
2671 /**
2672 * @}
2673 */
2674
2675 #ifdef __cplusplus
2676 }
2677 #endif
2678
2679 #endif /* STM32WB0x_LL_LPUART_H */
2680
