1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) MPU API to configure and enable regions
28 (+) API to access to MCU info (CPUID register)
29
30 @endverbatim
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32WB0x_LL_CORTEX_H
36 #define STM32WB0x_LL_CORTEX_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32wb0x.h"
44
45 /** @addtogroup STM32WB0x_LL_Driver
46 * @{
47 */
48
49 /** @defgroup CORTEX_LL CORTEX
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57
58 /* Private macros ------------------------------------------------------------*/
59
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
63 * @{
64 */
65
66 /** @defgroup CORTEX_LL_EC_CLKSOURCE_SYSCLK SYSTICK Clock Source
67 * @{
68 */
69 #define LL_SYSTICK_CLKSOURCE_SYSCLK SysTick_CTRL_CLKSOURCE_Msk /*!< System clock selected as SysTick clock source. */
70 /**
71 * @}
72 */
73
74 /** @defgroup CORTEX_LL_EX_NVIC_IRQ_PRIORITY NVIC IRQ Priority
75 * @{
76 */
77
78 #define LL_NVIC_CRITICAL_PRIORITY 0
79
80 #define LL_NVIC_HIGH_PRIORITY 1
81
82 #define LL_NVIC_MED_PRIORITY 2
83
84 #define LL_NVIC_LOW_PRIORITY 3
85
86 /**
87 * @}
88 */
89
90 #if __MPU_PRESENT
91
92 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
93 * @{
94 */
95 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
96 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
97 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
98 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
99 /**
100 * @}
101 */
102
103 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
104 * @{
105 */
106 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
107 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
108 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
109 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
110 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
111 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
112 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
113 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
114 /**
115 * @}
116 */
117
118 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
119 * @{
120 */
121 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
123 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
135 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
144 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
145 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
146 /**
147 * @}
148 */
149
150 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
151 * @{
152 */
153 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
154 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
155 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
156 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
157 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
158 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
159 /**
160 * @}
161 */
162
163 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
164 * @{
165 */
166 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
167 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
168 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
169 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
175 * @{
176 */
177 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
178 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
179 /**
180 * @}
181 */
182
183 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
184 * @{
185 */
186 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
187 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
188 /**
189 * @}
190 */
191
192 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
193 * @{
194 */
195 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
196 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
197 /**
198 * @}
199 */
200
201 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
202 * @{
203 */
204 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
205 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
206 /**
207 * @}
208 */
209 #endif /* __MPU_PRESENT */
210 /**
211 * @}
212 */
213
214 /* Exported macro ------------------------------------------------------------*/
215
216 /* Exported functions --------------------------------------------------------*/
217 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
218 * @{
219 */
220
221 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
222 * @{
223 */
224
225 /**
226 * @brief This function configures the Systick counter.
227 * @rmtoll LL_SYSTICK_Config
228 * @param ticks Number of ticks between two interrupts.
229 * @retval None.
230 */
LL_SYSTICK_Config(uint32_t ticks)231 __STATIC_INLINE void LL_SYSTICK_Config(uint32_t ticks)
232 {
233 SysTick_Config(ticks);
234 }
235
236 /**
237 * @brief This function enable the Systick counter.
238 * @rmtoll STK_CTRL ENABLE LL_SYSTICK_Enable
239 * @retval None.
240 */
LL_SYSTICK_Enable(void)241 __STATIC_INLINE void LL_SYSTICK_Enable(void)
242 {
243 SET_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk);
244 }
245
246 /**
247 * @brief This function disable the Systick counter.
248 * @rmtoll STK_CTRL DISABLE LL_SYSTICK_Disable
249 * @retval None.
250 */
LL_SYSTICK_Disable(void)251 __STATIC_INLINE void LL_SYSTICK_Disable(void)
252 {
253 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk);
254 }
255
256 /**
257 * @brief This function checks if the Systick counter flag is active or not.
258 * @note It can be used in timeout function on application side.
259 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
260 * @retval State of bit (1 or 0).
261 */
LL_SYSTICK_IsActiveCounterFlag(void)262 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
263 {
264 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
265 }
266
267 /**
268 * @brief Configures the SysTick clock source
269 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
270 * @param Source This parameter can be one of the following values:
271 * @arg @ref LL_SYSTICK_CLKSOURCE_SYSCLK
272 * @retval None
273 */
LL_SYSTICK_SetClkSource(uint32_t Source)274 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
275 {
276 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_SYSCLK);
277 }
278
279 /**
280 * @brief Get the SysTick clock source
281 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
282 * @retval Returned value can be one of the following values:
283 * @arg @ref LL_SYSTICK_CLKSOURCE_SYSCLK
284 */
LL_SYSTICK_GetClkSource(void)285 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
286 {
287 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_SYSCLK);
288 }
289
290 /**
291 * @brief Enable SysTick exception request
292 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
293 * @retval None
294 */
LL_SYSTICK_EnableIT(void)295 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
296 {
297 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
298 }
299
300 /**
301 * @brief Disable SysTick exception request
302 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
303 * @retval None
304 */
LL_SYSTICK_DisableIT(void)305 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
306 {
307 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
308 }
309
310 /**
311 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
312 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
313 * @retval State of bit (1 or 0).
314 */
LL_SYSTICK_IsEnabledIT(void)315 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
316 {
317 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
318 }
319
320 /**
321 * @}
322 */
323
324 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
325 * @{
326 */
327
328 /**
329 * @brief Processor uses sleep as its low power mode
330 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
331 * @retval None
332 */
LL_LPM_EnableSleep(void)333 __STATIC_INLINE void LL_LPM_EnableSleep(void)
334 {
335 /* Clear SLEEPDEEP bit of Cortex System Control Register */
336 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
337 }
338
339 /**
340 * @brief Processor uses deep sleep as its low power mode
341 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
342 * @retval None
343 */
LL_LPM_EnableDeepSleep(void)344 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
345 {
346 /* Set SLEEPDEEP bit of Cortex System Control Register */
347 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
348 }
349
350 /**
351 * @}
352 */
353
354 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
355 * @{
356 */
357
358 /**
359 * @brief Get Implementer code
360 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
361 * @retval Value should be equal to 0x41 for ARM
362 */
LL_CPUID_GetImplementer(void)363 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
364 {
365 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
366 }
367
368 /**
369 * @brief Get Variant number (The r value in the rnpn product revision identifier)
370 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
371 * @retval Value between 0 and 255 (0x0: revision 0)
372 */
LL_CPUID_GetVariant(void)373 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
374 {
375 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
376 }
377
378 /**
379 * @brief Get Constant number
380 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
381 * @retval Value should be equal to 0xC for Cortex-M0+ devices
382 */
LL_CPUID_GetConstant(void)383 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
384 {
385 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
386 }
387
388 /**
389 * @brief Get Part number
390 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
391 * @retval Value should be equal to 0xC60 for Cortex-M0+
392 */
LL_CPUID_GetParNo(void)393 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
394 {
395 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
396 }
397
398 /**
399 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
400 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
401 * @retval Value between 0 and 255 (0x1: patch 1)
402 */
LL_CPUID_GetRevision(void)403 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
404 {
405 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
406 }
407
408 /**
409 * @}
410 */
411
412 #if __MPU_PRESENT
413 /** @defgroup CORTEX_LL_EF_MPU MPU
414 * @{
415 */
416
417 /**
418 * @brief Enable MPU with input options
419 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
420 * @param Options This parameter can be one of the following values:
421 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
422 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
423 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
424 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
425 * @retval None
426 */
LL_MPU_Enable(uint32_t Options)427 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
428 {
429 /* Enable the MPU*/
430 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
431 /* Ensure MPU settings take effects */
432 __DSB();
433 /* Sequence instruction fetches using update settings */
434 __ISB();
435 }
436
437 /**
438 * @brief Disable MPU
439 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
440 * @retval None
441 */
LL_MPU_Disable(void)442 __STATIC_INLINE void LL_MPU_Disable(void)
443 {
444 /* Make sure outstanding transfers are done */
445 __DMB();
446 /* Disable MPU*/
447 WRITE_REG(MPU->CTRL, 0U);
448 }
449
450 /**
451 * @brief Check if MPU is enabled or not
452 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
453 * @retval State of bit (1 or 0).
454 */
LL_MPU_IsEnabled(void)455 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
456 {
457 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
458 }
459
460 /**
461 * @brief Enable a MPU region
462 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
463 * @param Region This parameter can be one of the following values:
464 * @arg @ref LL_MPU_REGION_NUMBER0
465 * @arg @ref LL_MPU_REGION_NUMBER1
466 * @arg @ref LL_MPU_REGION_NUMBER2
467 * @arg @ref LL_MPU_REGION_NUMBER3
468 * @arg @ref LL_MPU_REGION_NUMBER4
469 * @arg @ref LL_MPU_REGION_NUMBER5
470 * @arg @ref LL_MPU_REGION_NUMBER6
471 * @arg @ref LL_MPU_REGION_NUMBER7
472 * @retval None
473 */
LL_MPU_EnableRegion(uint32_t Region)474 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
475 {
476 /* Set Region number */
477 WRITE_REG(MPU->RNR, Region);
478 /* Enable the MPU region */
479 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
480 }
481
482 /**
483 * @brief Configure and enable a region
484 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
485 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
486 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
487 * MPU_RASR XN LL_MPU_ConfigRegion\n
488 * MPU_RASR AP LL_MPU_ConfigRegion\n
489 * MPU_RASR S LL_MPU_ConfigRegion\n
490 * MPU_RASR C LL_MPU_ConfigRegion\n
491 * MPU_RASR B LL_MPU_ConfigRegion\n
492 * MPU_RASR SIZE LL_MPU_ConfigRegion
493 * @param Region This parameter can be one of the following values:
494 * @arg @ref LL_MPU_REGION_NUMBER0
495 * @arg @ref LL_MPU_REGION_NUMBER1
496 * @arg @ref LL_MPU_REGION_NUMBER2
497 * @arg @ref LL_MPU_REGION_NUMBER3
498 * @arg @ref LL_MPU_REGION_NUMBER4
499 * @arg @ref LL_MPU_REGION_NUMBER5
500 * @arg @ref LL_MPU_REGION_NUMBER6
501 * @arg @ref LL_MPU_REGION_NUMBER7
502 * @param Address Value of region base address
503 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
504 * @param Attributes This parameter can be a combination of the following values:
505 * @arg @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B or @ref LL_MPU_REGION_SIZE_1KB
506 * or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB
507 * or @ref LL_MPU_REGION_SIZE_16KB or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB
508 * or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
509 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB
510 * or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB or @ref LL_MPU_REGION_SIZE_32MB
511 * or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB
512 * or @ref LL_MPU_REGION_SIZE_512MB or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB
513 * or @ref LL_MPU_REGION_SIZE_4GB
514 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
515 * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
516 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
517 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
518 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
519 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
520 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
521 * @retval None
522 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)523 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address,
524 uint32_t Attributes)
525 {
526 /* Set Region number */
527 WRITE_REG(MPU->RNR, Region);
528 /* Set base address */
529 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
530 /* Configure MPU */
531 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
532 }
533
534 /**
535 * @brief Disable a region
536 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
537 * MPU_RASR ENABLE LL_MPU_DisableRegion
538 * @param Region This parameter can be one of the following values:
539 * @arg @ref LL_MPU_REGION_NUMBER0
540 * @arg @ref LL_MPU_REGION_NUMBER1
541 * @arg @ref LL_MPU_REGION_NUMBER2
542 * @arg @ref LL_MPU_REGION_NUMBER3
543 * @arg @ref LL_MPU_REGION_NUMBER4
544 * @arg @ref LL_MPU_REGION_NUMBER5
545 * @arg @ref LL_MPU_REGION_NUMBER6
546 * @arg @ref LL_MPU_REGION_NUMBER7
547 * @retval None
548 */
LL_MPU_DisableRegion(uint32_t Region)549 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
550 {
551 /* Set Region number */
552 WRITE_REG(MPU->RNR, Region);
553 /* Disable the MPU region */
554 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
555 }
556
557 /**
558 * @}
559 */
560
561 #endif /* __MPU_PRESENT */
562 /**
563 * @}
564 */
565
566 /**
567 * @}
568 */
569
570 /**
571 * @}
572 */
573
574 #ifdef __cplusplus
575 }
576 #endif
577
578 #endif /* STM32WB0x_LL_CORTEX_H */
579
