1 /** 2 ****************************************************************************** 3 * @file stm32wb0x_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2024 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WB0x_HAL_TIM_H 21 #define STM32WB0x_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wb0x_hal_def.h" 29 30 /** @addtogroup STM32WB0x_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 50 51 uint32_t CounterMode; /*!< Specifies the counter mode. 52 This parameter can be a value of @ref TIM_Counter_Mode */ 53 54 uint32_t Period; /*!< Specifies the period value to be loaded into the active 55 Auto-Reload Register at the next update event. 56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 57 58 uint32_t ClockDivision; /*!< Specifies the clock division. 59 This parameter can be a value of @ref TIM_ClockDivision */ 60 61 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 62 reaches zero, an update event is generated and counting restarts 63 from the RCR value (N). 64 This means in PWM mode that (N+1) corresponds to: 65 - the number of PWM periods in edge-aligned mode 66 - the number of half PWM period in center-aligned mode 67 GP timers: this parameter must be a number between Min_Data = 0x00 and 68 Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 70 Max_Data = 0xFFFF. */ 71 72 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 73 This parameter can be a value of @ref TIM_AutoReloadPreload */ 74 } TIM_Base_InitTypeDef; 75 76 /** 77 * @brief TIM Output Compare Configuration Structure definition 78 */ 79 typedef struct 80 { 81 uint32_t OCMode; /*!< Specifies the TIM mode. 82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 83 84 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 85 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 86 87 uint32_t OCPolarity; /*!< Specifies the output polarity. 88 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 89 90 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 91 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 92 @note This parameter is valid only for timer instances supporting break feature. */ 93 94 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 95 This parameter can be a value of @ref TIM_Output_Fast_State 96 @note This parameter is valid only in PWM1 and PWM2 mode. */ 97 98 99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 101 @note This parameter is valid only for timer instances supporting break feature. */ 102 103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 105 @note This parameter is valid only for timer instances supporting break feature. */ 106 } TIM_OC_InitTypeDef; 107 108 /** 109 * @brief TIM One Pulse Mode Configuration Structure definition 110 */ 111 typedef struct 112 { 113 uint32_t OCMode; /*!< Specifies the TIM mode. 114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 115 116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 118 119 uint32_t OCPolarity; /*!< Specifies the output polarity. 120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 121 122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 124 @note This parameter is valid only for timer instances supporting break feature. */ 125 126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 128 @note This parameter is valid only for timer instances supporting break feature. */ 129 130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 132 @note This parameter is valid only for timer instances supporting break feature. */ 133 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 136 137 uint32_t ICSelection; /*!< Specifies the input. 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 139 140 uint32_t ICFilter; /*!< Specifies the input capture filter. 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 142 } TIM_OnePulse_InitTypeDef; 143 144 /** 145 * @brief TIM Input Capture Configuration Structure definition 146 */ 147 typedef struct 148 { 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 151 152 uint32_t ICSelection; /*!< Specifies the input. 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 154 155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 157 158 uint32_t ICFilter; /*!< Specifies the input capture filter. 159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 160 } TIM_IC_InitTypeDef; 161 162 /** 163 * @brief TIM Encoder Configuration Structure definition 164 */ 165 typedef struct 166 { 167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 168 This parameter can be a value of @ref TIM_Encoder_Mode */ 169 170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 171 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 172 173 uint32_t IC1Selection; /*!< Specifies the input. 174 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 175 176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 178 179 uint32_t IC1Filter; /*!< Specifies the input capture filter. 180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 181 182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 184 185 uint32_t IC2Selection; /*!< Specifies the input. 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 187 188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 190 191 uint32_t IC2Filter; /*!< Specifies the input capture filter. 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 193 } TIM_Encoder_InitTypeDef; 194 195 /** 196 * @brief Clock Configuration Handle Structure definition 197 */ 198 typedef struct 199 { 200 uint32_t ClockSource; /*!< TIM clock sources 201 This parameter can be a value of @ref TIM_Clock_Source */ 202 uint32_t ClockPolarity; /*!< TIM clock polarity 203 This parameter can be a value of @ref TIM_Clock_Polarity */ 204 uint32_t ClockPrescaler; /*!< TIM clock prescaler 205 This parameter can be a value of @ref TIM_Clock_Prescaler */ 206 uint32_t ClockFilter; /*!< TIM clock filter 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 208 } TIM_ClockConfigTypeDef; 209 210 /** 211 * @brief TIM Clear Input Configuration Handle Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t ClearInputState; /*!< TIM clear Input state 216 This parameter can be ENABLE or DISABLE */ 217 uint32_t ClearInputSource; /*!< TIM clear Input sources 218 This parameter can be a value of @ref TIM_ClearInput_Source */ 219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 220 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 222 This parameter must be 0: When OCRef clear feature is used with ETR source, 223 ETR prescaler must be off */ 224 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 226 } TIM_ClearInputConfigTypeDef; 227 228 /** 229 * @brief TIM Slave configuration Structure definition 230 */ 231 typedef struct 232 { 233 uint32_t SlaveMode; /*!< Slave mode selection 234 This parameter can be a value of @ref TIM_Slave_Mode */ 235 uint32_t InputTrigger; /*!< Input Trigger source 236 This parameter can be a value of @ref TIM_Trigger_Selection */ 237 uint32_t TriggerPolarity; /*!< Input Trigger polarity 238 This parameter can be a value of @ref TIM_Trigger_Polarity */ 239 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 240 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 241 uint32_t TriggerFilter; /*!< Input trigger filter 242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 243 244 } TIM_SlaveConfigTypeDef; 245 246 /** 247 * @brief TIM Break input(s) and Dead time configuration Structure definition 248 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 249 * filter and polarity. 250 */ 251 typedef struct 252 { 253 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 254 255 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 256 257 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 258 259 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 260 261 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 262 263 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 264 265 #if defined(TIM_BDTR_BKF) 266 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 267 #endif /* TIM_BDTR_BKF */ 268 269 #if defined(TIM_BDTR_BKBID) 270 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 271 272 #endif /* TIM_BDTR_BKBID */ 273 #if defined(TIM_BDTR_BK2E) 274 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 275 276 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 277 278 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 279 280 #endif /*TIM_BDTR_BK2E */ 281 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 282 283 } TIM_BreakDeadTimeConfigTypeDef; 284 285 /** 286 * @brief HAL State structures definition 287 */ 288 typedef enum 289 { 290 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 291 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 292 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 293 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 294 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 295 } HAL_TIM_StateTypeDef; 296 297 /** 298 * @brief TIM Channel States definition 299 */ 300 typedef enum 301 { 302 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 303 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 304 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 305 } HAL_TIM_ChannelStateTypeDef; 306 307 #if defined(TIM_DMA_SUPPORT) 308 /** 309 * @brief DMA Burst States definition 310 */ 311 typedef enum 312 { 313 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 314 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 315 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 316 } HAL_TIM_DMABurstStateTypeDef; 317 #endif /* TIM_DMA_SUPPORT */ 318 319 /** 320 * @brief HAL Active channel structures definition 321 */ 322 typedef enum 323 { 324 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 325 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 326 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 327 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 328 #if defined(TIM_CCER_CC5E) 329 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 330 #endif /* TIM_CCER_CC5E */ 331 #if defined(TIM_CCER_CC6E) 332 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 333 #endif /* TIM_CCER_CC6E */ 334 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 335 } HAL_TIM_ActiveChannel; 336 337 /** 338 * @brief TIM Time Base Handle Structure definition 339 */ 340 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 341 typedef struct __TIM_HandleTypeDef 342 #else 343 typedef struct 344 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 345 { 346 TIM_TypeDef *Instance; /*!< Register base address */ 347 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 348 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 349 #if defined(TIM_DMA_SUPPORT) 350 DMA_HandleTypeDef *hdma[5]; /*!< DMA Handlers array 351 This array is accessed by a @ref DMA_Handle_index */ 352 #endif /* TIM_DMA_SUPPORT */ 353 HAL_LockTypeDef Lock; /*!< Locking object */ 354 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 355 #if defined(TIM1) 356 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 357 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[3]; /*!< TIM complementary channel operation state */ 358 #else 359 __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ 360 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[1]; /*!< TIM complementary channel operation state */ 361 #endif /* TIM1 */ 362 #if defined(TIM_DMA_SUPPORT) 363 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 364 #endif /* TIM_DMA_SUPPORT */ 365 366 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 367 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 368 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 369 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 370 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 371 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 372 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 373 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 374 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 375 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 376 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 377 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 378 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 379 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 380 #if defined(TIM_DMA_SUPPORT) 381 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 382 #endif /* TIM_DMA_SUPPORT */ 383 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 384 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 385 #if defined(TIM_DMA_SUPPORT) 386 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 387 #endif /* TIM_DMA_SUPPORT */ 388 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 389 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 390 #if defined(TIM_DMA_SUPPORT) 391 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 392 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 393 #endif /* TIM_DMA_SUPPORT */ 394 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 395 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 396 #if defined(TIM_BDTR_BK2E) 397 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 398 #endif /* TIM_BDTR_BK2E */ 399 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 400 } TIM_HandleTypeDef; 401 402 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 403 /** 404 * @brief HAL TIM Callback ID enumeration definition 405 */ 406 typedef enum 407 { 408 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 409 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 410 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 411 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 412 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 413 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 414 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 415 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 416 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 417 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 418 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 419 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 420 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 421 #if defined(TIM_DMA_SUPPORT) 422 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 423 #endif /* TIM_DMA_SUPPORT */ 424 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 425 426 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 427 #if defined(TIM_DMA_SUPPORT) 428 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 429 #endif /* TIM_DMA_SUPPORT */ 430 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 431 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 432 #if defined(TIM_DMA_SUPPORT) 433 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 434 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 435 #endif /* TIM_DMA_SUPPORT */ 436 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 437 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 438 #if defined(TIM_BDTR_BK2E) 439 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 440 #endif /* TIM_BDTR_BK2E */ 441 } HAL_TIM_CallbackIDTypeDef; 442 443 /** 444 * @brief HAL TIM Callback pointer definition 445 */ 446 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 447 448 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 449 450 /** 451 * @} 452 */ 453 /* End of exported types -----------------------------------------------------*/ 454 455 /* Exported constants --------------------------------------------------------*/ 456 /** @defgroup TIM_Exported_Constants TIM Exported Constants 457 * @{ 458 */ 459 460 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 461 * @{ 462 */ 463 #define TIM_CLEARINPUTSOURCE_NONE 0x10000000U /*!< OCREF_CLR is disabled */ 464 #define TIM_CLEARINPUTSOURCE_ETR 0x20000000U /*!< OCREF_CLR is connected to ETRF input */ 465 /** 466 * @} 467 */ 468 469 #if defined(TIM_DMA_SUPPORT) 470 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 471 * @{ 472 */ 473 #define TIM_DMABASE_CR1 0x00000000U 474 #define TIM_DMABASE_CR2 0x00000001U 475 #define TIM_DMABASE_SMCR 0x00000002U 476 #define TIM_DMABASE_DIER 0x00000003U 477 #define TIM_DMABASE_SR 0x00000004U 478 #define TIM_DMABASE_EGR 0x00000005U 479 #define TIM_DMABASE_CCMR1 0x00000006U 480 #define TIM_DMABASE_CCMR2 0x00000007U 481 #define TIM_DMABASE_CCER 0x00000008U 482 #define TIM_DMABASE_CNT 0x00000009U 483 #define TIM_DMABASE_PSC 0x0000000AU 484 #define TIM_DMABASE_ARR 0x0000000BU 485 #define TIM_DMABASE_RCR 0x0000000CU 486 #define TIM_DMABASE_CCR1 0x0000000DU 487 #define TIM_DMABASE_CCR2 0x0000000EU 488 #define TIM_DMABASE_CCR3 0x0000000FU 489 #define TIM_DMABASE_CCR4 0x00000010U 490 #define TIM_DMABASE_BDTR 0x00000011U 491 #define TIM_DMABASE_DCR 0x00000012U 492 #define TIM_DMABASE_DMAR 0x00000013U 493 #define TIM_DMABASE_OR1 0x00000014U 494 #define TIM_DMABASE_AF1 0x00000018U 495 /** 496 * @} 497 */ 498 #endif /* TIM_DMA_SUPPORT */ 499 500 /** @defgroup TIM_Event_Source TIM Event Source 501 * @{ 502 */ 503 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 504 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 505 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 506 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 507 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 508 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 509 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 510 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 511 #if defined(TIM_EGR_B2G) 512 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 513 #endif /* TIM_EGR_B2G */ 514 /** 515 * @} 516 */ 517 518 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 519 * @{ 520 */ 521 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 522 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 523 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 529 * @{ 530 */ 531 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 532 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 533 /** 534 * @} 535 */ 536 537 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 538 * @{ 539 */ 540 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 541 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 542 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 543 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup TIM_Counter_Mode TIM Counter Mode 549 * @{ 550 */ 551 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 552 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 553 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 554 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 555 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 561 * @{ 562 */ 563 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 564 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 565 /** 566 * @} 567 */ 568 569 /** @defgroup TIM_ClockDivision TIM Clock Division 570 * @{ 571 */ 572 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 573 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 574 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 575 /** 576 * @} 577 */ 578 579 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 580 * @{ 581 */ 582 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 583 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 584 /** 585 * @} 586 */ 587 588 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 589 * @{ 590 */ 591 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 592 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 593 594 /** 595 * @} 596 */ 597 598 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 599 * @{ 600 */ 601 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 602 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 603 /** 604 * @} 605 */ 606 607 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 608 * @{ 609 */ 610 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 611 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 617 * @{ 618 */ 619 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 620 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 621 /** 622 * @} 623 */ 624 625 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 626 * @{ 627 */ 628 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 629 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 635 * @{ 636 */ 637 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 638 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 639 /** 640 * @} 641 */ 642 643 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 644 * @{ 645 */ 646 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 647 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 648 /** 649 * @} 650 */ 651 652 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 653 * @{ 654 */ 655 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 656 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 657 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 658 /** 659 * @} 660 */ 661 662 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 663 * @{ 664 */ 665 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 666 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 667 /** 668 * @} 669 */ 670 671 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 672 * @{ 673 */ 674 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 675 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 676 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 677 /** 678 * @} 679 */ 680 681 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 682 * @{ 683 */ 684 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 685 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 686 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 687 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 693 * @{ 694 */ 695 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 696 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 697 /** 698 * @} 699 */ 700 701 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 702 * @{ 703 */ 704 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 705 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 706 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 707 /** 708 * @} 709 */ 710 711 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 712 * @{ 713 */ 714 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 715 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 716 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 717 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 718 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 719 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 720 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 721 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 722 /** 723 * @} 724 */ 725 726 /** @defgroup TIM_Commutation_Source TIM Commutation Source 727 * @{ 728 */ 729 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 730 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 731 /** 732 * @} 733 */ 734 735 #if defined(TIM_DMA_SUPPORT) 736 /** @defgroup TIM_DMA_sources TIM DMA Sources 737 * @{ 738 */ 739 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 740 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 741 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 742 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 743 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 749 * @{ 750 */ 751 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 752 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 753 /** 754 * @} 755 */ 756 #endif /* TIM_DMA_SUPPORT */ 757 758 /** @defgroup TIM_Flag_definition TIM Flag Definition 759 * @{ 760 */ 761 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 762 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 763 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 764 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 765 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 766 #if defined(TIM_SR_CC5IF) 767 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 768 #endif /* TIM_SR_CC5IF */ 769 #if defined(TIM_SR_CC6IF) 770 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 771 #endif /* TIM_SR_CC6IF */ 772 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 773 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 774 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 775 #if defined(TIM_SR_B2IF) 776 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 777 #endif /* TIM_SR_B2IF */ 778 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 779 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 780 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 781 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 782 /** 783 * @} 784 */ 785 786 /** @defgroup TIM_Channel TIM Channel 787 * @{ 788 */ 789 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 790 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 791 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 792 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 793 #if defined(TIM_CCER_CC5E) 794 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 795 #endif /* TIM_CCER_CC5E */ 796 #if defined(TIM_CCER_CC6E) 797 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 798 #endif /* TIM_CCER_CC6E */ 799 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 800 /** 801 * @} 802 */ 803 804 /** @defgroup TIM_Clock_Source TIM Clock Source 805 * @{ 806 */ 807 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 808 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 809 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 810 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 811 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 812 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 813 /** 814 * @} 815 */ 816 817 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 818 * @{ 819 */ 820 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 821 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 822 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 823 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 824 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 830 * @{ 831 */ 832 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 833 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 834 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 835 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 836 /** 837 * @} 838 */ 839 840 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 841 * @{ 842 */ 843 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 844 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 845 /** 846 * @} 847 */ 848 849 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 850 * @{ 851 */ 852 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 853 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 854 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 855 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 856 /** 857 * @} 858 */ 859 860 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 861 * @{ 862 */ 863 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 864 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 865 /** 866 * @} 867 */ 868 869 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 870 * @{ 871 */ 872 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 873 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 874 /** 875 * @} 876 */ 877 /** @defgroup TIM_Lock_level TIM Lock level 878 * @{ 879 */ 880 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 881 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 882 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 883 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 884 /** 885 * @} 886 */ 887 888 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 889 * @{ 890 */ 891 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 892 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 893 /** 894 * @} 895 */ 896 897 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 898 * @{ 899 */ 900 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 901 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 902 /** 903 * @} 904 */ 905 #if defined(TIM_BDTR_BKBID) 906 907 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 908 * @{ 909 */ 910 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 911 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 912 /** 913 * @} 914 */ 915 #endif /* TIM_BDTR_BKBID */ 916 917 #if defined(TIM_BDTR_BK2E) 918 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 919 * @{ 920 */ 921 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 922 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 923 /** 924 * @} 925 */ 926 927 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 928 * @{ 929 */ 930 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 931 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 932 /** 933 * @} 934 */ 935 #endif /* TIM_BDTR_BK2E */ 936 937 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 938 * @{ 939 */ 940 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 941 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 942 /** 943 * @} 944 */ 945 946 #if defined(TIM_CCR5_CCR5) 947 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 948 * @{ 949 */ 950 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 951 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 952 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 953 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 954 /** 955 * @} 956 */ 957 #endif /* TIM_CCR5_CCR5 */ 958 959 960 /** @defgroup TIM_Slave_Mode TIM Slave mode 961 * @{ 962 */ 963 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 964 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 965 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 966 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 967 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 968 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 969 /** 970 * @} 971 */ 972 973 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 974 * @{ 975 */ 976 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 977 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 978 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 979 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 980 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 981 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 982 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 983 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 984 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 985 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 986 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 987 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 988 #define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 989 #define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 990 /** 991 * @} 992 */ 993 994 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 995 * @{ 996 */ 997 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 998 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 999 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1000 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1001 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 1002 /** 1003 * @} 1004 */ 1005 1006 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1007 * @{ 1008 */ 1009 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1010 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1011 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1012 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1013 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1014 /** 1015 * @} 1016 */ 1017 1018 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1019 * @{ 1020 */ 1021 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1022 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1023 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1024 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1025 /** 1026 * @} 1027 */ 1028 1029 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1030 * @{ 1031 */ 1032 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1033 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1034 /** 1035 * @} 1036 */ 1037 1038 #if defined(TIM_DMA_SUPPORT) 1039 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1040 * @{ 1041 */ 1042 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1043 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1044 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1045 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1046 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1047 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1048 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1049 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1050 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1051 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1052 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1053 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1054 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1055 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1056 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1057 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1058 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1059 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1060 /** 1061 * @} 1062 */ 1063 #endif /* TIM_DMA_SUPPORT */ 1064 1065 #if defined(TIM_DMA_SUPPORT) 1066 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1067 * @{ 1068 */ 1069 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1070 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1071 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1072 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1073 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1074 /** 1075 * @} 1076 */ 1077 #endif /* TIM_DMA_SUPPORT */ 1078 1079 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1080 * @{ 1081 */ 1082 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1083 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1084 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1085 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1086 /** 1087 * @} 1088 */ 1089 1090 /** 1091 * @} 1092 */ 1093 /* End of exported constants -------------------------------------------------*/ 1094 1095 /* Exported macros -----------------------------------------------------------*/ 1096 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1097 * @{ 1098 */ 1099 1100 /** @brief Reset TIM handle state. 1101 * @param __HANDLE__ TIM handle. 1102 * @retval None 1103 */ 1104 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1105 #if defined(TIM1) 1106 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1107 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1108 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1109 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1110 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1111 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1112 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1113 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1114 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1115 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1116 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1117 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1118 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1119 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1120 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1121 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1122 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1123 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1124 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1125 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1126 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1127 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1128 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1129 } while(0) 1130 #else 1131 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1132 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1133 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1134 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1135 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1136 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1137 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1138 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1139 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1140 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1141 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1142 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1143 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1144 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1145 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1146 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1147 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1148 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1149 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1150 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1151 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1152 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1153 } while(0) 1154 #endif /* TIM1 */ 1155 #else 1156 #if defined(TIM1) 1157 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1158 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1159 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1160 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1161 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1162 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1163 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1164 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1165 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1166 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1167 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1168 } while(0) 1169 #else 1170 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1171 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1172 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1173 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1174 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1175 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1176 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1177 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1178 } while(0) 1179 #endif /* TIM1 */ 1180 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1181 1182 /** 1183 * @brief Enable the TIM peripheral. 1184 * @param __HANDLE__ TIM handle 1185 * @retval None 1186 */ 1187 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1188 1189 /** 1190 * @brief Enable the TIM main Output. 1191 * @param __HANDLE__ TIM handle 1192 * @retval None 1193 */ 1194 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1195 1196 /** 1197 * @brief Disable the TIM peripheral. 1198 * @param __HANDLE__ TIM handle 1199 * @retval None 1200 */ 1201 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1202 do { \ 1203 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1204 { \ 1205 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1206 { \ 1207 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1208 } \ 1209 } \ 1210 } while(0) 1211 1212 /** 1213 * @brief Disable the TIM main Output. 1214 * @param __HANDLE__ TIM handle 1215 * @retval None 1216 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1217 * disabled 1218 */ 1219 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1220 do { \ 1221 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1222 { \ 1223 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1224 { \ 1225 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1226 } \ 1227 } \ 1228 } while(0) 1229 1230 /** 1231 * @brief Disable the TIM main Output. 1232 * @param __HANDLE__ TIM handle 1233 * @retval None 1234 * @note The Main Output Enable of a timer instance is disabled unconditionally 1235 */ 1236 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1237 1238 /** @brief Enable the specified TIM interrupt. 1239 * @param __HANDLE__ specifies the TIM Handle. 1240 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1241 * This parameter can be one of the following values: 1242 * @arg TIM_IT_UPDATE: Update interrupt 1243 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1244 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1245 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1246 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1247 * @arg TIM_IT_COM: Commutation interrupt 1248 * @arg TIM_IT_TRIGGER: Trigger interrupt 1249 * @arg TIM_IT_BREAK: Break interrupt 1250 * @retval None 1251 */ 1252 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1253 1254 /** @brief Disable the specified TIM interrupt. 1255 * @param __HANDLE__ specifies the TIM Handle. 1256 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1257 * This parameter can be one of the following values: 1258 * @arg TIM_IT_UPDATE: Update interrupt 1259 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1260 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1261 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1262 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1263 * @arg TIM_IT_COM: Commutation interrupt 1264 * @arg TIM_IT_TRIGGER: Trigger interrupt 1265 * @arg TIM_IT_BREAK: Break interrupt 1266 * @retval None 1267 */ 1268 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1269 1270 #if defined(TIM_DMA_SUPPORT) 1271 /** @brief Enable the specified DMA request. 1272 * @param __HANDLE__ specifies the TIM Handle. 1273 * @param __DMA__ specifies the TIM DMA request to enable. 1274 * This parameter can be one of the following values: 1275 * @arg TIM_DMA_UPDATE: Update DMA request 1276 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1277 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1278 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1279 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1280 * @retval None 1281 */ 1282 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1283 1284 /** @brief Disable the specified DMA request. 1285 * @param __HANDLE__ specifies the TIM Handle. 1286 * @param __DMA__ specifies the TIM DMA request to disable. 1287 * This parameter can be one of the following values: 1288 * @arg TIM_DMA_UPDATE: Update DMA request 1289 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1290 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1291 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1292 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1293 * @retval None 1294 */ 1295 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1296 #endif /* TIM_DMA_SUPPORT */ 1297 1298 /** @brief Check whether the specified TIM interrupt flag is set or not. 1299 * @param __HANDLE__ specifies the TIM Handle. 1300 * @param __FLAG__ specifies the TIM interrupt flag to check. 1301 * This parameter can be one of the following values: 1302 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1303 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1304 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1305 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1306 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1307 * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) 1308 * @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*) 1309 * @arg TIM_FLAG_COM: Commutation interrupt flag 1310 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1311 * @arg TIM_FLAG_BREAK: Break interrupt flag 1312 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) 1313 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1314 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1315 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1316 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1317 * (*) Value not defined for all devices 1318 * @retval The new state of __FLAG__ (TRUE or FALSE). 1319 */ 1320 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1321 1322 /** @brief Clear the specified TIM interrupt flag. 1323 * @param __HANDLE__ specifies the TIM Handle. 1324 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1325 * This parameter can be one of the following values: 1326 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1327 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1328 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1329 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1330 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1331 * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) 1332 * @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*) 1333 * @arg TIM_FLAG_COM: Commutation interrupt flag 1334 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1335 * @arg TIM_FLAG_BREAK: Break interrupt flag 1336 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) 1337 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1338 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1339 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1340 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1341 * (*) Value not defined for all devices 1342 * @retval The new state of __FLAG__ (TRUE or FALSE). 1343 */ 1344 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1345 1346 /** 1347 * @brief Check whether the specified TIM interrupt source is enabled or not. 1348 * @param __HANDLE__ TIM handle 1349 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1350 * This parameter can be one of the following values: 1351 * @arg TIM_IT_UPDATE: Update interrupt 1352 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1353 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1354 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1355 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1356 * @arg TIM_IT_COM: Commutation interrupt 1357 * @arg TIM_IT_TRIGGER: Trigger interrupt 1358 * @arg TIM_IT_BREAK: Break interrupt 1359 * @retval The state of TIM_IT (SET or RESET). 1360 */ 1361 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1362 == (__INTERRUPT__)) ? SET : RESET) 1363 1364 /** @brief Clear the TIM interrupt pending bits. 1365 * @param __HANDLE__ TIM handle 1366 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1367 * This parameter can be one of the following values: 1368 * @arg TIM_IT_UPDATE: Update interrupt 1369 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1370 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1371 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1372 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1373 * @arg TIM_IT_COM: Commutation interrupt 1374 * @arg TIM_IT_TRIGGER: Trigger interrupt 1375 * @arg TIM_IT_BREAK: Break interrupt 1376 * @retval None 1377 */ 1378 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1379 1380 /** 1381 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1382 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1383 * in an atomic way. 1384 * @param __HANDLE__ TIM handle. 1385 * @retval None 1386 mode. 1387 */ 1388 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1389 1390 /** 1391 * @brief Disable update interrupt flag (UIF) remapping. 1392 * @param __HANDLE__ TIM handle. 1393 * @retval None 1394 mode. 1395 */ 1396 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1397 1398 /** 1399 * @brief Get update interrupt flag (UIF) copy status. 1400 * @param __COUNTER__ Counter value. 1401 * @retval The state of UIFCPY (TRUE or FALSE). 1402 mode. 1403 */ 1404 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1405 1406 /** 1407 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1408 * @param __HANDLE__ TIM handle. 1409 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1410 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1411 * or Encoder mode. 1412 */ 1413 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1414 1415 /** 1416 * @brief Set the TIM Prescaler on runtime. 1417 * @param __HANDLE__ TIM handle. 1418 * @param __PRESC__ specifies the Prescaler new value. 1419 * @retval None 1420 */ 1421 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1422 1423 /** 1424 * @brief Set the TIM Counter Register value on runtime. 1425 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 1426 * case of 32 bits counter TIM instance. 1427 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1428 * @param __HANDLE__ TIM handle. 1429 * @param __COUNTER__ specifies the Counter register new value. 1430 * @retval None 1431 */ 1432 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1433 1434 /** 1435 * @brief Get the TIM Counter Register value on runtime. 1436 * @param __HANDLE__ TIM handle. 1437 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1438 */ 1439 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1440 1441 /** 1442 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1443 * @param __HANDLE__ TIM handle. 1444 * @param __AUTORELOAD__ specifies the Counter register new value. 1445 * @retval None 1446 */ 1447 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1448 do{ \ 1449 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1450 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1451 } while(0) 1452 1453 /** 1454 * @brief Get the TIM Autoreload Register value on runtime. 1455 * @param __HANDLE__ TIM handle. 1456 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1457 */ 1458 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1459 1460 /** 1461 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1462 * @param __HANDLE__ TIM handle. 1463 * @param __CKD__ specifies the clock division value. 1464 * This parameter can be one of the following value: 1465 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1466 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1467 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1468 * @retval None 1469 */ 1470 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1471 do{ \ 1472 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1473 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1474 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1475 } while(0) 1476 1477 /** 1478 * @brief Get the TIM Clock Division value on runtime. 1479 * @param __HANDLE__ TIM handle. 1480 * @retval The clock division can be one of the following values: 1481 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1482 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1483 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1484 */ 1485 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1486 1487 /** 1488 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1489 * function. 1490 * @param __HANDLE__ TIM handle. 1491 * @param __CHANNEL__ TIM Channels to be configured. 1492 * This parameter can be one of the following values: 1493 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1494 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1495 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1496 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1497 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1498 * This parameter can be one of the following values: 1499 * @arg TIM_ICPSC_DIV1: no prescaler 1500 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1501 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1502 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1503 * @retval None 1504 */ 1505 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1506 do{ \ 1507 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1508 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1509 } while(0) 1510 1511 /** 1512 * @brief Get the TIM Input Capture prescaler on runtime. 1513 * @param __HANDLE__ TIM handle. 1514 * @param __CHANNEL__ TIM Channels to be configured. 1515 * This parameter can be one of the following values: 1516 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1517 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1518 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1519 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1520 * @retval The input capture prescaler can be one of the following values: 1521 * @arg TIM_ICPSC_DIV1: no prescaler 1522 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1523 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1524 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1525 */ 1526 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1527 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1528 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1529 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1530 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1531 1532 /** 1533 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1534 * @param __HANDLE__ TIM handle. 1535 * @param __CHANNEL__ TIM Channels to be configured. 1536 * This parameter can be one of the following values: 1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1541 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1542 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1543 * (*) Value not defined for all devices 1544 * @param __COMPARE__ specifies the Capture Compare register new value. 1545 * @retval None 1546 */ 1547 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1548 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1549 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1550 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1551 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1552 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1553 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1554 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1555 #else 1556 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1557 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1558 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1559 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1560 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) 1561 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1562 1563 /** 1564 * @brief Get the TIM Capture Compare Register value on runtime. 1565 * @param __HANDLE__ TIM handle. 1566 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1567 * This parameter can be one of the following values: 1568 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1569 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1570 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1571 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1572 * @arg TIM_CHANNEL_5: get capture/compare 5 register value (*) 1573 * @arg TIM_CHANNEL_6: get capture/compare 6 register value (*) 1574 * (*) Value not defined for all devices 1575 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1576 */ 1577 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1578 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1579 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1580 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1581 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1582 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1583 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1584 ((__HANDLE__)->Instance->CCR6)) 1585 #else 1586 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1587 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1588 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1589 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1590 ((__HANDLE__)->Instance->CCR4)) 1591 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1592 1593 /** 1594 * @brief Set the TIM Output compare preload. 1595 * @param __HANDLE__ TIM handle. 1596 * @param __CHANNEL__ TIM Channels to be configured. 1597 * This parameter can be one of the following values: 1598 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1599 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1600 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1601 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1602 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1603 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1604 * (*) Value not defined for all devices 1605 * @retval None 1606 */ 1607 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1608 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1609 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1610 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1611 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1612 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1613 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1614 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1615 #else 1616 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1617 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1618 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1619 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1620 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) 1621 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1622 1623 /** 1624 * @brief Reset the TIM Output compare preload. 1625 * @param __HANDLE__ TIM handle. 1626 * @param __CHANNEL__ TIM Channels to be configured. 1627 * This parameter can be one of the following values: 1628 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1629 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1630 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1631 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1632 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1633 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1634 * (*) Value not defined for all devices 1635 * @retval None 1636 */ 1637 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1638 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1639 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1640 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1641 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1642 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1643 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1644 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1645 #else 1646 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1647 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1648 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1649 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1650 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) 1651 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1652 1653 /** 1654 * @brief Enable fast mode for a given channel. 1655 * @param __HANDLE__ TIM handle. 1656 * @param __CHANNEL__ TIM Channels to be configured. 1657 * This parameter can be one of the following values: 1658 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1659 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1660 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1661 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1662 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1663 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1664 * (*) Value not defined for all devices 1665 * @note When fast mode is enabled an active edge on the trigger input acts 1666 * like a compare match on CCx output. Delay to sample the trigger 1667 * input and to activate CCx output is reduced to 3 clock cycles. 1668 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1669 * @retval None 1670 */ 1671 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1672 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1673 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1674 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1675 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1676 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1677 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1678 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1679 #else 1680 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1681 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1682 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1683 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1684 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) 1685 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1686 1687 /** 1688 * @brief Disable fast mode for a given channel. 1689 * @param __HANDLE__ TIM handle. 1690 * @param __CHANNEL__ TIM Channels to be configured. 1691 * This parameter can be one of the following values: 1692 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1693 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1694 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1695 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1696 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1697 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1698 * (*) Value not defined for all devices 1699 * @note When fast mode is disabled CCx output behaves normally depending 1700 * on counter and CCRx values even when the trigger is ON. The minimum 1701 * delay to activate CCx output when an active edge occurs on the 1702 * trigger input is 5 clock cycles. 1703 * @retval None 1704 */ 1705 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1706 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1707 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1708 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1709 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1710 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1711 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1712 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1713 #else 1714 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1715 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1716 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1717 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1718 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) 1719 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1720 1721 /** 1722 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1723 * @param __HANDLE__ TIM handle. 1724 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1725 * overflow/underflow generates an update interrupt or DMA request (if 1726 * enabled) 1727 * @retval None 1728 */ 1729 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1730 1731 /** 1732 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1733 * @param __HANDLE__ TIM handle. 1734 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1735 * following events generate an update interrupt or DMA request (if 1736 * enabled): 1737 * _ Counter overflow underflow 1738 * _ Setting the UG bit 1739 * _ Update generation through the slave mode controller 1740 * @retval None 1741 */ 1742 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1743 1744 /** 1745 * @brief Set the TIM Capture x input polarity on runtime. 1746 * @param __HANDLE__ TIM handle. 1747 * @param __CHANNEL__ TIM Channels to be configured. 1748 * This parameter can be one of the following values: 1749 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1750 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1751 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1752 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1753 * @param __POLARITY__ Polarity for TIx source 1754 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1755 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1756 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1757 * @retval None 1758 */ 1759 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1760 do{ \ 1761 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1762 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1763 }while(0) 1764 1765 #if defined(TIM_DMA_SUPPORT) 1766 /** @brief Select the Capture/compare DMA request source. 1767 * @param __HANDLE__ specifies the TIM Handle. 1768 * @param __CCDMA__ specifies Capture/compare DMA request source 1769 * This parameter can be one of the following values: 1770 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1771 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1772 * @retval None 1773 */ 1774 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1775 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1776 #endif /* TIM_DMA_SUPPORT */ 1777 1778 /** 1779 * @} 1780 */ 1781 /* End of exported macros ----------------------------------------------------*/ 1782 1783 /* Private constants ---------------------------------------------------------*/ 1784 /** @defgroup TIM_Private_Constants TIM Private Constants 1785 * @{ 1786 */ 1787 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1788 channels have been disabled */ 1789 #if defined(TIM1) 1790 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E |\ 1791 TIM_CCER_CC5E | TIM_CCER_CC6E)) 1792 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1793 #else 1794 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1795 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE)) 1796 #endif /* TIM1 */ 1797 /** 1798 * @} 1799 */ 1800 /* End of private constants --------------------------------------------------*/ 1801 1802 /* Private macros ------------------------------------------------------------*/ 1803 /** @defgroup TIM_Private_Macros TIM Private Macros 1804 * @{ 1805 */ 1806 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1807 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1808 1809 #if defined(TIM_DMA_SUPPORT) 1810 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1811 ((__BASE__) == TIM_DMABASE_CR2) || \ 1812 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1813 ((__BASE__) == TIM_DMABASE_DIER) || \ 1814 ((__BASE__) == TIM_DMABASE_SR) || \ 1815 ((__BASE__) == TIM_DMABASE_EGR) || \ 1816 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1817 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1818 ((__BASE__) == TIM_DMABASE_CCER) || \ 1819 ((__BASE__) == TIM_DMABASE_CNT) || \ 1820 ((__BASE__) == TIM_DMABASE_PSC) || \ 1821 ((__BASE__) == TIM_DMABASE_ARR) || \ 1822 ((__BASE__) == TIM_DMABASE_RCR) || \ 1823 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1824 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1825 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1826 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1827 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1828 ((__BASE__) == TIM_DMABASE_OR1) || \ 1829 ((__BASE__) == TIM_DMABASE_AF1)) 1830 #endif /* TIM_DMA_SUPPORT */ 1831 1832 #if defined(TIM_EGR_B2G) 1833 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1834 #else 1835 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1836 #endif /* TIM_EGR_B2G */ 1837 1838 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1839 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1840 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1841 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1842 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1843 1844 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1845 ((__MODE__) == TIM_UIFREMAP_ENABLE)) 1846 1847 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1848 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1849 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1850 1851 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1852 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1853 1854 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1855 ((__STATE__) == TIM_OCFAST_ENABLE)) 1856 1857 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1858 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1859 1860 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1861 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1862 1863 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1864 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1865 1866 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1867 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1868 1869 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1870 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1871 1872 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1873 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1874 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1875 1876 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1877 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1878 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1879 1880 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1881 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1882 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1883 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1884 1885 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1886 #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ 1887 ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ 1888 ((__CHANNEL__) != (TIM_CHANNEL_6))) 1889 #else 1890 #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__)) 1891 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1892 1893 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1894 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1895 1896 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1897 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1898 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1899 1900 #if defined(TIM_DMA_SUPPORT) 1901 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFE0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1902 #endif /* TIM_DMA_SUPPORT */ 1903 1904 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1905 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1906 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1907 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1908 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1909 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1910 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1911 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1912 #else 1913 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1914 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1915 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1916 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1917 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1918 #endif /* TIM_CCER_CC5E &&TIM_CCER_CC6E */ 1919 1920 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1921 ((__CHANNEL__) == TIM_CHANNEL_2)) 1922 1923 #define IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU)) 1924 1925 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1926 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1927 ((__CHANNEL__) == TIM_CHANNEL_3)) 1928 1929 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1930 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1931 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1932 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1933 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1934 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)) 1935 1936 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1937 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1938 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1939 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1940 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1941 1942 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1943 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1944 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1945 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1946 1947 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1948 1949 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1950 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1951 1952 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1953 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1954 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1955 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1956 1957 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1958 1959 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1960 ((__STATE__) == TIM_OSSR_DISABLE)) 1961 1962 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1963 ((__STATE__) == TIM_OSSI_DISABLE)) 1964 1965 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1966 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1967 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1968 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1969 1970 #if defined(TIM_BDTR_BKF) 1971 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1972 #endif /* TIM_BDTR_BKF */ 1973 1974 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1975 ((__STATE__) == TIM_BREAK_DISABLE)) 1976 1977 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1978 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1979 #if defined(TIM_BDTR_BKBID) 1980 1981 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 1982 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 1983 1984 #endif /* TIM_BDTR_BKBID */ 1985 1986 #if defined(TIM_BDTR_BK2E) 1987 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1988 ((__STATE__) == TIM_BREAK2_DISABLE)) 1989 1990 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1991 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1992 #endif /* TIM_BDTR_BK2E */ 1993 1994 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1995 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1996 1997 #if defined(TIM_CCR5_CCR5) 1998 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1999 #endif /* TIM_CCR5_CCR5 */ 2000 2001 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2002 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2003 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2004 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2005 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 2006 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2007 2008 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2009 ((__MODE__) == TIM_OCMODE_PWM2) || \ 2010 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 2011 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 2012 ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ 2013 ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) 2014 2015 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2016 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2017 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2018 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2019 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2020 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 2021 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 2022 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 2023 2024 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 2025 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 2026 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 2027 ((__SELECTION__) == TIM_TS_ETRF)) 2028 2029 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2030 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2031 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2032 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2033 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2034 2035 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2036 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2037 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2038 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2039 2040 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2041 2042 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2043 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2044 2045 #if defined(TIM_DMA_SUPPORT) 2046 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2047 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2048 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2049 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2050 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2051 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2052 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2053 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2054 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2055 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2056 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2057 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2058 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2059 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2060 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2061 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2062 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2063 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 2064 2065 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2066 #endif /* TIM_DMA_SUPPORT */ 2067 2068 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2069 2070 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2071 2072 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2073 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2074 2075 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2076 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2077 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2078 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2079 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2080 2081 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2082 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2083 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2084 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2085 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2086 2087 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2088 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2089 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2090 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2091 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2092 2093 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2094 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2095 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2096 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2097 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2098 2099 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 2100 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2101 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2102 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2103 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2104 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2105 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2106 (__HANDLE__)->ChannelState[5]) 2107 2108 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2109 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2110 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2111 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2112 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2113 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2114 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2115 2116 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2117 (__HANDLE__)->ChannelState[0] = \ 2118 (__CHANNEL_STATE__); \ 2119 (__HANDLE__)->ChannelState[1] = \ 2120 (__CHANNEL_STATE__); \ 2121 (__HANDLE__)->ChannelState[2] = \ 2122 (__CHANNEL_STATE__); \ 2123 (__HANDLE__)->ChannelState[3] = \ 2124 (__CHANNEL_STATE__); \ 2125 (__HANDLE__)->ChannelState[4] = \ 2126 (__CHANNEL_STATE__); \ 2127 (__HANDLE__)->ChannelState[5] = \ 2128 (__CHANNEL_STATE__); \ 2129 } while(0) 2130 #else 2131 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2132 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2133 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2134 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2135 (__HANDLE__)->ChannelState[3]) 2136 2137 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2138 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2139 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2140 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2141 ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) 2142 2143 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2144 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 2145 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 2146 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 2147 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 2148 } while(0) 2149 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 2150 2151 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 2152 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2153 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2154 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2155 (__HANDLE__)->ChannelNState[2]) 2156 2157 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2158 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2159 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2160 ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__))) 2161 2162 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2163 (__HANDLE__)->ChannelNState[0] = \ 2164 (__CHANNEL_STATE__); \ 2165 (__HANDLE__)->ChannelNState[1] = \ 2166 (__CHANNEL_STATE__); \ 2167 (__HANDLE__)->ChannelNState[2] = \ 2168 (__CHANNEL_STATE__); \ 2169 } while(0) 2170 #else 2171 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2172 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2173 HAL_TIM_CHANNEL_STATE_READY) 2174 2175 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2176 (((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__))) 2177 2178 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ 2179 (((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__))) 2180 2181 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 2182 2183 /** 2184 * @} 2185 */ 2186 /* End of private macros -----------------------------------------------------*/ 2187 2188 /* Include TIM HAL Extended module */ 2189 #include "stm32wb0x_hal_tim_ex.h" 2190 2191 /* Exported functions --------------------------------------------------------*/ 2192 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2193 * @{ 2194 */ 2195 2196 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2197 * @brief Time Base functions 2198 * @{ 2199 */ 2200 /* Time Base functions ********************************************************/ 2201 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2202 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2203 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2204 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2205 /* Blocking mode: Polling */ 2206 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2207 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2208 /* Non-Blocking mode: Interrupt */ 2209 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2210 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2211 #if defined(TIM_DMA_SUPPORT) 2212 /* Non-Blocking mode: DMA */ 2213 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); 2214 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2215 #endif /* TIM_DMA_SUPPORT */ 2216 /** 2217 * @} 2218 */ 2219 2220 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2221 * @brief TIM Output Compare functions 2222 * @{ 2223 */ 2224 /* Timer Output Compare functions *********************************************/ 2225 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2226 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2227 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2228 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2229 /* Blocking mode: Polling */ 2230 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2231 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2232 /* Non-Blocking mode: Interrupt */ 2233 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2234 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2235 #if defined(TIM_DMA_SUPPORT) 2236 /* Non-Blocking mode: DMA */ 2237 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2238 uint16_t Length); 2239 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2240 #endif /* TIM_DMA_SUPPORT */ 2241 /** 2242 * @} 2243 */ 2244 2245 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2246 * @brief TIM PWM functions 2247 * @{ 2248 */ 2249 /* Timer PWM functions ********************************************************/ 2250 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2251 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2252 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2253 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2254 /* Blocking mode: Polling */ 2255 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2256 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2257 /* Non-Blocking mode: Interrupt */ 2258 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2259 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2260 #if defined(TIM_DMA_SUPPORT) 2261 /* Non-Blocking mode: DMA */ 2262 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2263 uint16_t Length); 2264 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2265 #endif /* TIM_DMA_SUPPORT */ 2266 /** 2267 * @} 2268 */ 2269 2270 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2271 * @brief TIM Input Capture functions 2272 * @{ 2273 */ 2274 /* Timer Input Capture functions **********************************************/ 2275 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2276 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2277 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2278 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2279 /* Blocking mode: Polling */ 2280 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2281 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2282 /* Non-Blocking mode: Interrupt */ 2283 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2284 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2285 #if defined(TIM_DMA_SUPPORT) 2286 /* Non-Blocking mode: DMA */ 2287 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2288 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2289 #endif /* TIM_DMA_SUPPORT */ 2290 /** 2291 * @} 2292 */ 2293 2294 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2295 * @brief TIM One Pulse functions 2296 * @{ 2297 */ 2298 /* Timer One Pulse functions **************************************************/ 2299 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2300 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2301 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2302 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2303 /* Blocking mode: Polling */ 2304 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2305 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2306 /* Non-Blocking mode: Interrupt */ 2307 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2308 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2309 /** 2310 * @} 2311 */ 2312 2313 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2314 * @brief TIM Encoder functions 2315 * @{ 2316 */ 2317 /* Timer Encoder functions ****************************************************/ 2318 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); 2319 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2320 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2321 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2322 /* Blocking mode: Polling */ 2323 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2324 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2325 /* Non-Blocking mode: Interrupt */ 2326 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2328 #if defined(TIM_DMA_SUPPORT) 2329 /* Non-Blocking mode: DMA */ 2330 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2331 uint32_t *pData2, uint16_t Length); 2332 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2333 #endif /* TIM_DMA_SUPPORT */ 2334 /** 2335 * @} 2336 */ 2337 2338 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2339 * @brief IRQ handler management 2340 * @{ 2341 */ 2342 /* Interrupt Handler functions ***********************************************/ 2343 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2344 /** 2345 * @} 2346 */ 2347 2348 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2349 * @brief Peripheral Control functions 2350 * @{ 2351 */ 2352 /* Control functions *********************************************************/ 2353 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2354 uint32_t Channel); 2355 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2356 uint32_t Channel); 2357 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, 2358 uint32_t Channel); 2359 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2360 uint32_t OutputChannel, uint32_t InputChannel); 2361 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 2362 const TIM_ClearInputConfigTypeDef *sClearInputConfig, 2363 uint32_t Channel); 2364 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); 2365 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2366 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2367 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2368 #if defined(TIM_DMA_SUPPORT) 2369 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2370 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); 2371 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2372 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 2373 uint32_t BurstLength, uint32_t DataLength); 2374 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2375 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2376 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2377 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2378 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2379 uint32_t BurstLength, uint32_t DataLength); 2380 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2381 #endif /* TIM_DMA_SUPPORT */ 2382 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2383 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); 2384 /** 2385 * @} 2386 */ 2387 2388 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2389 * @brief TIM Callbacks functions 2390 * @{ 2391 */ 2392 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2393 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2394 #if defined(TIM_DMA_SUPPORT) 2395 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2396 #endif /* TIM_DMA_SUPPORT */ 2397 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2398 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2399 #if defined(TIM_DMA_SUPPORT) 2400 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2401 #endif /* TIM_DMA_SUPPORT */ 2402 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2403 #if defined(TIM_DMA_SUPPORT) 2404 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2405 #endif /* TIM_DMA_SUPPORT */ 2406 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2407 #if defined(TIM_DMA_SUPPORT) 2408 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2409 #endif /* TIM_DMA_SUPPORT */ 2410 2411 /* Callbacks Register/UnRegister functions ***********************************/ 2412 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2413 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2414 pTIM_CallbackTypeDef pCallback); 2415 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2416 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2417 2418 /** 2419 * @} 2420 */ 2421 2422 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2423 * @brief Peripheral State functions 2424 * @{ 2425 */ 2426 /* Peripheral State functions ************************************************/ 2427 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); 2428 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); 2429 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); 2430 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); 2431 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); 2432 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); 2433 2434 /* Peripheral Channel state functions ************************************************/ 2435 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); 2436 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); 2437 #if defined(TIM_DMA_SUPPORT) 2438 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); 2439 #endif /* TIM_DMA_SUPPORT */ 2440 /** 2441 * @} 2442 */ 2443 2444 /** 2445 * @} 2446 */ 2447 /* End of exported functions -------------------------------------------------*/ 2448 2449 /* Private functions----------------------------------------------------------*/ 2450 /** @defgroup TIM_Private_Functions TIM Private Functions 2451 * @{ 2452 */ 2453 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2454 #if defined(TIM_DMA_SUPPORT) 2455 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2456 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2457 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2458 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2459 #endif /* TIM_DMA_SUPPORT */ 2460 2461 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2462 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2463 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2464 2465 /** 2466 * @} 2467 */ 2468 /* End of private functions --------------------------------------------------*/ 2469 2470 /** 2471 * @} 2472 */ 2473 2474 /** 2475 * @} 2476 */ 2477 2478 #ifdef __cplusplus 2479 } 2480 #endif 2481 2482 #endif /* STM32WB0x_HAL_TIM_H */ 2483
