1 /** 2 ****************************************************************************** 3 * @file stm32wb0x_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2024 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WB0x_HAL_CORTEX_H 21 #define STM32WB0x_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wb0x_hal_def.h" 29 30 /** @addtogroup STM32WB0x_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @brief MPU Region initialization structure 47 * @{ 48 */ 49 typedef struct 50 { 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. 56 */ 57 uint8_t Size; /*!< Specifies the size of the region to protect. 58 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 59 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 60 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 61 uint8_t TypeExtField; /*!< Specifies the TEX field level. 62 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 63 uint8_t AccessPermission; /*!< Specifies the region access permission type. 64 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 65 uint8_t DisableExec; /*!< Specifies the instruction access status. 66 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 67 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 68 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 69 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 70 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 71 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 72 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 73 } MPU_Region_InitTypeDef; 74 /** 75 * @} 76 */ 77 #endif /* __MPU_PRESENT */ 78 79 /** 80 * @} 81 */ 82 83 /* Exported constants --------------------------------------------------------*/ 84 85 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 86 * @{ 87 */ 88 89 /** @defgroup CORTEX_NVIC_Priority CORTEX IRQ NVIC Priority 90 * @{ 91 */ 92 93 #define NVIC_CRITICAl_PRIORITY 0 /*!< Critical Priority */ 94 95 #define NVIC_HIGH_PRIORITY 1 /*!< High Priority */ 96 97 #define NVIC_MED_PRIORITY 2 /*!< Medium Priority */ 98 99 #define NVIC_LOW_PRIORITY 3 /*!< Low Priority */ 100 101 /** 102 * @} 103 */ 104 105 106 #if (__MPU_PRESENT == 1) 107 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 108 * @{ 109 */ 110 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 111 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 112 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 113 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 114 /** 115 * @} 116 */ 117 118 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 119 * @{ 120 */ 121 #define MPU_REGION_ENABLE ((uint8_t)0x01) 122 #define MPU_REGION_DISABLE ((uint8_t)0x00) 123 /** 124 * @} 125 */ 126 127 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 128 * @{ 129 */ 130 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 131 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 132 /** 133 * @} 134 */ 135 136 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 137 * @{ 138 */ 139 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 140 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 141 /** 142 * @} 143 */ 144 145 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 146 * @{ 147 */ 148 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 149 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 150 /** 151 * @} 152 */ 153 154 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 155 * @{ 156 */ 157 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 158 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 159 /** 160 * @} 161 */ 162 163 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 164 * @{ 165 */ 166 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 167 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 168 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 169 /** 170 * @} 171 */ 172 173 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 174 * @{ 175 */ 176 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 177 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 178 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 179 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 180 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 181 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 182 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 183 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 184 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 185 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 186 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 187 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 188 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 189 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 190 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 191 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 192 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 193 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 194 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 195 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 196 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 197 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 198 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 199 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 200 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 201 /** 202 * @} 203 */ 204 205 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 206 * @{ 207 */ 208 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 209 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 210 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 211 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 212 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 213 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 214 /** 215 * @} 216 */ 217 218 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 219 * @{ 220 */ 221 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 222 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 223 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 224 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 225 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 226 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 227 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 228 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 229 /** 230 * @} 231 */ 232 #endif /* __MPU_PRESENT */ 233 234 /** 235 * @} 236 */ 237 238 /* Exported macros -----------------------------------------------------------*/ 239 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 240 * @{ 241 */ 242 243 /** 244 * @} 245 */ 246 247 /* Exported functions --------------------------------------------------------*/ 248 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 249 * @{ 250 */ 251 252 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 253 * @brief Initialization and Configuration functions 254 * @{ 255 */ 256 /* Initialization and Configuration functions *****************************/ 257 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 258 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 259 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 260 void HAL_NVIC_SystemReset(void); 261 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 262 /** 263 * @} 264 */ 265 266 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 267 * @brief Cortex control functions 268 * @{ 269 */ 270 /* Peripheral Control functions *************************************************/ 271 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); 272 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 273 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 274 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 275 void HAL_SYSTICK_IRQHandler(void); 276 void HAL_SYSTICK_Callback(void); 277 278 #if (__MPU_PRESENT == 1U) 279 void HAL_MPU_Enable(uint32_t MPU_Control); 280 void HAL_MPU_Disable(void); 281 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 282 #endif /* __MPU_PRESENT */ 283 /** 284 * @} 285 */ 286 287 /** 288 * @} 289 */ 290 291 /* Private types -------------------------------------------------------------*/ 292 /* Private variables ---------------------------------------------------------*/ 293 /* Private constants ---------------------------------------------------------*/ 294 /* Private macros ------------------------------------------------------------*/ 295 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 296 * @{ 297 */ 298 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) 299 300 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 301 302 #if (__MPU_PRESENT == 1) 303 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 304 ((STATE) == MPU_REGION_DISABLE)) 305 306 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 307 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 308 309 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 310 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 311 312 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 313 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 314 315 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 316 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 317 318 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 319 ((TYPE) == MPU_TEX_LEVEL1) || \ 320 ((TYPE) == MPU_TEX_LEVEL2)) 321 322 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 323 ((TYPE) == MPU_REGION_PRIV_RW) || \ 324 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 325 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 326 ((TYPE) == MPU_REGION_PRIV_RO) || \ 327 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 328 329 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 330 ((NUMBER) == MPU_REGION_NUMBER1) || \ 331 ((NUMBER) == MPU_REGION_NUMBER2) || \ 332 ((NUMBER) == MPU_REGION_NUMBER3) || \ 333 ((NUMBER) == MPU_REGION_NUMBER4) || \ 334 ((NUMBER) == MPU_REGION_NUMBER5) || \ 335 ((NUMBER) == MPU_REGION_NUMBER6) || \ 336 ((NUMBER) == MPU_REGION_NUMBER7)) 337 338 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ 339 ((SIZE) == MPU_REGION_SIZE_512B) || \ 340 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 341 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 342 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 343 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 344 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 345 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 346 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 347 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 348 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 349 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 350 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 351 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 352 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 353 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 354 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 355 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 356 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 357 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 358 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 359 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 360 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 361 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 362 ((SIZE) == MPU_REGION_SIZE_4GB)) 363 364 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 365 #endif /* __MPU_PRESENT */ 366 367 /** 368 * @} 369 */ 370 371 /* Private functions ---------------------------------------------------------*/ 372 373 /** 374 * @} 375 */ 376 377 /** 378 * @} 379 */ 380 381 #ifdef __cplusplus 382 } 383 #endif 384 385 #endif /* STM32WB0x_HAL_CORTEX_H */ 386
