1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_ll_usb.h 4 * @author MCD Application Team 5 * @brief Header file of USB Low Layer HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_LL_USB_H 21 #define STM32U5xx_LL_USB_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup USB_LL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 #ifndef HAL_USB_TIMEOUT 41 #define HAL_USB_TIMEOUT 0xF000000U 42 #endif /* define HAL_USB_TIMEOUT */ 43 44 #ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS 45 #define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U 46 #endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ 47 48 /** 49 * @brief USB Mode definition 50 */ 51 52 typedef enum 53 { 54 USB_DEVICE_MODE = 0, 55 USB_HOST_MODE = 1, 56 USB_DRD_MODE = 2 57 } USB_ModeTypeDef; 58 59 /** 60 * @brief URB States definition 61 */ 62 typedef enum 63 { 64 URB_IDLE = 0, 65 URB_DONE, 66 URB_NOTREADY, 67 URB_NYET, 68 URB_ERROR, 69 URB_STALL 70 } USB_URBStateTypeDef; 71 72 /** 73 * @brief Host channel States definition 74 */ 75 typedef enum 76 { 77 HC_IDLE = 0, 78 HC_XFRC, 79 HC_HALTED, 80 HC_ACK, 81 HC_NAK, 82 HC_NYET, 83 HC_STALL, 84 HC_XACTERR, 85 HC_BBLERR, 86 HC_DATATGLERR 87 } USB_HCStateTypeDef; 88 89 90 /** 91 * @brief USB Instance Initialization Structure definition 92 */ 93 typedef struct 94 { 95 uint8_t dev_endpoints; /*!< Device Endpoints number. 96 This parameter depends on the used USB core. 97 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 98 99 uint8_t Host_channels; /*!< Host Channels number. 100 This parameter Depends on the used USB core. 101 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 102 103 uint8_t dma_enable; /*!< USB DMA state. 104 If DMA is not supported this parameter shall be set by default to zero */ 105 106 uint8_t speed; /*!< USB Core speed. 107 This parameter can be any value of @ref PCD_Speed/HCD_Speed 108 (HCD_SPEED_xxx, HCD_SPEED_xxx) */ 109 110 uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ 111 112 uint8_t phy_itface; /*!< Select the used PHY interface. 113 This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ 114 115 uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ 116 117 uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ 118 119 uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ 120 121 uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ 122 123 uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ 124 125 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 126 uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ 127 128 uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ 129 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 130 #if defined (USB_DRD_FS) 131 uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ 132 133 uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ 134 #endif /* defined (USB_DRD_FS) */ 135 } USB_CfgTypeDef; 136 137 typedef struct 138 { 139 uint8_t num; /*!< Endpoint number 140 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 141 142 uint8_t is_in; /*!< Endpoint direction 143 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 144 145 uint8_t is_stall; /*!< Endpoint stall condition 146 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 147 148 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 149 uint8_t is_iso_incomplete; /*!< Endpoint isoc condition 150 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 151 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 152 153 uint8_t type; /*!< Endpoint type 154 This parameter can be any value of @ref USB_LL_EP_Type */ 155 156 uint8_t data_pid_start; /*!< Initial data PID 157 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 158 159 #if defined (USB_DRD_FS) 160 uint16_t pmaadress; /*!< PMA Address 161 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 162 163 uint16_t pmaaddr0; /*!< PMA Address0 164 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 165 166 uint16_t pmaaddr1; /*!< PMA Address1 167 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 168 169 uint8_t doublebuffer; /*!< Double buffer enable 170 This parameter can be 0 or 1 */ 171 #endif /* defined (USB_DRD_FS) */ 172 173 uint32_t maxpacket; /*!< Endpoint Max packet size 174 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 175 176 uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ 177 178 uint32_t xfer_len; /*!< Current transfer length */ 179 180 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ 181 182 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 183 uint8_t even_odd_frame; /*!< IFrame parity 184 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 185 186 uint16_t tx_fifo_num; /*!< Transmission FIFO number 187 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 188 189 uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ 190 191 uint32_t xfer_size; /*!< requested transfer size */ 192 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 193 194 #if defined (USB_DRD_FS) 195 uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ 196 197 uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ 198 #endif /* defined (USB_DRD_FS) */ 199 } USB_EPTypeDef; 200 201 typedef struct 202 { 203 uint8_t dev_addr; /*!< USB device address. 204 This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ 205 #if defined (USB_DRD_FS) 206 uint8_t phy_ch_num; /*!< Host channel number. 207 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 208 209 uint8_t ch_dir; /*!< channel direction 210 This parameter store the physical channel direction IN/OUT/BIDIR */ 211 #else 212 uint8_t ch_num; /*!< Host channel number. 213 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 214 215 uint8_t ep_is_in; /*!< Endpoint direction 216 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 217 #endif /* defined (USB_DRD_FS) */ 218 219 uint8_t ep_num; /*!< Endpoint number. 220 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 221 uint8_t speed; /*!< USB Host Channel speed. 222 This parameter can be any value of @ref HCD_Device_Speed: 223 (HCD_DEVICE_SPEED_xxx) */ 224 225 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 226 uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ 227 uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ 228 uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ 229 uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ 230 uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ 231 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 232 233 uint8_t hub_port_nbr; /*!< USB HUB port number */ 234 uint8_t hub_addr; /*!< USB HUB address */ 235 236 uint8_t ep_type; /*!< Endpoint Type. 237 This parameter can be any value of @ref USB_LL_EP_Type */ 238 239 uint16_t max_packet; /*!< Endpoint Max packet size. 240 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 241 242 uint8_t data_pid; /*!< Initial data PID. 243 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 244 245 uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ 246 247 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 248 uint32_t XferSize; /*!< OTG Channel transfer size. */ 249 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 250 251 uint32_t xfer_len; /*!< Current transfer length. */ 252 #if defined (USB_DRD_FS) 253 uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ 254 #endif /* defined (USB_DRD_FS) */ 255 256 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ 257 258 uint8_t toggle_in; /*!< IN transfer current toggle flag. 259 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 260 261 uint8_t toggle_out; /*!< OUT transfer current toggle flag 262 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 263 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 264 uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ 265 uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ 266 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 267 268 uint32_t ErrCnt; /*!< Host channel error count. */ 269 270 #if defined (USB_DRD_FS) 271 uint16_t pmaadress; /*!< PMA Address 272 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 273 274 uint16_t pmaaddr0; /*!< PMA Address0 275 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 276 277 uint16_t pmaaddr1; /*!< PMA Address1 278 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 279 280 uint8_t doublebuffer; /*!< Double buffer enable 281 This parameter can be 0 or 1 */ 282 #endif /* defined (USB_DRD_FS) */ 283 284 USB_URBStateTypeDef urb_state; /*!< URB state. 285 This parameter can be any value of @ref USB_URBStateTypeDef */ 286 287 USB_HCStateTypeDef state; /*!< Host Channel state. 288 This parameter can be any value of @ref USB_HCStateTypeDef */ 289 } USB_HCTypeDef; 290 291 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 292 typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; 293 typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; 294 typedef USB_EPTypeDef USB_OTG_EPTypeDef; 295 typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; 296 typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; 297 typedef USB_HCTypeDef USB_OTG_HCTypeDef; 298 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 299 #if defined (USB_DRD_FS) 300 typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; 301 typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; 302 typedef USB_EPTypeDef USB_DRD_EPTypeDef; 303 typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; 304 typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; 305 typedef USB_HCTypeDef USB_DRD_HCTypeDef; 306 #endif /* defined (USB_DRD_FS) */ 307 308 /* Exported constants --------------------------------------------------------*/ 309 310 /** @defgroup PCD_Exported_Constants PCD Exported Constants 311 * @{ 312 */ 313 314 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 315 /** @defgroup USB_OTG_CORE VERSION ID 316 * @{ 317 */ 318 #define USB_OTG_CORE_ID_300A 0x4F54300AU 319 #define USB_OTG_CORE_ID_310A 0x4F54310AU 320 /** 321 * @} 322 */ 323 324 /** @defgroup USB_Core_Mode_ USB Core Mode 325 * @{ 326 */ 327 #define USB_OTG_MODE_DEVICE 0U 328 #define USB_OTG_MODE_HOST 1U 329 #define USB_OTG_MODE_DRD 2U 330 /** 331 * @} 332 */ 333 334 /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed 335 * @{ 336 */ 337 #define USB_OTG_SPEED_HIGH 0U 338 #define USB_OTG_SPEED_HIGH_IN_FULL 1U 339 #define USB_OTG_SPEED_FULL 3U 340 /** 341 * @} 342 */ 343 344 /** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY 345 * @{ 346 */ 347 #define USB_OTG_EMBEDDED_PHY 2U 348 #define USB_OTG_HS_EMBEDDED_PHY 3U 349 /** 350 * @} 351 */ 352 353 /** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value 354 * @{ 355 */ 356 #ifndef USBD_HS_TRDT_VALUE 357 #define USBD_HS_TRDT_VALUE 9U 358 #endif /* USBD_HS_TRDT_VALUE */ 359 #ifndef USBD_FS_TRDT_VALUE 360 #define USBD_FS_TRDT_VALUE 5U 361 #define USBD_DEFAULT_TRDT_VALUE 9U 362 #endif /* USBD_HS_TRDT_VALUE */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS 368 * @{ 369 */ 370 #define USB_OTG_HS_MAX_PACKET_SIZE 512U 371 #define USB_OTG_FS_MAX_PACKET_SIZE 64U 372 #define USB_OTG_MAX_EP0_SIZE 64U 373 /** 374 * @} 375 */ 376 377 /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency 378 * @{ 379 */ 380 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) 381 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) 382 #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) 383 /** 384 * @} 385 */ 386 387 /** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval 388 * @{ 389 */ 390 #define DCFG_FRAME_INTERVAL_80 0U 391 #define DCFG_FRAME_INTERVAL_85 1U 392 #define DCFG_FRAME_INTERVAL_90 2U 393 #define DCFG_FRAME_INTERVAL_95 3U 394 /** 395 * @} 396 */ 397 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 398 /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS 399 * @{ 400 */ 401 #define EP_MPS_64 0U 402 #define EP_MPS_32 1U 403 #define EP_MPS_16 2U 404 #define EP_MPS_8 3U 405 /** 406 * @} 407 */ 408 409 /** @defgroup USB_LL_EP_Type USB Low Layer EP Type 410 * @{ 411 */ 412 #define EP_TYPE_CTRL 0U 413 #define EP_TYPE_ISOC 1U 414 #define EP_TYPE_BULK 2U 415 #define EP_TYPE_INTR 3U 416 #define EP_TYPE_MSK 3U 417 /** 418 * @} 419 */ 420 421 /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed 422 * @{ 423 */ 424 #define EP_SPEED_LOW 0U 425 #define EP_SPEED_FULL 1U 426 #define EP_SPEED_HIGH 2U 427 /** 428 * @} 429 */ 430 431 /** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type 432 * @{ 433 */ 434 #define HC_PID_DATA0 0U 435 #define HC_PID_DATA2 1U 436 #define HC_PID_DATA1 2U 437 #define HC_PID_SETUP 3U 438 /** 439 * @} 440 */ 441 442 /** @defgroup USB_LL Device Speed 443 * @{ 444 */ 445 #define USBD_HS_SPEED 0U 446 #define USBD_HSINFS_SPEED 1U 447 #define USBH_HS_SPEED 0U 448 #define USBD_FS_SPEED 2U 449 #define USBH_FSLS_SPEED 1U 450 /** 451 * @} 452 */ 453 454 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 455 /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines 456 * @{ 457 */ 458 #define STS_GOUT_NAK 1U 459 #define STS_DATA_UPDT 2U 460 #define STS_XFER_COMP 3U 461 #define STS_SETUP_COMP 4U 462 #define STS_SETUP_UPDT 6U 463 /** 464 * @} 465 */ 466 467 /** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines 468 * @{ 469 */ 470 #define HCFG_30_60_MHZ 0U 471 #define HCFG_48_MHZ 1U 472 #define HCFG_6_MHZ 2U 473 /** 474 * @} 475 */ 476 477 /** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines 478 * @{ 479 */ 480 #define HFIR_6_MHZ 6000U 481 #define HFIR_60_MHZ 60000U 482 #define HFIR_48_MHZ 48000U 483 /** 484 * @} 485 */ 486 487 /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines 488 * @{ 489 */ 490 #define HPRT0_PRTSPD_HIGH_SPEED 0U 491 #define HPRT0_PRTSPD_FULL_SPEED 1U 492 #define HPRT0_PRTSPD_LOW_SPEED 2U 493 /** 494 * @} 495 */ 496 497 #define HCCHAR_CTRL 0U 498 #define HCCHAR_ISOC 1U 499 #define HCCHAR_BULK 2U 500 #define HCCHAR_INTR 3U 501 502 #define GRXSTS_PKTSTS_IN 2U 503 #define GRXSTS_PKTSTS_IN_XFER_COMP 3U 504 #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U 505 #define GRXSTS_PKTSTS_CH_HALTED 7U 506 507 #define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU 508 509 #define HC_MAX_PKT_CNT 256U 510 #define ISO_SPLT_MPS 188U 511 512 #define HCSPLT_BEGIN 1U 513 #define HCSPLT_MIDDLE 2U 514 #define HCSPLT_END 3U 515 #define HCSPLT_FULL 4U 516 517 #define TEST_J 1U 518 #define TEST_K 2U 519 #define TEST_SE0_NAK 3U 520 #define TEST_PACKET 4U 521 #define TEST_FORCE_EN 5U 522 523 #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) 524 #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) 525 526 #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) 527 #define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ 528 + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) 529 530 #define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ 531 + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) 532 533 #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) 534 535 #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) 536 #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ 537 + USB_OTG_HOST_CHANNEL_BASE\ 538 + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) 539 540 541 #define EP_ADDR_MSK 0xFU 542 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 543 #if defined (USB_DRD_FS) 544 #define EP_ADDR_MSK 0x7U 545 546 #ifndef USE_USB_DOUBLE_BUFFER 547 #define USE_USB_DOUBLE_BUFFER 1U 548 #endif /* USE_USB_DOUBLE_BUFFER */ 549 550 #define USB_EMBEDDED_PHY 2U 551 552 /*!< USB Speed */ 553 #define USB_DRD_SPEED_FS 1U 554 #define USB_DRD_SPEED_LS 2U 555 #define USB_DRD_SPEED_LSFS 3U 556 557 /*!< Channel Direction */ 558 #define CH_IN_DIR 1U 559 #define CH_OUT_DIR 0U 560 561 /*!< Number of used channels in the Application */ 562 #ifndef USB_DRD_USED_CHANNELS 563 #define USB_DRD_USED_CHANNELS 8U 564 #endif /* USB_DRD_USED_CHANNELS */ 565 566 /** 567 * used for USB_HC_DoubleBuffer API 568 */ 569 #define USB_DRD_BULK_DBUFF_ENBALE 1U 570 #define USB_DRD_BULK_DBUFF_DISABLE 2U 571 #define USB_DRD_ISOC_DBUFF_ENBALE 3U 572 #define USB_DRD_ISOC_DBUFF_DISABLE 4U 573 574 /* First available address in PMA */ 575 #define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) 576 #define PMA_END_ADDR USB_DRD_PMA_SIZE 577 578 /* Exported macro ------------------------------------------------------------*/ 579 /** 580 * @} 581 */ 582 /******************** Bit definition for USB_COUNTn_RX register *************/ 583 #define USB_CNTRX_NBLK_MSK (0x1FU << 26) 584 #define USB_CNTRX_BLSIZE (0x1U << 31) 585 586 587 /*Set Channel/Endpoint to the USB Register */ 588 #define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ 589 (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) 590 591 /*Get Channel/Endpoint from the USB Register */ 592 #define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) 593 594 595 /** 596 * @brief free buffer used from the application realizing it to the line 597 * toggles bit SW_BUF in the double buffered endpoint register 598 * @param USBx USB device. 599 * @param bEpChNum, bDir 600 * @retval None 601 */ 602 #define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ 603 do { \ 604 if ((bDir) == 0U) \ 605 { \ 606 /* OUT double buffered endpoint */ \ 607 USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ 608 } \ 609 else if ((bDir) == 1U) \ 610 { \ 611 /* IN double buffered endpoint */ \ 612 USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ 613 } \ 614 } while(0) 615 616 617 /** 618 * @brief Set the Setup bit in the corresponding channel, when a Setup 619 transaction is needed. 620 * @param USBx USB device. 621 * @param bEpChNum 622 * @retval None 623 */ 624 #define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ 625 do { \ 626 uint32_t _wRegVal; \ 627 \ 628 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ 629 \ 630 /* Set Setup bit */ \ 631 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ 632 } while(0) 633 634 635 /** 636 * @brief Clears bit ERR_RX in the Channel register 637 * @param USBx USB peripheral instance register address. 638 * @param bChNum Endpoint Number. 639 * @retval None 640 */ 641 #define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ 642 do { \ 643 uint32_t _wRegVal; \ 644 \ 645 _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ 646 _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ 647 (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ 648 \ 649 USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ 650 } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ 651 652 653 /** 654 * @brief Clears bit ERR_TX in the Channel register 655 * @param USBx USB peripheral instance register address. 656 * @param bChNum Endpoint Number. 657 * @retval None 658 */ 659 #define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ 660 do { \ 661 uint32_t _wRegVal; \ 662 \ 663 _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ 664 _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ 665 (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ 666 \ 667 USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ 668 } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ 669 670 671 /** 672 * @brief sets the status for tx transfer (bits STAT_TX[1:0]). 673 * @param USBx USB peripheral instance register address. 674 * @param bEpChNum Endpoint Number. 675 * @param wState new state 676 * @retval None 677 */ 678 #define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ 679 do { \ 680 uint32_t _wRegVal; \ 681 \ 682 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ 683 /* toggle first bit ? */ \ 684 if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ 685 { \ 686 _wRegVal ^= USB_CHEP_TX_DTOG1; \ 687 } \ 688 /* toggle second bit ? */ \ 689 if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ 690 { \ 691 _wRegVal ^= USB_CHEP_TX_DTOG2; \ 692 } \ 693 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ 694 } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ 695 696 697 /** 698 * @brief sets the status for rx transfer (bits STAT_TX[1:0]) 699 * @param USBx USB peripheral instance register address. 700 * @param bEpChNum Endpoint Number. 701 * @param wState new state 702 * @retval None 703 */ 704 #define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ 705 do { \ 706 uint32_t _wRegVal; \ 707 \ 708 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ 709 /* toggle first bit ? */ \ 710 if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ 711 { \ 712 _wRegVal ^= USB_CHEP_RX_DTOG1; \ 713 } \ 714 /* toggle second bit ? */ \ 715 if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ 716 { \ 717 _wRegVal ^= USB_CHEP_RX_DTOG2; \ 718 } \ 719 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 720 } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ 721 722 723 /** 724 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] 725 * /STAT_RX[1:0]) 726 * @param USBx USB peripheral instance register address. 727 * @param bEpChNum Endpoint Number. 728 * @retval status 729 */ 730 #define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ 731 ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) 732 733 #define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ 734 ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) 735 736 737 /** 738 * @brief set EP_KIND bit. 739 * @param USBx USB peripheral instance register address. 740 * @param bEpChNum Endpoint Number. 741 * @retval None 742 */ 743 #define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ 744 do { \ 745 uint32_t _wRegVal; \ 746 \ 747 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 748 \ 749 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ 750 } while(0) /* USB_DRD_SET_CHEP_KIND */ 751 752 753 /** 754 * @brief clear EP_KIND bit. 755 * @param USBx USB peripheral instance register address. 756 * @param bEpChNum Endpoint Number. 757 * @retval None 758 */ 759 #define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ 760 do { \ 761 uint32_t _wRegVal; \ 762 \ 763 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ 764 \ 765 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 766 } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ 767 768 769 /** 770 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. 771 * @param USBx USB peripheral instance register address. 772 * @param bEpChNum Endpoint Number. 773 * @retval None 774 */ 775 #define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ 776 do { \ 777 uint32_t _wRegVal; \ 778 \ 779 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ 780 \ 781 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ 782 } while(0) /* USB_CLEAR_RX_CHEP_CTR */ 783 784 #define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ 785 do { \ 786 uint32_t _wRegVal; \ 787 \ 788 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ 789 \ 790 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ 791 } while(0) /* USB_CLEAR_TX_CHEP_CTR */ 792 793 794 /** 795 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 796 * @param USBx USB peripheral instance register address. 797 * @param bEpChNum Endpoint Number. 798 * @retval None 799 */ 800 #define USB_DRD_RX_DTOG(USBx, bEpChNum) \ 801 do { \ 802 uint32_t _wEPVal; \ 803 \ 804 _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 805 \ 806 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ 807 } while(0) /* USB_DRD_RX_DTOG */ 808 809 #define USB_DRD_TX_DTOG(USBx, bEpChNum) \ 810 do { \ 811 uint32_t _wEPVal; \ 812 \ 813 _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 814 \ 815 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ 816 } while(0) /* USB_TX_DTOG */ 817 818 819 /** 820 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. 821 * @param USBx USB peripheral instance register address. 822 * @param bEpChNum Endpoint Number. 823 * @retval None 824 */ 825 #define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ 826 do { \ 827 uint32_t _wRegVal; \ 828 \ 829 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ 830 \ 831 if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ 832 { \ 833 USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ 834 } \ 835 } while(0) /* USB_DRD_CLEAR_RX_DTOG */ 836 837 #define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ 838 do { \ 839 uint32_t _wRegVal; \ 840 \ 841 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ 842 \ 843 if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ 844 { \ 845 USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ 846 } \ 847 } while(0) /* USB_DRD_CLEAR_TX_DTOG */ 848 849 850 /** 851 * @brief Sets address in an endpoint register. 852 * @param USBx USB peripheral instance register address. 853 * @param bEpChNum Endpoint Number. 854 * @param bAddr Address. 855 * @retval None 856 */ 857 #define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ 858 do { \ 859 uint32_t _wRegVal; \ 860 \ 861 /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ 862 _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ 863 \ 864 /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ 865 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 866 } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ 867 868 869 /* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ 870 /* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor 871 * The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) 872 * TXBD [Reserve |Countx| Address_Tx] 873 * RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ 874 875 /* Set TX Buffer Descriptor Address Field */ 876 #define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ 877 do { \ 878 /* Reset old Address */ \ 879 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ 880 \ 881 /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ 882 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ 883 } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ 884 885 /* Set RX Buffer Descriptor Address Field */ 886 #define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ 887 do { \ 888 /* Reset old Address */ \ 889 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ 890 \ 891 /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ 892 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ 893 } while(0) /* USB_SET_CHEP_RX_ADDRESS */ 894 895 896 /** 897 * @brief Sets counter of rx buffer with no. of blocks. 898 * @param pdwReg Register pointer 899 * @param wCount Counter. 900 * @param wNBlocks no. of Blocks. 901 * @retval None 902 */ 903 #define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ 904 do { \ 905 /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ 906 (wNBlocks) =((uint32_t)(wCount) >> 5U); \ 907 if (((uint32_t)(wCount) % 32U) == 0U) \ 908 { \ 909 (wNBlocks)--; \ 910 } \ 911 \ 912 (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ 913 } while(0) /* USB_DRD_CALC_BLK32 */ 914 915 #define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ 916 do { \ 917 /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ 918 (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ 919 if (((wCount) & 0x1U) != 0U) \ 920 { \ 921 (wNBlocks)++; \ 922 } \ 923 (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ 924 } while(0) /* USB_DRD_CALC_BLK2 */ 925 926 #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ 927 do { \ 928 uint32_t wNBlocks; \ 929 \ 930 (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ 931 \ 932 if ((wCount) == 0U) \ 933 { \ 934 (pdwReg) |= USB_CNTRX_BLSIZE; \ 935 } \ 936 else if ((wCount) <= 62U) \ 937 { \ 938 USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ 939 } \ 940 else \ 941 { \ 942 USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ 943 } \ 944 } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ 945 946 947 /** 948 * @brief sets counter for the tx/rx buffer. 949 * @param USBx USB peripheral instance register address. 950 * @param bEpChNum Endpoint Number. 951 * @param wCount Counter value. 952 * @retval None 953 */ 954 #define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ 955 do { \ 956 /* Reset old TX_Count value */ \ 957 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ 958 \ 959 /* Set the wCount in the dedicated EP_TXBuffer */ \ 960 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ 961 } while(0) 962 963 #define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ 964 USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) 965 966 #define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ 967 USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) 968 969 /** 970 * @brief gets counter of the tx buffer. 971 * @param USBx USB peripheral instance register address. 972 * @param bEpChNum Endpoint Number. 973 * @retval Counter value 974 */ 975 #define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) 976 #define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) 977 978 #define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT 979 #define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT 980 981 #define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT 982 #define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT 983 /** 984 * @brief Sets buffer 0/1 address in a double buffer endpoint. 985 * @param USBx USB peripheral instance register address. 986 * @param bEpChNum Endpoint Number. 987 * @param wBuf0Addr buffer 0 address. 988 * @retval Counter value 989 */ 990 #define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ 991 USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) 992 993 #define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ 994 USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) 995 996 997 /** 998 * @brief Sets addresses in a double buffer endpoint. 999 * @param USBx USB peripheral instance register address. 1000 * @param bEpChNum Endpoint Number. 1001 * @param wBuf0Addr: buffer 0 address. 1002 * @param wBuf1Addr = buffer 1 address. 1003 * @retval None 1004 */ 1005 #define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ 1006 do { \ 1007 USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ 1008 USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ 1009 } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ 1010 1011 1012 /** 1013 * @brief Gets buffer 0/1 address of a double buffer endpoint. 1014 * @param USBx USB peripheral instance register address. 1015 * @param bEpChNum Endpoint Number. 1016 * @param bDir endpoint dir EP_DBUF_OUT = OUT 1017 * EP_DBUF_IN = IN 1018 * @param wCount: Counter value 1019 * @retval None 1020 */ 1021 #define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ 1022 do { \ 1023 if ((bDir) == 0U) \ 1024 { \ 1025 /* OUT endpoint */ \ 1026 USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ 1027 } \ 1028 else \ 1029 { \ 1030 if ((bDir) == 1U) \ 1031 { \ 1032 /* IN endpoint */ \ 1033 USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ 1034 } \ 1035 } \ 1036 } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ 1037 1038 #define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ 1039 do { \ 1040 if ((bDir) == 0U) \ 1041 { \ 1042 /* OUT endpoint */ \ 1043 USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ 1044 } \ 1045 else \ 1046 { \ 1047 if ((bDir) == 1U) \ 1048 { \ 1049 /* IN endpoint */ \ 1050 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ 1051 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ 1052 } \ 1053 } \ 1054 } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ 1055 1056 #define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ 1057 do { \ 1058 USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ 1059 USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ 1060 } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ 1061 1062 /** 1063 * @brief Gets buffer 0/1 rx/tx counter for double buffering. 1064 * @param USBx USB peripheral instance register address. 1065 * @param bEpChNum Endpoint Number. 1066 * @retval None 1067 */ 1068 #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) 1069 #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) 1070 #endif /* defined (USB_DRD_FS) */ 1071 /** 1072 * @} 1073 */ 1074 1075 /* Exported macro ------------------------------------------------------------*/ 1076 /** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros 1077 * @{ 1078 */ 1079 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 1080 #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) 1081 #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) 1082 1083 #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) 1084 #define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) 1085 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 1086 /** 1087 * @} 1088 */ 1089 1090 /* Exported functions --------------------------------------------------------*/ 1091 /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions 1092 * @{ 1093 */ 1094 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 1095 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); 1096 HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); 1097 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); 1098 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); 1099 HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); 1100 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); 1101 HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); 1102 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); 1103 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); 1104 HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); 1105 HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); 1106 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); 1107 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); 1108 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); 1109 HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, 1110 uint8_t ch_ep_num, uint16_t len, uint8_t dma); 1111 1112 void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); 1113 HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); 1114 HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); 1115 HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); 1116 HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); 1117 HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); 1118 HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); 1119 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); 1120 HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); 1121 HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); 1122 uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); 1123 uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); 1124 uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); 1125 uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); 1126 uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); 1127 uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); 1128 uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); 1129 uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); 1130 void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); 1131 1132 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); 1133 HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); 1134 HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); 1135 HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); 1136 uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); 1137 uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); 1138 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, 1139 uint8_t epnum, uint8_t dev_address, uint8_t speed, 1140 uint8_t ep_type, uint16_t mps); 1141 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, 1142 USB_OTG_HCTypeDef *hc, uint8_t dma); 1143 1144 uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); 1145 HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); 1146 HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); 1147 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); 1148 HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); 1149 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); 1150 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 1151 1152 #if defined (USB_DRD_FS) 1153 HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 1154 HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 1155 HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); 1156 HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); 1157 HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); 1158 1159 HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); 1160 HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); 1161 1162 #if defined (HAL_PCD_MODULE_ENABLED) 1163 HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1164 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1165 HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1166 HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1167 HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1168 HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 1169 #endif /* defined (HAL_PCD_MODULE_ENABLED) */ 1170 1171 HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); 1172 HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); 1173 HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); 1174 HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); 1175 uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); 1176 1177 HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); 1178 HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 1179 HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); 1180 HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); 1181 HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); 1182 1183 uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); 1184 uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); 1185 HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); 1186 HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); 1187 HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, 1188 uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); 1189 1190 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); 1191 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); 1192 1193 void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, 1194 uint16_t wPMABufAddr, uint16_t wNBytes); 1195 1196 void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, 1197 uint16_t wPMABufAddr, uint16_t wNBytes); 1198 #endif /* defined (USB_DRD_FS) */ 1199 /** 1200 * @} 1201 */ 1202 1203 /** 1204 * @} 1205 */ 1206 1207 /** 1208 * @} 1209 */ 1210 1211 /** 1212 * @} 1213 */ 1214 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ 1215 1216 #ifdef __cplusplus 1217 } 1218 #endif /* __cplusplus */ 1219 1220 1221 #endif /* STM32U5xx_LL_USB_H */ 1222
