1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_LL_SDMMC_H 21 #define STM32U5xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SDMMC_LL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SDMMC Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. 49 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 50 51 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 52 disabled when the bus is idle. 53 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 54 55 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 56 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 57 58 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 59 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 60 61 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 62 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 63 64 #if (USE_SD_TRANSCEIVER != 0U) 65 uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. 66 This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ 67 #endif /* USE_SD_TRANSCEIVER */ 68 } SDMMC_InitTypeDef; 69 70 71 /** 72 * @brief SDMMC Command Control structure 73 */ 74 typedef struct 75 { 76 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 77 to a card as part of a command message. If a command 78 contains an argument, it must be loaded into this register 79 before writing the command to the command register. */ 80 81 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 82 Max_Data = 64 */ 83 84 uint32_t Response; /*!< Specifies the SDMMC response type. 85 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 86 87 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 88 enabled or disabled. 89 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 90 91 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 92 is enabled or disabled. 93 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 94 } SDMMC_CmdInitTypeDef; 95 96 97 /** 98 * @brief SDMMC Data Control structure 99 */ 100 typedef struct 101 { 102 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 103 104 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 105 106 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 107 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 108 109 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 110 is a read or write. 111 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 112 113 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 114 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 115 116 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 117 is enabled or disabled. 118 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 119 } SDMMC_DataInitTypeDef; 120 121 /** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure 122 * @{ 123 */ 124 typedef struct 125 { 126 __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list configuration register */ 127 __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register */ 128 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register */ 129 } SDMMC_DMALinkNodeTypeDef; 130 131 typedef struct 132 { 133 uint32_t BufferAddress; /*!< Node Buffer address */ 134 uint32_t BufferSize ; /*!< Node Buffer size */ 135 } SDMMC_DMALinkNodeConfTypeDef; 136 137 typedef struct 138 { 139 SDMMC_DMALinkNodeTypeDef *pHeadNode; /*!< Linked List Node Head */ 140 SDMMC_DMALinkNodeTypeDef *pTailNode; /*!< Linked List Node Head */ 141 uint32_t NodesCounter ; /*!< Node is ready for execution */ 142 } SDMMC_DMALinkedListTypeDef; 143 /** 144 * @} 145 */ 146 147 /* Exported constants --------------------------------------------------------*/ 148 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 149 * @{ 150 */ 151 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 152 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 153 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 154 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 155 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 156 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 157 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 158 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 159 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ 160 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 161 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 162 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 163 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ 164 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 165 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 166 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 167 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 168 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 169 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 170 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 171 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 172 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 173 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 174 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ 175 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 176 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 177 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 178 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 179 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 180 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 181 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 182 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 183 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 184 185 /** 186 * @brief SDMMC Commands Index 187 */ 188 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 189 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 190 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 191 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 192 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 193 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ 194 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 195 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 196 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ 197 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 198 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 199 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 200 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 201 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 202 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 203 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 204 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ 205 /*!< for SDHS and SDXC. */ 206 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 207 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ 208 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 209 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 210 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 211 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 212 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 213 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 214 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 215 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 216 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 217 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 218 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 219 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 220 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ 221 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ 222 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 223 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 224 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 225 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ 226 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ 227 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ 228 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 229 230 /** 231 * @brief Following commands are SD Card Specific commands. 232 * SDMMC_APP_CMD should be sent before sending these commands. 233 */ 234 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ 235 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 236 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ 237 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ 238 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 239 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 240 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 241 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 242 243 /** 244 * @brief Following commands are SD Card Specific security commands. 245 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 246 */ 247 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 248 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 249 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 250 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 251 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 252 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 253 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 254 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 255 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 256 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 257 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 258 259 /** 260 * @brief Masks for errors Card Status R1 (OCR Register) 261 */ 262 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 263 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 264 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 265 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 266 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 267 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 268 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 269 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 270 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 271 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 272 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 273 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 274 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 275 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 276 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 277 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 278 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 279 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 280 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 281 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 282 283 /** 284 * @brief Masks for R6 Response 285 */ 286 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 287 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 288 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 289 290 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 291 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 292 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 293 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 294 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 295 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 296 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 297 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 298 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 299 300 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 301 302 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 303 304 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 305 306 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 307 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 308 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 309 310 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 311 312 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 313 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 314 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 315 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 316 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 317 318 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 319 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 320 321 /** 322 * @brief Command Class supported 323 */ 324 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 325 326 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 327 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 328 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 329 330 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 331 * @{ 332 */ 333 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 334 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 335 336 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 337 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 338 /** 339 * @} 340 */ 341 342 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 343 * @{ 344 */ 345 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 346 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 347 348 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 349 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 350 /** 351 * @} 352 */ 353 354 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 355 * @{ 356 */ 357 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 358 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 359 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 360 361 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 362 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 363 ((WIDE) == SDMMC_BUS_WIDE_8B)) 364 /** 365 * @} 366 */ 367 368 /** @defgroup SDMMC_LL_Speed_Mode 369 * @{ 370 */ 371 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 372 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 373 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 374 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 375 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 376 377 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 378 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 379 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 380 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 381 ((MODE) == SDMMC_SPEED_MODE_DDR)) 382 383 /** 384 * @} 385 */ 386 387 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 388 * @{ 389 */ 390 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 391 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 392 393 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 394 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 395 /** 396 * @} 397 */ 398 399 /** @defgroup SDMMC_LL_Clock_Division Clock Division 400 * @{ 401 */ 402 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 403 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 404 /** 405 * @} 406 */ 407 408 /** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present 409 * @{ 410 */ 411 #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) 412 #define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) 413 #define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) 414 415 /** 416 * @} 417 */ 418 419 /** @defgroup SDMMC_LL_Command_Index Command Index 420 * @{ 421 */ 422 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 423 /** 424 * @} 425 */ 426 427 /** @defgroup SDMMC_LL_Response_Type Response Type 428 * @{ 429 */ 430 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 431 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 432 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 433 434 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 435 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 436 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 437 /** 438 * @} 439 */ 440 441 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 442 * @{ 443 */ 444 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 445 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 446 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 447 448 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 449 ((WAIT) == SDMMC_WAIT_IT) || \ 450 ((WAIT) == SDMMC_WAIT_PEND)) 451 /** 452 * @} 453 */ 454 455 /** @defgroup SDMMC_LL_CPSM_State CPSM State 456 * @{ 457 */ 458 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 459 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 460 461 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 462 ((CPSM) == SDMMC_CPSM_ENABLE)) 463 /** 464 * @} 465 */ 466 467 /** @defgroup SDMMC_LL_Response_Registers Response Register 468 * @{ 469 */ 470 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 471 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 472 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 473 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 474 475 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 476 ((RESP) == SDMMC_RESP2) || \ 477 ((RESP) == SDMMC_RESP3) || \ 478 ((RESP) == SDMMC_RESP4)) 479 480 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 481 * @{ 482 */ 483 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 484 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 485 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 486 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 487 488 /** 489 * @} 490 */ 491 492 /** @defgroup SDMMC_LL_Data_Length Data Length 493 * @{ 494 */ 495 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 496 /** 497 * @} 498 */ 499 500 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 501 * @{ 502 */ 503 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 504 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 505 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 506 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 507 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 508 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 509 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 510 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 511 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 512 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 513 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 514 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 515 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 516 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 517 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 518 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 519 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 520 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ 521 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 522 523 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 524 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 525 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 526 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 527 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 528 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 529 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 530 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 531 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 532 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 533 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 534 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 535 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 536 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 537 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 538 /** 539 * @} 540 */ 541 542 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 543 * @{ 544 */ 545 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 546 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 547 548 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 549 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 550 /** 551 * @} 552 */ 553 554 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 555 * @{ 556 */ 557 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 558 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 559 560 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 561 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 562 /** 563 * @} 564 */ 565 566 /** @defgroup SDMMC_LL_DPSM_State DPSM State 567 * @{ 568 */ 569 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 570 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 571 572 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 573 ((DPSM) == SDMMC_DPSM_ENABLE)) 574 /** 575 * @} 576 */ 577 578 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 579 * @{ 580 */ 581 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 582 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 583 584 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 585 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 586 /** 587 * @} 588 */ 589 590 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 591 * @{ 592 */ 593 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 594 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 595 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 596 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 597 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 598 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 599 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 600 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 601 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 602 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 603 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 604 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 605 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 606 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 607 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 608 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 609 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 610 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 611 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 612 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 613 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 614 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 615 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 616 /** 617 * @} 618 */ 619 620 /** @defgroup SDMMC_LL_Flags Flags 621 * @{ 622 */ 623 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 624 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 625 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 626 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 627 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 628 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 629 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 630 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 631 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 632 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 633 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 634 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 635 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 636 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 637 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 638 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 639 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 640 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 641 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 642 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 643 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 644 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 645 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 646 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 647 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 648 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 649 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 650 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 651 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 652 653 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 654 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 655 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 656 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 657 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 658 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 659 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 660 661 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 662 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 663 664 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 665 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 666 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 667 SDMMC_FLAG_IDMABTC)) 668 /** 669 * @} 670 */ 671 672 /** 673 * @} 674 */ 675 676 /* Exported macro ------------------------------------------------------------*/ 677 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 678 * @{ 679 */ 680 681 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 682 * @brief SDMMC_LL registers bit address in the alias region 683 * @{ 684 */ 685 /* ---------------------- SDMMC registers bit mask --------------------------- */ 686 /* --- CLKCR Register ---*/ 687 /* CLKCR register clear mask */ 688 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 689 SDMMC_CLKCR_WIDBUS |\ 690 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 691 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 692 SDMMC_CLKCR_SELCLKRX)) 693 694 /* --- DCTRL Register ---*/ 695 /* SDMMC DCTRL Clear Mask */ 696 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 697 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 698 699 /* --- CMD Register ---*/ 700 /* CMD Register clear mask */ 701 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 702 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 703 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 704 705 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/ 706 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) 707 708 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/ 709 #define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4) 710 711 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/ 712 #define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) 713 /** 714 * @} 715 */ 716 717 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 718 * @brief macros to handle interrupts and specific clock configurations 719 * @{ 720 */ 721 722 /** 723 * @brief Enable the SDMMC device interrupt. 724 * @param __INSTANCE__ Pointer to SDMMC register base 725 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 726 * This parameter can be one or a combination of the following values: 727 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 728 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 729 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 730 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 731 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 732 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 733 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 734 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 735 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 736 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 737 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 738 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 739 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 740 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 741 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 742 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 743 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 744 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 745 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 746 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 747 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 748 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 749 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 750 * @retval None 751 */ 752 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 753 754 /** 755 * @brief Disable the SDMMC device interrupt. 756 * @param __INSTANCE__ Pointer to SDMMC register base 757 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 758 * This parameter can be one or a combination of the following values: 759 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 760 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 761 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 762 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 763 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 764 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 765 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 766 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 767 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 768 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 769 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 770 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 771 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 772 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 773 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 774 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 775 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 776 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 777 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 778 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 779 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 780 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 781 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 782 * @retval None 783 */ 784 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 785 786 /** 787 * @brief Checks whether the specified SDMMC flag is set or not. 788 * @param __INSTANCE__ Pointer to SDMMC register base 789 * @param __FLAG__ specifies the flag to check. 790 * This parameter can be one of the following values: 791 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 792 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 793 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 794 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 795 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 796 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 797 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 798 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 799 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 800 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 801 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 802 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 803 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 804 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 805 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 806 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 807 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 808 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 809 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 810 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 811 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 812 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 813 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 814 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 815 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 816 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 817 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 818 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 819 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 820 * @retval The new state of SDMMC_FLAG (SET or RESET). 821 */ 822 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 823 824 825 /** 826 * @brief Clears the SDMMC pending flags. 827 * @param __INSTANCE__ Pointer to SDMMC register base 828 * @param __FLAG__ specifies the flag to clear. 829 * This parameter can be one or a combination of the following values: 830 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 831 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 832 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 833 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 834 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 835 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 836 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 837 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 838 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 839 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 840 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 841 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 842 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 843 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 844 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 845 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 846 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 847 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 848 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 849 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 850 * @retval None 851 */ 852 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 853 854 /** 855 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 856 * @param __INSTANCE__ Pointer to SDMMC register base 857 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 858 * This parameter can be one of the following values: 859 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 860 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 861 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 862 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 863 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 864 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 865 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 866 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 867 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 868 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 869 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 870 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 871 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 872 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 873 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 874 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 875 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 876 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 877 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 878 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 879 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 880 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 881 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 882 * @retval The new state of SDMMC_IT (SET or RESET). 883 */ 884 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 885 886 /** 887 * @brief Clears the SDMMC's interrupt pending bits. 888 * @param __INSTANCE__ Pointer to SDMMC register base 889 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 890 * This parameter can be one or a combination of the following values: 891 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 892 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 893 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 894 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 895 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 896 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 897 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 898 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 899 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 900 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 901 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 902 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 903 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 904 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 905 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 906 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 907 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 908 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 909 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 910 * @retval None 911 */ 912 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 913 914 /** 915 * @brief Enable Start the SD I/O Read Wait operation. 916 * @param __INSTANCE__ Pointer to SDMMC register base 917 * @retval None 918 */ 919 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 920 921 /** 922 * @brief Disable Start the SD I/O Read Wait operations. 923 * @param __INSTANCE__ Pointer to SDMMC register base 924 * @retval None 925 */ 926 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 927 928 /** 929 * @brief Enable Start the SD I/O Read Wait operation. 930 * @param __INSTANCE__ Pointer to SDMMC register base 931 * @retval None 932 */ 933 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 934 935 /** 936 * @brief Disable Stop the SD I/O Read Wait operations. 937 * @param __INSTANCE__ Pointer to SDMMC register base 938 * @retval None 939 */ 940 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 941 942 /** 943 * @brief Enable the SD I/O Mode Operation. 944 * @param __INSTANCE__ Pointer to SDMMC register base 945 * @retval None 946 */ 947 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 948 949 /** 950 * @brief Disable the SD I/O Mode Operation. 951 * @param __INSTANCE__ Pointer to SDMMC register base 952 * @retval None 953 */ 954 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 955 956 /** 957 * @brief Enable the SD I/O Suspend command sending. 958 * @param __INSTANCE__ Pointer to SDMMC register base 959 * @retval None 960 */ 961 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 962 963 /** 964 * @brief Disable the SD I/O Suspend command sending. 965 * @param __INSTANCE__ Pointer to SDMMC register base 966 * @retval None 967 */ 968 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 969 970 /** 971 * @brief Enable the CMDTRANS mode. 972 * @param __INSTANCE__ Pointer to SDMMC register base 973 * @retval None 974 */ 975 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 976 977 /** 978 * @brief Disable the CMDTRANS mode. 979 * @param __INSTANCE__ Pointer to SDMMC register base 980 * @retval None 981 */ 982 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 983 984 /** 985 * @brief Enable the CMDSTOP mode. 986 * @param __INSTANCE__ Pointer to SDMMC register base 987 * @retval None 988 */ 989 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 990 991 /** 992 * @brief Disable the CMDSTOP mode. 993 * @param __INSTANCE__ Pointer to SDMMC register base 994 * @retval None 995 */ 996 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 997 998 /** 999 * @} 1000 */ 1001 1002 /** 1003 * @} 1004 */ 1005 1006 /* Exported functions --------------------------------------------------------*/ 1007 /** @addtogroup SDMMC_LL_Exported_Functions 1008 * @{ 1009 */ 1010 1011 /* Initialization/de-initialization functions **********************************/ 1012 /** @addtogroup HAL_SDMMC_LL_Group1 1013 * @{ 1014 */ 1015 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1016 /** 1017 * @} 1018 */ 1019 1020 /* I/O operation functions *****************************************************/ 1021 /** @addtogroup HAL_SDMMC_LL_Group2 1022 * @{ 1023 */ 1024 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 1025 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1026 /** 1027 * @} 1028 */ 1029 1030 /* Peripheral Control functions ************************************************/ 1031 /** @addtogroup HAL_SDMMC_LL_Group3 1032 * @{ 1033 */ 1034 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1035 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1036 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1037 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1038 1039 /* Command path state machine (CPSM) management functions */ 1040 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1041 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1042 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1043 1044 /* Data path state machine (DPSM) management functions */ 1045 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); 1046 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1047 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1048 1049 /* SDMMC Cards mode management functions */ 1050 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1051 /** 1052 * @} 1053 */ 1054 1055 /* SDMMC Commands management functions ******************************************/ 1056 /** @addtogroup HAL_SDMMC_LL_Group4 1057 * @{ 1058 */ 1059 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1060 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1061 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1062 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1063 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1064 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1065 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1066 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1067 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1068 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1069 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1070 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); 1071 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1072 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1073 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1074 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1075 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1076 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1077 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1078 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1079 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1080 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1081 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1082 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1083 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1084 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1085 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1086 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1087 /** 1088 * @} 1089 */ 1090 1091 /* SDMMC Responses management functions *****************************************/ 1092 /** @addtogroup HAL_SDMMC_LL_Group5 1093 * @{ 1094 */ 1095 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1096 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1097 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1098 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1099 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1100 /** 1101 * @} 1102 */ 1103 1104 /* Linked List functions *******************************************************/ 1105 /** @addtogroup HAL_SDMMC_LL_Group6 1106 * @{ 1107 */ 1108 uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf); 1109 uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, 1110 SDMMC_DMALinkNodeTypeDef *pNode); 1111 uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); 1112 uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode); 1113 uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode); 1114 uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); 1115 uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); 1116 /** 1117 * @} 1118 */ 1119 1120 /** 1121 * @} 1122 */ 1123 1124 /** 1125 * @} 1126 */ 1127 1128 /** 1129 * @} 1130 */ 1131 1132 /** 1133 * @} 1134 */ 1135 1136 /** 1137 * @} 1138 */ 1139 #ifdef __cplusplus 1140 } 1141 #endif 1142 1143 #endif /* STM32U5xx_LL_SDMMC_H */ 1144
