1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_LPTIM_H
21 #define STM32U5xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94 /** Legacy definitions for compatibility purpose
95 @cond 0
96 */
97 #define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
98 #define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
99 #define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
100 #define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
101 /**
102 @endcond
103 */
104
105 /* Private macros ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
108 * @{
109 */
110 /**
111 * @}
112 */
113 #endif /*USE_FULL_LL_DRIVER*/
114
115 /* Exported types ------------------------------------------------------------*/
116 #if defined(USE_FULL_LL_DRIVER)
117 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
118 * @{
119 */
120
121 /**
122 * @brief LPTIM Init structure definition
123 */
124 typedef struct
125 {
126 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
127 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
128
129 This feature can be modified afterwards using unitary
130 function @ref LL_LPTIM_SetClockSource().*/
131
132 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
133 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
134
135 This feature can be modified afterwards using using unitary
136 function @ref LL_LPTIM_SetPrescaler().*/
137
138 uint32_t Waveform; /*!< Specifies the waveform shape.
139 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
140
141 This feature can be modified afterwards using unitary
142 function @ref LL_LPTIM_SetWaveform().*/
143 } LL_LPTIM_InitTypeDef;
144
145 /**
146 * @}
147 */
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
152 * @{
153 */
154
155 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
157 * @{
158 */
159 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
160 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
161 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
162 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
163 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
164 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
165 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
166 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
167 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
168 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
169 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
170 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
171 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
172 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
173 /**
174 * @}
175 */
176
177 /** @defgroup LPTIM_LL_EC_IT IT Defines
178 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
179 * @{
180 */
181 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
182 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
183 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
184 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
185 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
186 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
187 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
188 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
189 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
190 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
191 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
192 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
193 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
194 /**
195 * @}
196 */
197
198 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
199 * @{
200 */
201 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
202 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
203 /**
204 * @}
205 */
206
207 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
208 * @{
209 */
210 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
211 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
212 /**
213 * @}
214 */
215
216 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
217 * @{
218 */
219 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
220 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
226 * @{
227 */
228 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
229 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
230 /**
231 * @}
232 */
233
234 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
235 * @{
236 */
237 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
238 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
239 /**
240 * @}
241 */
242
243 /** @defgroup TIM_LL_EC_CHANNEL Channel
244 * @{
245 */
246 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
247 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
248 /**
249 * @}
250 */
251
252 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
253 * @{
254 */
255 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
256 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
257 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
258 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
259 /**
260 * @}
261 */
262
263 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
264 * @{
265 */
266 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
267 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
268 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
269 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
270 /**
271 * @}
272 */
273
274 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
275 * @{
276 */
277 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
278 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
279 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
280 /**
281 * @}
282 */
283 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
284 * @{
285 */
286 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
287 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
288 /**
289 * @}
290 */
291
292 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
293 * @{
294 */
295 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
296 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
297 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
298 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
299 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
300 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
301 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
302 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
303 /**
304 * @}
305 */
306
307 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
308 * @{
309 */
310 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
311 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
312 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
313 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
314 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
315 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
316 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
317 #if defined(COMP2)
318 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
319 #endif /* COMP2 */
320 #define LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPDMA CH0 transfer complete */
321 #define LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to LPDMA CH1 transfer complete */
322 #define LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPDMA CH2 transfer complete */
323 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
324 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
325 /**
326 * @}
327 */
328
329 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
330 * @{
331 */
332 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
333 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
334 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
335 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
336 /**
337 * @}
338 */
339
340 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
341 * @{
342 */
343 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
344 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
345 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
346 /**
347 * @}
348 */
349
350 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
351 * @{
352 */
353 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
354 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
355 /**
356 * @}
357 */
358
359 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
360 * @{
361 */
362 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
363 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
364 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
365 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
366 /**
367 * @}
368 */
369
370 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
371 * @{
372 */
373 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
374 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
375 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
376 /**
377 * @}
378 */
379
380 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
381 * @{
382 */
383 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
384 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
385 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
386 /**
387 * @}
388 */
389
390 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
391 * @{
392 */
393 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
394 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
395 #if defined(COMP2)
396 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM1 and LPTIM2 */
397 #endif /* COMP2 */
398 /**
399 * @}
400 */
401
402 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
403 * @{
404 */
405 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
406 #if defined(COMP2)
407 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */
408 #endif /* COMP2 */
409 /**
410 * @}
411 */
412
413 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
414 * @{
415 */
416 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
417 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
418 #if defined(COMP2)
419 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
420 #endif /* COMP2 */
421 /**
422 * @}
423 */
424
425 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
426 * @{
427 */
428 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
429 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
430 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
431 /**
432 * @}
433 */
434
435 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
436 * @{
437 */
438 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
439 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
440 #if defined(COMP2)
441 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
442 #endif /* COMP2 */
443 /**
444 * @}
445 */
446
447 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
448 * @{
449 */
450 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
451 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI */
452 #define LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MSIS/1024 */
453 #define LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4 (LPTIM_CFGR2_IC2SEL_1|LPTIM_CFGR2_IC2SEL_0) /*!< IC2 connected to MSIS/4 */
454 /**
455 * @}
456 */
457
458 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
459 * @{
460 */
461 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
462 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
463 #if defined(COMP2)
464 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
465 #endif /* COMP2 */
466 /**
467 * @}
468 */
469
470
471 /**
472 * @}
473 */
474
475 /* Exported macro ------------------------------------------------------------*/
476 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
477 * @{
478 */
479
480 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
481 * @{
482 */
483
484 /**
485 * @brief Write a value in LPTIM register
486 * @param __INSTANCE__ LPTIM Instance
487 * @param __REG__ Register to be written
488 * @param __VALUE__ Value to be written in the register
489 * @retval None
490 */
491 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
492
493 /**
494 * @brief Read a value in LPTIM register
495 * @param __INSTANCE__ LPTIM Instance
496 * @param __REG__ Register to be read
497 * @retval Register value
498 */
499 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
500
501 /**
502 * @brief LPTimer Input Capture Get Offset(in counter step unit)
503 * @note The real capture value corresponding to the input capture trigger can be calculated using
504 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
505 * The Offset value is depending on the glitch filter value for the channel
506 * and the value of the prescaler for the kernel clock.
507 * Please check Errata Sheet V1_8 for more details under "variable latency
508 * on input capture channel" section.
509 * @param __PSC__ This parameter can be one of the following values:
510 * @arg @ref LL_LPTIM_PRESCALER_DIV1
511 * @arg @ref LL_LPTIM_PRESCALER_DIV2
512 * @arg @ref LL_LPTIM_PRESCALER_DIV4
513 * @arg @ref LL_LPTIM_PRESCALER_DIV8
514 * @arg @ref LL_LPTIM_PRESCALER_DIV16
515 * @arg @ref LL_LPTIM_PRESCALER_DIV32
516 * @arg @ref LL_LPTIM_PRESCALER_DIV64
517 * @arg @ref LL_LPTIM_PRESCALER_DIV128
518 * @param __FLT__ This parameter can be one of the following values:
519 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
520 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
521 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
522 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
523 * @retval offset value
524 */
525 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
526 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
527 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
528 /**
529 * @}
530 */
531
532 /**
533 * @}
534 */
535
536 /* Exported functions --------------------------------------------------------*/
537 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
538 * @{
539 */
540
541 /** Legacy definitions for compatibility purpose
542 @cond 0
543 */
544 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
545 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
546 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
547 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
548 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
549 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
550 /**
551 @endcond
552 */
553
554 #if defined(USE_FULL_LL_DRIVER)
555 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
556 * @{
557 */
558
559 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
560 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
561 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
562 /**
563 * @}
564 */
565 #endif /* USE_FULL_LL_DRIVER */
566
567 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
568 * @{
569 */
570
571 /**
572 * @brief Enable the LPTIM instance
573 * @note After setting the ENABLE bit, a delay of two counter clock is needed
574 * before the LPTIM instance is actually enabled.
575 * @rmtoll CR ENABLE LL_LPTIM_Enable
576 * @param LPTIMx Low-Power Timer instance
577 * @retval None
578 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)579 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
580 {
581 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
582 }
583
584 /**
585 * @brief Disable the LPTIM instance
586 * @rmtoll CR ENABLE LL_LPTIM_Disable
587 * @param LPTIMx Low-Power Timer instance
588 * @retval None
589 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)590 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
591 {
592 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
593 }
594
595 /**
596 * @brief Indicates whether the LPTIM instance is enabled.
597 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
598 * @param LPTIMx Low-Power Timer instance
599 * @retval State of bit (1 or 0).
600 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)601 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
602 {
603 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
604 }
605
606 /**
607 * @brief Starts the LPTIM counter in the desired mode.
608 * @note LPTIM instance must be enabled before starting the counter.
609 * @note It is possible to change on the fly from One Shot mode to
610 * Continuous mode.
611 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
612 * CR SNGSTRT LL_LPTIM_StartCounter
613 * @param LPTIMx Low-Power Timer instance
614 * @param OperatingMode This parameter can be one of the following values:
615 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
616 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
617 * @retval None
618 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)619 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
620 {
621 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
622 }
623
624 /**
625 * @brief Enable reset after read.
626 * @note After calling this function any read access to LPTIM_CNT
627 * register will asynchronously reset the LPTIM_CNT register content.
628 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
629 * @param LPTIMx Low-Power Timer instance
630 * @retval None
631 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)632 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
633 {
634 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
635 }
636
637 /**
638 * @brief Disable reset after read.
639 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
640 * @param LPTIMx Low-Power Timer instance
641 * @retval None
642 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)643 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
644 {
645 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
646 }
647
648 /**
649 * @brief Indicate whether the reset after read feature is enabled.
650 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
651 * @param LPTIMx Low-Power Timer instance
652 * @retval State of bit (1 or 0).
653 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)654 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
655 {
656 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
657 }
658
659 /**
660 * @brief Reset of the LPTIM_CNT counter register (synchronous).
661 * @note Due to the synchronous nature of this reset, it only takes
662 * place after a synchronization delay of 3 LPTIM core clock cycles
663 * (LPTIM core clock may be different from APB clock).
664 * @note COUNTRST is automatically cleared by hardware
665 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
666 * @param LPTIMx Low-Power Timer instance
667 * @retval None
668 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)669 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
670 {
671 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
672 }
673
674 /**
675 * @brief Set the LPTIM registers update mode (enable/disable register preload)
676 * @note This function must be called when the LPTIM instance is disabled.
677 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
678 * @param LPTIMx Low-Power Timer instance
679 * @param UpdateMode This parameter can be one of the following values:
680 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
681 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
682 * @retval None
683 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)684 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
685 {
686 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
687 }
688
689 /**
690 * @brief Get the LPTIM registers update mode
691 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
692 * @param LPTIMx Low-Power Timer instance
693 * @retval Returned value can be one of the following values:
694 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
695 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
696 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)697 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
698 {
699 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
700 }
701
702 /**
703 * @brief Set the auto reload value
704 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
705 * @note After a write to the LPTIMx_ARR register a new write operation to the
706 * same register can only be performed when the previous write operation
707 * is completed. Any successive write before the ARROK flag is set, will
708 * lead to unpredictable results.
709 * @note autoreload value be strictly greater than the compare value.
710 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
711 * @param LPTIMx Low-Power Timer instance
712 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
713 * @retval None
714 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)715 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
716 {
717 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
718 }
719
720 /**
721 * @brief Get actual auto reload value
722 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
723 * @param LPTIMx Low-Power Timer instance
724 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
725 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)726 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
727 {
728 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
729 }
730
731 /**
732 * @brief Set the repetition value
733 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
734 * @rmtoll RCR REP LL_LPTIM_SetRepetition
735 * @param LPTIMx Low-Power Timer instance
736 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
737 * @retval None
738 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)739 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
740 {
741 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
742 }
743
744 /**
745 * @brief Get the repetition value
746 * @rmtoll RCR REP LL_LPTIM_GetRepetition
747 * @param LPTIMx Low-Power Timer instance
748 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
749 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)750 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
751 {
752 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
753 }
754
755 /**
756 * @brief Enable capture/compare channel.
757 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
758 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
759 * @param LPTIMx LPTimer instance
760 * @param Channel This parameter can be one of the following values:
761 * @arg @ref LL_LPTIM_CHANNEL_CH1
762 * @arg @ref LL_LPTIM_CHANNEL_CH2
763 * @retval None
764 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)765 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
766 {
767 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
768 }
769
770 /**
771 * @brief Disable capture/compare channel.
772 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
773 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
774 * @param LPTIMx LPTimer instance
775 * @param Channel This parameter can be one of the following values:
776 * @arg @ref LL_LPTIM_CHANNEL_CH1
777 * @arg @ref LL_LPTIM_CHANNEL_CH2
778 * @retval None
779 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)780 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
781 {
782 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
783 }
784
785 /**
786 * @brief Indicate whether channel is enabled.
787 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
788 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
789 * @param LPTIMx LPTimer instance
790 * @param Channel This parameter can be one of the following values:
791 * @arg @ref LL_LPTIM_CHANNEL_CH1
792 * @arg @ref LL_LPTIM_CHANNEL_CH2
793 * @retval State of bit (1 or 0).
794 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)795 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
796 {
797 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
798 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
799
800 }
801
802 /**
803 * @brief Set the compare value
804 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
805 * same register can only be performed when the previous write operation
806 * is completed. Any successive write before the CMP1OK flag is set, will
807 * lead to unpredictable results.
808 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
809 * @param LPTIMx Low-Power Timer instance
810 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
811 * @retval None
812 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)813 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
814 {
815 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
816 }
817
818 /**
819 * @brief Get actual compare value
820 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
821 * @param LPTIMx Low-Power Timer instance
822 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
823 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)824 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
825 {
826 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
827 }
828
829 /**
830 * @brief Set the compare value
831 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
832 * same register can only be performed when the previous write operation
833 * is completed. Any successive write before the CMP2OK flag is set, will
834 * lead to unpredictable results.
835 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
836 * @param LPTIMx Low-Power Timer instance
837 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
838 * @retval None
839 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)840 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
841 {
842 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
843 }
844
845 /**
846 * @brief Get actual compare value
847 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
848 * @param LPTIMx Low-Power Timer instance
849 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
850 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)851 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
852 {
853 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
854 }
855
856 /**
857 * @brief Get actual counter value
858 * @note When the LPTIM instance is running with an asynchronous clock, reading
859 * the LPTIMx_CNT register may return unreliable values. So in this case
860 * it is necessary to perform two consecutive read accesses and verify
861 * that the two returned values are identical.
862 * @rmtoll CNT CNT LL_LPTIM_GetCounter
863 * @param LPTIMx Low-Power Timer instance
864 * @retval Counter value
865 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)866 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
867 {
868 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
869 }
870
871 /**
872 * @brief Set the counter mode (selection of the LPTIM counter clock source).
873 * @note The counter mode can be set only when the LPTIM instance is disabled.
874 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
875 * @param LPTIMx Low-Power Timer instance
876 * @param CounterMode This parameter can be one of the following values:
877 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
878 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
879 * @retval None
880 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)881 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
882 {
883 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
884 }
885
886 /**
887 * @brief Get the counter mode
888 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
889 * @param LPTIMx Low-Power Timer instance
890 * @retval Returned value can be one of the following values:
891 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
892 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
893 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)894 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
895 {
896 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
897 }
898
899 /**
900 * @brief Set waveform shape
901 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
902 * @param LPTIMx Low-Power Timer instance
903 * @param Waveform This parameter can be one of the following values:
904 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
905 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
906 * @retval None
907 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)908 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
909 {
910 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
911 }
912
913 /**
914 * @brief Get actual waveform shape
915 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
916 * @param LPTIMx Low-Power Timer instance
917 * @retval Returned value can be one of the following values:
918 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
919 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
920 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)921 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
922 {
923 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
924 }
925
926 /**
927 * @brief Set the polarity of an output channel.
928 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
929 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
930 * @param LPTIMx Low-Power Timer instance
931 * @param Channel This parameter can be one of the following values:
932 * @arg @ref LL_LPTIM_CHANNEL_CH1
933 * @arg @ref LL_LPTIM_CHANNEL_CH2
934 * @param Polarity This parameter can be one of the following values:
935 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
936 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
937 * @retval None
938 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)939 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
940 {
941 if (LPTIMx == LPTIM4)
942 {
943 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
944 }
945 else
946 {
947 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
948 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
949 }
950 }
951
952 /**
953 * @brief Get the polarity of an output channel.
954 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
955 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
956 * @param LPTIMx Low-Power Timer instance
957 * @param Channel This parameter can be one of the following values:
958 * @arg @ref LL_LPTIM_CHANNEL_CH1
959 * @arg @ref LL_LPTIM_CHANNEL_CH2
960 * @retval Returned value can be one of the following values:
961 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
962 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
963 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)964 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
965 {
966 if (LPTIMx == LPTIM4)
967 {
968 return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
969 }
970 else
971 {
972 return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
973 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
974 }
975 }
976
977 /**
978 * @brief Set actual prescaler division ratio.
979 * @note This function must be called when the LPTIM instance is disabled.
980 * @note When the LPTIM is configured to be clocked by an internal clock source
981 * and the LPTIM counter is configured to be updated by active edges
982 * detected on the LPTIM external Input1, the internal clock provided to
983 * the LPTIM must be not be prescaled.
984 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
985 * @param LPTIMx Low-Power Timer instance
986 * @param Prescaler This parameter can be one of the following values:
987 * @arg @ref LL_LPTIM_PRESCALER_DIV1
988 * @arg @ref LL_LPTIM_PRESCALER_DIV2
989 * @arg @ref LL_LPTIM_PRESCALER_DIV4
990 * @arg @ref LL_LPTIM_PRESCALER_DIV8
991 * @arg @ref LL_LPTIM_PRESCALER_DIV16
992 * @arg @ref LL_LPTIM_PRESCALER_DIV32
993 * @arg @ref LL_LPTIM_PRESCALER_DIV64
994 * @arg @ref LL_LPTIM_PRESCALER_DIV128
995 * @retval None
996 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)997 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
998 {
999 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
1000 }
1001
1002 /**
1003 * @brief Get actual prescaler division ratio.
1004 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
1005 * @param LPTIMx Low-Power Timer instance
1006 * @retval Returned value can be one of the following values:
1007 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1008 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1009 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1010 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1011 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1012 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1013 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1014 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1015 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)1016 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
1017 {
1018 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
1019 }
1020
1021 /**
1022 * @brief Set LPTIM input 1 source (default GPIO).
1023 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1024 * @param LPTIMx Low-Power Timer instance
1025 * @param Src This parameter can be one of the following values:
1026 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1027 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
1028 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 (*)
1029 * (*) Value not defined for all devices
1030 * @retval None
1031 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1032 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1033 {
1034 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1035 }
1036
1037 /**
1038 * @brief Set LPTIM input 2 source (default GPIO).
1039 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1040 * @param LPTIMx Low-Power Timer instance
1041 * @param Src This parameter can be one of the following values:
1042 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1043 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2 (*)
1044 * (*) Value not defined for all devices
1045 * @retval None
1046 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1047 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1048 {
1049 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1050 }
1051
1052 /**
1053 * @brief Set LPTIM input source (default GPIO).
1054 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1055 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1056 * @param LPTIMx Low-Power Timer instance
1057 * @param Src This parameter can be one of the following values:
1058 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1059 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1
1060 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2 (*)
1061 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1062 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
1063 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
1064 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1065 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1
1066 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 (*)
1067 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1068 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI
1069 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024
1070 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4
1071 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO
1072 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1
1073 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2 (*)
1074 *
1075 * (*) Value not defined in all devices. \n
1076 *
1077 * @retval None
1078 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1079 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1080 {
1081 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1082 }
1083
1084 /**
1085 * @brief Set the polarity of IC channel 1.
1086 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1087 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1088 * @param LPTIMx Low-Power Timer instance
1089 * @param Channel This parameter can be one of the following values:
1090 * @arg @ref LL_LPTIM_CHANNEL_CH1
1091 * @arg @ref LL_LPTIM_CHANNEL_CH2
1092 * @param Polarity This parameter can be one of the following values:
1093 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1094 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1095 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1096 * @retval None
1097 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1098 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1099 {
1100 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1101 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1102 }
1103
1104 /**
1105 * @brief Get the polarity of IC channels.
1106 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1107 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1108 * @param LPTIMx Low-Power Timer instance
1109 * @param Channel This parameter can be one of the following values:
1110 * @arg @ref LL_LPTIM_CHANNEL_CH1
1111 * @arg @ref LL_LPTIM_CHANNEL_CH2
1112 * @retval Returned value can be one of the following values:
1113 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1114 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1115 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1116 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1117 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1118 {
1119 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1120 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1121
1122 }
1123
1124 /**
1125 * @brief Set the filter of IC channels.
1126 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1127 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1128 * @param LPTIMx Low-Power Timer instance
1129 * @param Channel This parameter can be one of the following values:
1130 * @arg @ref LL_LPTIM_CHANNEL_CH1
1131 * @arg @ref LL_LPTIM_CHANNEL_CH2
1132 * @param Filter This parameter can be one of the following values:
1133 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1134 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1135 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1136 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1137 * @retval None
1138 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1139 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1140 {
1141 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1142 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1143 }
1144
1145 /**
1146 * @brief Get the filter of IC channels.
1147 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1148 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1149 * @param LPTIMx Low-Power Timer instance
1150 * @param Channel This parameter can be one of the following values:
1151 * @arg @ref LL_LPTIM_CHANNEL_CH1
1152 * @arg @ref LL_LPTIM_CHANNEL_CH2
1153 * @retval Returned value can be one of the following values:
1154 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1155 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1156 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1157 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1158 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1159 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1160 {
1161 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1162 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1163 }
1164
1165 /**
1166 * @brief Set the prescaler of IC channels.
1167 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1168 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1169 * @param LPTIMx Low-Power Timer instance
1170 * @param Channel This parameter can be one of the following values:
1171 * @arg @ref LL_LPTIM_CHANNEL_CH1
1172 * @arg @ref LL_LPTIM_CHANNEL_CH2
1173 * @param Prescaler This parameter can be one of the following values:
1174 * @arg @ref LL_LPTIM_ICPSC_DIV1
1175 * @arg @ref LL_LPTIM_ICPSC_DIV2
1176 * @arg @ref LL_LPTIM_ICPSC_DIV4
1177 * @arg @ref LL_LPTIM_ICPSC_DIV8
1178 * @retval None
1179 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1180 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1181 {
1182 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1183 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1184 }
1185
1186 /**
1187 * @brief Get the prescaler of IC channels.
1188 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1189 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1190 * @param LPTIMx Low-Power Timer instance
1191 * @param Channel This parameter can be one of the following values:
1192 * @arg @ref LL_LPTIM_CHANNEL_CH1
1193 * @arg @ref LL_LPTIM_CHANNEL_CH2
1194 * @retval Returned value can be one of the following values:
1195 * @arg @ref LL_LPTIM_ICPSC_DIV1
1196 * @arg @ref LL_LPTIM_ICPSC_DIV2
1197 * @arg @ref LL_LPTIM_ICPSC_DIV4
1198 * @arg @ref LL_LPTIM_ICPSC_DIV8
1199 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1200 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1201 {
1202 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1203 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1204 }
1205
1206 /**
1207 * @brief Set the Channel Mode.
1208 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1209 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1210 * @param LPTIMx Low-Power Timer instance
1211 * @param Channel This parameter can be one of the following values:
1212 * @arg @ref LL_LPTIM_CHANNEL_CH1
1213 * @arg @ref LL_LPTIM_CHANNEL_CH2
1214 * @param CCMode This parameter can be one of the following values:
1215 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1216 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1217 * @retval None
1218 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1219 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1220 {
1221 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1222 }
1223
1224 /**
1225 * @brief Get the Channel Mode.
1226 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1227 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1228 * @param LPTIMx Low-Power Timer instance
1229 * @param Channel This parameter can be one of the following values:
1230 * @arg @ref LL_LPTIM_CHANNEL_CH1
1231 * @arg @ref LL_LPTIM_CHANNEL_CH2
1232 * @retval Returned value can be one of the following values:
1233 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1234 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1235 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1236 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1237 {
1238 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1239 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1240 }
1241
1242 /**
1243 * @brief Get captured value for input channel 1.
1244 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1245 * @note The real capture value corresponding to the input capture trigger can be calculated using
1246 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1247 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1248 * @param LPTIMx Low-Power Timer instance
1249 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1250 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1251 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1252 {
1253 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1254 }
1255
1256 /**
1257 * @brief Get captured value for input channel 2.
1258 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1259 * @note The real capture value corresponding to the input capture trigger can be calculated using
1260 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1261 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1262 * @param LPTIMx Low-Power Timer instance
1263 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1264 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1265 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1266 {
1267 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1268 }
1269
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1275 * @{
1276 */
1277
1278 /**
1279 * @brief Enable the timeout function
1280 * @note This function must be called when the LPTIM instance is disabled.
1281 * @note The first trigger event will start the timer, any successive trigger
1282 * event will reset the counter and the timer will restart.
1283 * @note The timeout value corresponds to the compare value; if no trigger
1284 * occurs within the expected time frame, the MCU is waked-up by the
1285 * compare match event.
1286 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1287 * @param LPTIMx Low-Power Timer instance
1288 * @retval None
1289 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1290 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1291 {
1292 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1293 }
1294
1295 /**
1296 * @brief Disable the timeout function
1297 * @note This function must be called when the LPTIM instance is disabled.
1298 * @note A trigger event arriving when the timer is already started will be
1299 * ignored.
1300 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1301 * @param LPTIMx Low-Power Timer instance
1302 * @retval None
1303 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1304 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1305 {
1306 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1307 }
1308
1309 /**
1310 * @brief Indicate whether the timeout function is enabled.
1311 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1312 * @param LPTIMx Low-Power Timer instance
1313 * @retval State of bit (1 or 0).
1314 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1315 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1316 {
1317 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1318 }
1319
1320 /**
1321 * @brief Start the LPTIM counter
1322 * @note This function must be called when the LPTIM instance is disabled.
1323 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1324 * @param LPTIMx Low-Power Timer instance
1325 * @retval None
1326 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1327 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1328 {
1329 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1330 }
1331
1332 /**
1333 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1334 * @note This function must be called when the LPTIM instance is disabled.
1335 * @note An internal clock source must be present when a digital filter is
1336 * required for the trigger.
1337 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1338 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1339 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1340 * @param LPTIMx Low-Power Timer instance
1341 * @param Source This parameter can be one of the following values:
1342 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1343 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1344 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1345 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1346 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1347 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1348 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
1349 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1350 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
1351 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
1352 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
1353 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
1354 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
1355 *
1356 * (*) Value not defined in all devices. \n
1357 *
1358 * @param Filter This parameter can be one of the following values:
1359 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1360 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1361 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1362 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1363 * @param Polarity This parameter can be one of the following values:
1364 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1365 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1366 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1367 * @retval None
1368 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1369 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1370 {
1371 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1372 }
1373
1374 /**
1375 * @brief Get actual external trigger source.
1376 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1377 * @param LPTIMx Low-Power Timer instance
1378 * @retval Returned value can be one of the following values:
1379 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1380 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1381 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1382 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1383 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1384 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1385 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
1386 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1387 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
1388 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
1389 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
1390 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
1391 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
1392 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1393 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1394 {
1395 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1396 }
1397
1398 /**
1399 * @brief Get actual external trigger filter.
1400 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1401 * @param LPTIMx Low-Power Timer instance
1402 * @retval Returned value can be one of the following values:
1403 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1404 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1405 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1406 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1407 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1408 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1409 {
1410 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1411 }
1412
1413 /**
1414 * @brief Get actual external trigger polarity.
1415 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1416 * @param LPTIMx Low-Power Timer instance
1417 * @retval Returned value can be one of the following values:
1418 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1419 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1420 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1421 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1422 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1423 {
1424 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1425 }
1426
1427 /**
1428 * @}
1429 */
1430
1431 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1432 * @{
1433 */
1434
1435 /**
1436 * @brief Set the source of the clock used by the LPTIM instance.
1437 * @note This function must be called when the LPTIM instance is disabled.
1438 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1439 * @param LPTIMx Low-Power Timer instance
1440 * @param ClockSource This parameter can be one of the following values:
1441 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1442 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1443 * @retval None
1444 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1445 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1446 {
1447 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1448 }
1449
1450 /**
1451 * @brief Get actual LPTIM instance clock source.
1452 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1453 * @param LPTIMx Low-Power Timer instance
1454 * @retval Returned value can be one of the following values:
1455 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1456 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1457 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1458 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1459 {
1460 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1461 }
1462
1463 /**
1464 * @brief Configure the active edge or edges used by the counter when
1465 the LPTIM is clocked by an external clock source.
1466 * @note This function must be called when the LPTIM instance is disabled.
1467 * @note When both external clock signal edges are considered active ones,
1468 * the LPTIM must also be clocked by an internal clock source with a
1469 * frequency equal to at least four times the external clock frequency.
1470 * @note An internal clock source must be present when a digital filter is
1471 * required for external clock.
1472 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1473 * CFGR CKPOL LL_LPTIM_ConfigClock
1474 * @param LPTIMx Low-Power Timer instance
1475 * @param ClockFilter This parameter can be one of the following values:
1476 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1477 * @arg @ref LL_LPTIM_CLK_FILTER_2
1478 * @arg @ref LL_LPTIM_CLK_FILTER_4
1479 * @arg @ref LL_LPTIM_CLK_FILTER_8
1480 * @param ClockPolarity This parameter can be one of the following values:
1481 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1482 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1483 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1484 * @retval None
1485 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1486 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1487 {
1488 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1489 }
1490
1491 /**
1492 * @brief Get actual clock polarity
1493 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1494 * @param LPTIMx Low-Power Timer instance
1495 * @retval Returned value can be one of the following values:
1496 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1497 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1498 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1499 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1500 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1501 {
1502 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1503 }
1504
1505 /**
1506 * @brief Get actual clock digital filter
1507 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1508 * @param LPTIMx Low-Power Timer instance
1509 * @retval Returned value can be one of the following values:
1510 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1511 * @arg @ref LL_LPTIM_CLK_FILTER_2
1512 * @arg @ref LL_LPTIM_CLK_FILTER_4
1513 * @arg @ref LL_LPTIM_CLK_FILTER_8
1514 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1515 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1516 {
1517 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1518 }
1519
1520 /**
1521 * @}
1522 */
1523
1524 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1525 * @{
1526 */
1527
1528 /**
1529 * @brief Configure the encoder mode.
1530 * @note This function must be called when the LPTIM instance is disabled.
1531 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1532 * @param LPTIMx Low-Power Timer instance
1533 * @param EncoderMode This parameter can be one of the following values:
1534 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1535 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1536 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1537 * @retval None
1538 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1539 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1540 {
1541 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1542 }
1543
1544 /**
1545 * @brief Get actual encoder mode.
1546 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1547 * @param LPTIMx Low-Power Timer instance
1548 * @retval Returned value can be one of the following values:
1549 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1550 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1551 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1552 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1553 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1554 {
1555 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1556 }
1557
1558 /**
1559 * @brief Enable the encoder mode
1560 * @note This function must be called when the LPTIM instance is disabled.
1561 * @note In this mode the LPTIM instance must be clocked by an internal clock
1562 * source. Also, the prescaler division ratio must be equal to 1.
1563 * @note LPTIM instance must be configured in continuous mode prior enabling
1564 * the encoder mode.
1565 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1566 * @param LPTIMx Low-Power Timer instance
1567 * @retval None
1568 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1569 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1570 {
1571 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1572 }
1573
1574 /**
1575 * @brief Disable the encoder mode
1576 * @note This function must be called when the LPTIM instance is disabled.
1577 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1578 * @param LPTIMx Low-Power Timer instance
1579 * @retval None
1580 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1581 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1582 {
1583 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1584 }
1585
1586 /**
1587 * @brief Indicates whether the LPTIM operates in encoder mode.
1588 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1589 * @param LPTIMx Low-Power Timer instance
1590 * @retval State of bit (1 or 0).
1591 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1592 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1593 {
1594 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1595 }
1596
1597 /**
1598 * @}
1599 */
1600
1601 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1602 * @{
1603 */
1604
1605 /**
1606 * @brief Clear the compare match flag for channel 1 (CC1CF)
1607 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1608 * @param LPTIMx Low-Power Timer instance
1609 * @retval None
1610 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1611 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1612 {
1613 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1614 }
1615
1616 /**
1617 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1618 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1619 * @param LPTIMx Low-Power Timer instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1622 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1623 {
1624 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1625 }
1626
1627 /**
1628 * @brief Clear the compare match flag for channel 2 (CC2CF)
1629 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1630 * @param LPTIMx Low-Power Timer instance
1631 * @retval None
1632 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1633 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1634 {
1635 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1636 }
1637
1638 /**
1639 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1640 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1641 * @param LPTIMx Low-Power Timer instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1644 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1645 {
1646 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1647 }
1648
1649 /**
1650 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1651 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1652 * @param LPTIMx Low-Power Timer instance
1653 * @retval None
1654 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1655 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1656 {
1657 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1658 }
1659
1660 /**
1661 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1662 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1663 * @param LPTIMx Low-Power Timer instance
1664 * @retval State of bit (1 or 0).
1665 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1666 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1667 {
1668 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1669 }
1670
1671 /**
1672 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1673 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1674 * @param LPTIMx Low-Power Timer instance
1675 * @retval None
1676 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1677 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1678 {
1679 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1680 }
1681
1682 /**
1683 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1684 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1685 * @param LPTIMx Low-Power Timer instance
1686 * @retval State of bit (1 or 0).
1687 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1688 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1689 {
1690 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1691 }
1692
1693 /**
1694 * @brief Clear the autoreload match flag (ARRMCF)
1695 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1696 * @param LPTIMx Low-Power Timer instance
1697 * @retval None
1698 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1699 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1700 {
1701 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1702 }
1703
1704 /**
1705 * @brief Inform application whether a autoreload match interrupt has occurred.
1706 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1707 * @param LPTIMx Low-Power Timer instance
1708 * @retval State of bit (1 or 0).
1709 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1710 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1711 {
1712 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1713 }
1714
1715 /**
1716 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1717 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1718 * @param LPTIMx Low-Power Timer instance
1719 * @retval None
1720 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1721 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1722 {
1723 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1724 }
1725
1726 /**
1727 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1728 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1729 * @param LPTIMx Low-Power Timer instance
1730 * @retval State of bit (1 or 0).
1731 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1732 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1733 {
1734 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1735 }
1736
1737 /**
1738 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1739 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1740 * @param LPTIMx Low-Power Timer instance
1741 * @retval None
1742 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1743 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1744 {
1745 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1746 }
1747
1748 /**
1749 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1750 completed. If so, a new one can be initiated.
1751 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1752 * @param LPTIMx Low-Power Timer instance
1753 * @retval State of bit (1 or 0).
1754 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1755 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1756 {
1757 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1758 }
1759
1760 /**
1761 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1762 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1763 * @param LPTIMx Low-Power Timer instance
1764 * @retval None
1765 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1766 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1767 {
1768 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1769 }
1770
1771 /**
1772 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1773 completed. If so, a new one can be initiated.
1774 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1775 * @param LPTIMx Low-Power Timer instance
1776 * @retval State of bit (1 or 0).
1777 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1778 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1779 {
1780 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1781 }
1782
1783 /**
1784 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1785 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1786 * @param LPTIMx Low-Power Timer instance
1787 * @retval None
1788 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1789 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1790 {
1791 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1792 }
1793
1794 /**
1795 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1796 completed. If so, a new one can be initiated.
1797 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1798 * @param LPTIMx Low-Power Timer instance
1799 * @retval State of bit (1 or 0).
1800 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1801 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1802 {
1803 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1804 }
1805
1806 /**
1807 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1808 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1809 * @param LPTIMx Low-Power Timer instance
1810 * @retval None
1811 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1812 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1813 {
1814 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1815 }
1816
1817 /**
1818 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1819 completed. If so, a new one can be initiated.
1820 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1821 * @param LPTIMx Low-Power Timer instance
1822 * @retval State of bit (1 or 0).
1823 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1824 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1825 {
1826 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1827 }
1828
1829 /**
1830 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1831 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1832 * @param LPTIMx Low-Power Timer instance
1833 * @retval None
1834 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1835 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1836 {
1837 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1838 }
1839
1840 /**
1841 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1842 operates in encoder mode).
1843 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1844 * @param LPTIMx Low-Power Timer instance
1845 * @retval State of bit (1 or 0).
1846 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1847 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1848 {
1849 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1850 }
1851
1852 /**
1853 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1854 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1855 * @param LPTIMx Low-Power Timer instance
1856 * @retval None
1857 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1858 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1859 {
1860 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1861 }
1862
1863 /**
1864 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1865 operates in encoder mode).
1866 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1867 * @param LPTIMx Low-Power Timer instance
1868 * @retval State of bit (1 or 0).
1869 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1870 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1871 {
1872 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1873 }
1874
1875 /**
1876 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1877 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1878 * @param LPTIMx Low-Power Timer instance
1879 * @retval None
1880 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1881 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1882 {
1883 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1884 }
1885
1886 /**
1887 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1888 completed; If so, a new one can be initiated.
1889 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1890 * @param LPTIMx Low-Power Timer instance
1891 * @retval State of bit (1 or 0).
1892 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1893 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1894 {
1895 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1896 }
1897
1898 /**
1899 * @brief Clear the update event flag (UECF).
1900 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1901 * @param LPTIMx Low-Power Timer instance
1902 * @retval None
1903 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1904 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1905 {
1906 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1907 }
1908
1909 /**
1910 * @brief Informs application whether the LPTIMx update event has occurred.
1911 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1912 * @param LPTIMx Low-Power Timer instance
1913 * @retval State of bit (1 or 0).
1914 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1915 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1916 {
1917 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1918 }
1919
1920 /**
1921 * @}
1922 */
1923
1924 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1925 * @{
1926 */
1927 /**
1928 * @brief Enable capture/compare 1 interrupt (CC1IE).
1929 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1930 * @param LPTIMx Low-Power Timer instance
1931 * @retval None
1932 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1933 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1934 {
1935 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1936 }
1937
1938 /**
1939 * @brief Disable capture/compare 1 interrupt (CC1IE).
1940 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1941 * @param LPTIMx Low-Power Timer instance
1942 * @retval None
1943 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1944 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1945 {
1946 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1947 }
1948
1949 /**
1950 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1951 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1952 * @param LPTIMx Low-Power Timer instance
1953 * @retval State of bit (1 or 0).
1954 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1955 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1956 {
1957 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1958 }
1959
1960 /**
1961 * @brief Enable capture/compare 1 interrupt (CC2IE).
1962 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
1963 * @param LPTIMx Low-Power Timer instance
1964 * @retval None
1965 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)1966 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
1967 {
1968 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1969 }
1970
1971 /**
1972 * @brief Disable capture/compare 2 interrupt (CC2IE).
1973 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
1974 * @param LPTIMx Low-Power Timer instance
1975 * @retval None
1976 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)1977 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
1978 {
1979 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1980 }
1981
1982 /**
1983 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
1984 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
1985 * @param LPTIMx Low-Power Timer instance
1986 * @retval State of bit (1 or 0).
1987 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)1988 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
1989 {
1990 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
1991 }
1992
1993 /**
1994 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
1995 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
1996 * @param LPTIMx Low-Power Timer instance
1997 * @retval None
1998 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)1999 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2000 {
2001 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2002 }
2003
2004 /**
2005 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
2006 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
2007 * @param LPTIMx Low-Power Timer instance
2008 * @retval None
2009 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)2010 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2011 {
2012 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2013 }
2014
2015 /**
2016 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
2017 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
2018 * @param LPTIMx Low-Power Timer instance
2019 * @retval State of bit (1 or 0).
2020 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)2021 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
2022 {
2023 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
2024 }
2025
2026 /**
2027 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
2028 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
2029 * @param LPTIMx Low-Power Timer instance
2030 * @retval None
2031 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)2032 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2033 {
2034 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2035 }
2036
2037 /**
2038 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2039 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2040 * @param LPTIMx Low-Power Timer instance
2041 * @retval None
2042 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2043 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2044 {
2045 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2046 }
2047
2048 /**
2049 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2050 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2051 * @param LPTIMx Low-Power Timer instance
2052 * @retval State of bit (1 or 0).
2053 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2054 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2055 {
2056 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2057 }
2058
2059 /**
2060 * @brief Enable autoreload match interrupt (ARRMIE).
2061 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2062 * @param LPTIMx Low-Power Timer instance
2063 * @retval None
2064 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2065 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2066 {
2067 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2068 }
2069
2070 /**
2071 * @brief Disable autoreload match interrupt (ARRMIE).
2072 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2073 * @param LPTIMx Low-Power Timer instance
2074 * @retval None
2075 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2076 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2077 {
2078 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2079 }
2080
2081 /**
2082 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2083 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2084 * @param LPTIMx Low-Power Timer instance
2085 * @retval State of bit (1 or 0).
2086 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2087 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2088 {
2089 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2090 }
2091
2092 /**
2093 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2094 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2095 * @param LPTIMx Low-Power Timer instance
2096 * @retval None
2097 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2098 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2099 {
2100 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2101 }
2102
2103 /**
2104 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2105 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2106 * @param LPTIMx Low-Power Timer instance
2107 * @retval None
2108 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2109 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2110 {
2111 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2112 }
2113
2114 /**
2115 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2116 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2117 * @param LPTIMx Low-Power Timer instance
2118 * @retval State of bit (1 or 0).
2119 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2120 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2121 {
2122 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2123 }
2124
2125 /**
2126 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2127 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2128 * @param LPTIMx Low-Power Timer instance
2129 * @retval None
2130 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2131 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2132 {
2133 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2134 }
2135
2136 /**
2137 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2138 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2139 * @param LPTIMx Low-Power Timer instance
2140 * @retval None
2141 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2142 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2143 {
2144 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2145 }
2146
2147 /**
2148 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2149 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2150 * @param LPTIMx Low-Power Timer instance
2151 * @retval State of bit (1 or 0).
2152 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2153 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2154 {
2155 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2156 }
2157
2158 /**
2159 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2160 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2161 * @param LPTIMx Low-Power Timer instance
2162 * @retval None
2163 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2164 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2165 {
2166 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2167 }
2168
2169 /**
2170 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2171 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2172 * @param LPTIMx Low-Power Timer instance
2173 * @retval None
2174 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2175 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2176 {
2177 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2178 }
2179
2180 /**
2181 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2182 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2183 * @param LPTIMx Low-Power Timer instance
2184 * @retval State of bit (1 or 0).
2185 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2186 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2187 {
2188 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2189 }
2190
2191 /**
2192 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2193 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2194 * @param LPTIMx Low-Power Timer instance
2195 * @retval None
2196 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2197 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2198 {
2199 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2200 }
2201
2202 /**
2203 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2204 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2205 * @param LPTIMx Low-Power Timer instance
2206 * @retval None
2207 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2208 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2209 {
2210 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2211 }
2212
2213 /**
2214 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2215 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2216 * @param LPTIMx Low-Power Timer instance
2217 * @retval State of bit(1 or 0).
2218 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2219 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2220 {
2221 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2222 }
2223
2224 /**
2225 * @brief Enable direction change to up interrupt (UPIE).
2226 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2227 * @param LPTIMx Low-Power Timer instance
2228 * @retval None
2229 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2230 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2231 {
2232 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2233 }
2234
2235 /**
2236 * @brief Disable direction change to up interrupt (UPIE).
2237 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2238 * @param LPTIMx Low-Power Timer instance
2239 * @retval None
2240 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2241 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2242 {
2243 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2244 }
2245
2246 /**
2247 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2248 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2249 * @param LPTIMx Low-Power Timer instance
2250 * @retval State of bit(1 or 0).
2251 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2252 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2253 {
2254 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2255 }
2256
2257 /**
2258 * @brief Enable direction change to down interrupt (DOWNIE).
2259 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2260 * @param LPTIMx Low-Power Timer instance
2261 * @retval None
2262 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2263 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2264 {
2265 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2266 }
2267
2268 /**
2269 * @brief Disable direction change to down interrupt (DOWNIE).
2270 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2271 * @param LPTIMx Low-Power Timer instance
2272 * @retval None
2273 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2274 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2275 {
2276 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2277 }
2278
2279 /**
2280 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2281 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2282 * @param LPTIMx Low-Power Timer instance
2283 * @retval State of bit(1 or 0).
2284 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2285 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2286 {
2287 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2288 }
2289
2290 /**
2291 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2292 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2293 * @param LPTIMx Low-Power Timer instance
2294 * @retval None
2295 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2296 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2297 {
2298 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2299 }
2300
2301 /**
2302 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2303 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2304 * @param LPTIMx Low-Power Timer instance
2305 * @retval None
2306 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2307 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2308 {
2309 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2310 }
2311
2312 /**
2313 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2314 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2315 * @param LPTIMx Low-Power Timer instance
2316 * @retval State of bit(1 or 0).
2317 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2318 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2319 {
2320 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2321 }
2322
2323 /**
2324 * @brief Enable update event interrupt (UEIE).
2325 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2326 * @param LPTIMx Low-Power Timer instance
2327 * @retval None
2328 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2329 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2330 {
2331 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2332 }
2333
2334 /**
2335 * @brief Disable update event interrupt (UEIE).
2336 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2337 * @param LPTIMx Low-Power Timer instance
2338 * @retval None
2339 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2340 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2341 {
2342 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2343 }
2344
2345 /**
2346 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2347 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2348 * @param LPTIMx Low-Power Timer instance
2349 *@ retval State of bit(1 or 0).
2350 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2351 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2352 {
2353 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2354 }
2355 /**
2356 * @}
2357 */
2358
2359
2360 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2361 * @{
2362 */
2363 /**
2364 * @brief Enable update DMA request.
2365 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2366 * @param LPTIMx Low-Power Timer instance
2367 * @retval None
2368 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2369 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2370 {
2371 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2372 }
2373
2374 /**
2375 * @brief Disable update DMA request.
2376 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2377 * @param LPTIMx Low-Power Timer instance
2378 * @retval None
2379 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2380 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2381 {
2382 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2383 }
2384
2385 /**
2386 * @brief Indicates whether the update DMA request is enabled.
2387 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2388 * @param LPTIMx Low-Power Timer instance
2389 * @retval State of bit (1 or 0).
2390 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2391 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2392 {
2393 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2394 }
2395
2396 /**
2397 * @brief Enable capture/compare 1 DMA request (CC1DE).
2398 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2399 * @param LPTIMx Low-Power Timer instance
2400 * @retval None
2401 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2402 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2403 {
2404 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2405 }
2406
2407 /**
2408 * @brief Disable capture/compare 1 DMA request (CC1DE).
2409 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2410 * @param LPTIMx Low-Power Timer instance
2411 * @retval None
2412 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2413 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2414 {
2415 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2416 }
2417
2418 /**
2419 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2420 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2421 * @param LPTIMx Low-Power Timer instance
2422 * @retval State of bit (1 or 0).
2423 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2424 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2425 {
2426 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2427 }
2428
2429 /**
2430 * @brief Enable capture/compare 2 DMA request (CC2DE).
2431 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2432 * @param LPTIMx Low-Power Timer instance
2433 * @retval None
2434 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2435 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2436 {
2437 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2438 }
2439
2440 /**
2441 * @brief Disable capture/compare 2 DMA request (CC2DE).
2442 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2443 * @param LPTIMx Low-Power Timer instance
2444 * @retval None
2445 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2446 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2447 {
2448 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2449 }
2450
2451 /**
2452 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2453 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2454 * @param LPTIMx Low-Power Timer instance
2455 * @retval State of bit (1 or 0).
2456 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2457 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2458 {
2459 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2460 }
2461
2462 /**
2463 * @}
2464 */
2465 /**
2466 * @}
2467 */
2468
2469 /**
2470 * @}
2471 */
2472
2473 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
2474
2475 /**
2476 * @}
2477 */
2478
2479 #ifdef __cplusplus
2480 }
2481 #endif
2482
2483 #endif /* STM32U5xx_LL_LPTIM_H */
2484
