1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with
25 HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or
26 @ref LL_Init1msTick_LSE with external source
27 (+) Low power mode configuration (SCB register of Cortex-MCU)
28 (+) API to access to MCU info (CPUID register)
29 (+) API to enable fault handler (SHCSR accesses)
30 (+) API to enable and disable the MPU secure and non-secure
31 (+) API to configure the region of MPU secure and non-secure
32 (+) API to configure the attributes region of MPU secure and non-secure
33
34 @endverbatim
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32U5xx_LL_CORTEX_H
39 #define STM32U5xx_LL_CORTEX_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32u5xx.h"
47
48 /** @addtogroup STM32U5xx_LL_Driver
49 * @{
50 */
51
52 /** @defgroup CORTEX_LL CORTEX
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
60 * @{
61 */
62 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
63 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
64 /**
65 * @}
66 */
67
68 /* Private macros ------------------------------------------------------------*/
69 /* Exported types ------------------------------------------------------------*/
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
72 * @{
73 */
74
75 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
76 * @{
77 */
78 #define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick
79 clock source */
80 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
81 clock source */
82 /** Legacy definitions for backward compatibility purpose
83 */
84 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL
85 /**
86 */
87 /**
88 * @}
89 */
90
91 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
92 * @{
93 */
94 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
95 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
96 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
97 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
98 /**
99 * @}
100 */
101
102 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
103 * @{
104 */
105 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
106 #define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
107 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
108 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
109 /**
110 * @}
111 */
112
113 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
114 * @{
115 */
116 /* Device memory attributes */
117 #define LL_MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */
118 #define LL_MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */
119 #define LL_MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */
120 #define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */
121
122 /* Normal memory attributes */
123 /* Non-cacheable memory attribute */
124 #define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */
125
126 /* Cacheable memory attributes: combination of cache write policy, transient and allocation */
127 /* - cache write policy */
128 #define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */
129 #define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */
130 /* - transient mode attribute */
131 #define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */
132 #define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */
133 /* - allocation attribute */
134 #define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */
135 #define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */
136 #define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */
137 #define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */
138 /**
139 * @}
140 */
141
142 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
143 * @{
144 */
145 #define LL_MPU_REGION_ENABLE 1U
146 #define LL_MPU_REGION_DISABLE 0U
147 /**
148 * @}
149 */
150
151 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
152 * @{
153 */
154 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */
155 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */
156 /**
157 * @}
158 */
159
160 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
161 * @{
162 */
163 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */
164 #define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */
165 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */
166 /**
167 * @}
168 */
169
170 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
171 * @{
172 */
173 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */
174 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */
175 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */
176 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */
177 /**
178 * @}
179 */
180
181 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
182 * @{
183 */
184 #define LL_MPU_REGION_NUMBER0 0U
185 #define LL_MPU_REGION_NUMBER1 1U
186 #define LL_MPU_REGION_NUMBER2 2U
187 #define LL_MPU_REGION_NUMBER3 3U
188 #define LL_MPU_REGION_NUMBER4 4U
189 #define LL_MPU_REGION_NUMBER5 5U
190 #define LL_MPU_REGION_NUMBER6 6U
191 #define LL_MPU_REGION_NUMBER7 7U
192 /**
193 * @}
194 */
195
196 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
197 * @{
198 */
199 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
200 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
201 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
202 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
203 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
204 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
205 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
206 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
207 /**
208 * @}
209 */
210
211 /**
212 * @}
213 */
214
215 /* Exported macro ------------------------------------------------------------*/
216
217 /* Exported functions --------------------------------------------------------*/
218 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
219 * @{
220 */
221
222 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
223 * @brief CORTEX SYSTICK LL module driver
224 * @{
225 */
226
227 /**
228 * @brief This function checks if the Systick counter flag is active or not.
229 * @note It can be used in timeout function on application side.
230 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
231 * @retval State of bit (1 or 0).
232 */
LL_SYSTICK_IsActiveCounterFlag(void)233 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
234 {
235 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
236 }
237
238 /**
239 * @brief Configures the SysTick clock source
240 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
241 * @param Source This parameter can be one of the following values:
242 * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL
243 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
244 * @retval None
245 */
LL_SYSTICK_SetClkSource(uint32_t Source)246 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
247 {
248 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
249 {
250 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
251 }
252 else
253 {
254 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
255 }
256 }
257
258 /**
259 * @brief Get the SysTick clock source
260 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
261 * @retval Returned value can be one of the following values:
262 * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL
263 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
264 */
LL_SYSTICK_GetClkSource(void)265 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
266 {
267 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
268 }
269
270 /**
271 * @brief Enable SysTick exception request
272 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
273 * @retval None
274 */
LL_SYSTICK_EnableIT(void)275 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
276 {
277 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
278 }
279
280 /**
281 * @brief Disable SysTick exception request
282 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
283 * @retval None
284 */
LL_SYSTICK_DisableIT(void)285 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
286 {
287 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
288 }
289
290 /**
291 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
292 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
293 * @retval State of bit (1 or 0).
294 */
LL_SYSTICK_IsEnabledIT(void)295 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
296 {
297 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
298 }
299
300 /**
301 * @}
302 */
303
304 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
305 * @{
306 */
307
308 /**
309 * @brief Processor uses sleep as its low power mode
310 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
311 * @retval None
312 */
LL_LPM_EnableSleep(void)313 __STATIC_INLINE void LL_LPM_EnableSleep(void)
314 {
315 /* Clear SLEEPDEEP bit of Cortex System Control Register */
316 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
317 }
318
319 /**
320 * @brief Processor uses deep sleep as its low power mode
321 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
322 * @retval None
323 */
LL_LPM_EnableDeepSleep(void)324 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
325 {
326 /* Set SLEEPDEEP bit of Cortex System Control Register */
327 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
328 }
329
330 /**
331 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
332 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
333 * empty main application.
334 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
335 * @retval None
336 */
LL_LPM_EnableSleepOnExit(void)337 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
338 {
339 /* Set SLEEPONEXIT bit of Cortex System Control Register */
340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
341 }
342
343 /**
344 * @brief Do not sleep when returning to Thread mode.
345 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
346 * @retval None
347 */
LL_LPM_DisableSleepOnExit(void)348 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
349 {
350 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
351 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
352 }
353
354 /**
355 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
356 * processor.
357 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
358 * @retval None
359 */
LL_LPM_EnableEventOnPend(void)360 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
361 {
362 /* Set SEVEONPEND bit of Cortex System Control Register */
363 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
364 }
365
366 /**
367 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
368 * excluded
369 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
370 * @retval None
371 */
LL_LPM_DisableEventOnPend(void)372 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
373 {
374 /* Clear SEVEONPEND bit of Cortex System Control Register */
375 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
376 }
377
378 /**
379 * @}
380 */
381
382 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
383 * @{
384 */
385
386 /**
387 * @brief Enable a fault in System handler control register (SHCSR)
388 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
389 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
390 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
391 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
392 * @param Fault This parameter can be a combination of the following values:
393 * @arg @ref LL_HANDLER_FAULT_USG
394 * @arg @ref LL_HANDLER_FAULT_BUS
395 * @arg @ref LL_HANDLER_FAULT_MEM
396 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
397 *
398 * (*) value applicable in secure when the system implements the security.
399 * @retval None
400 */
LL_HANDLER_EnableFault(uint32_t Fault)401 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
402 {
403 /* Enable the system handler fault */
404 SET_BIT(SCB->SHCSR, Fault);
405 }
406
407 /**
408 * @brief Disable a fault in System handler control register (SHCSR)
409 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
410 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
411 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
412 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
413 * @param Fault This parameter can be a combination of the following values:
414 * @arg @ref LL_HANDLER_FAULT_USG
415 * @arg @ref LL_HANDLER_FAULT_BUS
416 * @arg @ref LL_HANDLER_FAULT_MEM
417 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
418 *
419 * (*) value applicable in secure when the system implements the security.
420 * @retval None
421 */
LL_HANDLER_DisableFault(uint32_t Fault)422 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
423 {
424 /* Disable the system handler fault */
425 CLEAR_BIT(SCB->SHCSR, Fault);
426 }
427
428 /**
429 * @}
430 */
431
432 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
433 * @{
434 */
435
436 /**
437 * @brief Get Implementer code
438 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
439 * @retval Value should be equal to 0x41 for ARM
440 */
LL_CPUID_GetImplementer(void)441 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
442 {
443 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
444 }
445
446 /**
447 * @brief Get Variant number (The r value in the rnpn product revision identifier)
448 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
449 * @retval Value between 0 and 255 (0x0: revision 0)
450 */
LL_CPUID_GetVariant(void)451 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
452 {
453 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
454 }
455
456 /**
457 * @brief Get Architecture version
458 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
459 * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension")
460 */
LL_CPUID_GetArchitecture(void)461 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
462 {
463 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
464 }
465
466 /**
467 * @brief Get Part number
468 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
469 * @retval Value should be equal to 0xD21 for Cortex-M33
470 */
LL_CPUID_GetParNo(void)471 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
472 {
473 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
474 }
475
476 /**
477 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
478 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
479 * @retval Value between 0 and 255 (0x1: patch 1)
480 */
LL_CPUID_GetRevision(void)481 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
482 {
483 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
484 }
485
486 /**
487 * @}
488 */
489
490 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
491 * @{
492 */
493
494 /**
495 * @brief Enable MPU with input options
496 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
497 * @param MPU_Control This parameter can be one of the following values:
498 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
499 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
500 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
501 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
502 * @retval None
503 */
LL_MPU_Enable(uint32_t MPU_Control)504 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
505 {
506 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
507
508 /* Enable the MPU*/
509 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
510
511 /* Follow ARM recommendation with */
512 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
513 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
514 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
515 }
516
517 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
518 /**
519 * @brief Enable non-secure MPU with input options
520 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
521 * @param MPU_Control This parameter can be one of the following values:
522 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
523 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
524 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
525 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
526 * @retval None
527 */
LL_MPU_Enable_NS(uint32_t MPU_Control)528 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
529 {
530 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
531
532 /* Enable the MPU*/
533 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
534
535 /* Follow ARM recommendation with */
536 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
537 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
538 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
539 }
540 #endif /* __ARM_FEATURE_CMSE */
541
542 /**
543 * @brief Disable MPU
544 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
545 * @retval None
546 */
LL_MPU_Disable(void)547 __STATIC_INLINE void LL_MPU_Disable(void)
548 {
549 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
550
551 /* Disable MPU */
552 WRITE_REG(MPU->CTRL, 0U);
553
554 /* Follow ARM recommendation with */
555 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
556 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
557 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
558 }
559
560 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
561 /**
562 * @brief Disable the non-secure MPU
563 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
564 * @retval None
565 */
LL_MPU_Disable_NS(void)566 __STATIC_INLINE void LL_MPU_Disable_NS(void)
567 {
568 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
569
570 /* Disable MPU*/
571 WRITE_REG(MPU_NS->CTRL, 0U);
572
573 /* Follow ARM recommendation with */
574 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
575 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
576 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
577 }
578 #endif /* __ARM_FEATURE_CMSE */
579
580
581 /**
582 * @brief Check if MPU is enabled or not
583 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
584 * @retval State of bit (1 or 0).
585 */
LL_MPU_IsEnabled(void)586 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
587 {
588 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
589 }
590
591 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
592 /**
593 * @brief Check if non-secure MPU is enabled or not
594 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
595 * @retval State of bit (1 or 0).
596 */
LL_MPU_IsEnabled_NS(void)597 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
598 {
599 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
600 }
601 #endif /* __ARM_FEATURE_CMSE */
602
603 /**
604 * @brief Enable a MPU region
605 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
606 * @param Region This parameter can be one of the following values:
607 * @arg @ref LL_MPU_REGION_NUMBER0
608 * @arg @ref LL_MPU_REGION_NUMBER1
609 * @arg @ref LL_MPU_REGION_NUMBER2
610 * @arg @ref LL_MPU_REGION_NUMBER3
611 * @arg @ref LL_MPU_REGION_NUMBER4
612 * @arg @ref LL_MPU_REGION_NUMBER5
613 * @arg @ref LL_MPU_REGION_NUMBER6
614 * @arg @ref LL_MPU_REGION_NUMBER7
615 * @note cortex-M33 supports 8 secure and 8 non secure regions.
616 * @retval None
617 */
LL_MPU_EnableRegion(uint32_t Region)618 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
619 {
620 /* Set Region number */
621 WRITE_REG(MPU->RNR, Region);
622
623 /* Enable the MPU region */
624 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
625 }
626
627 /**
628 * @brief Check if MPU region is enabled or not
629 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
630 * @param Region This parameter can be one of the following values:
631 * @arg @ref LL_MPU_REGION_NUMBER0
632 * @arg @ref LL_MPU_REGION_NUMBER1
633 * @arg @ref LL_MPU_REGION_NUMBER2
634 * @arg @ref LL_MPU_REGION_NUMBER3
635 * @arg @ref LL_MPU_REGION_NUMBER4
636 * @arg @ref LL_MPU_REGION_NUMBER5
637 * @arg @ref LL_MPU_REGION_NUMBER6
638 * @arg @ref LL_MPU_REGION_NUMBER7
639 * @note cortex-M33 supports 8 secure and 8 non secure regions.
640 * @retval State of bit (1 or 0).
641 */
LL_MPU_IsEnabled_Region(uint32_t Region)642 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
643 {
644 /* Set region index */
645 WRITE_REG(MPU->RNR, Region);
646
647 /* Return MPU region status */
648 return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
649 }
650
651 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
652 /**
653 * @brief Enable a non-secure MPU region
654 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
655 * @param Region This parameter can be one of the following values:
656 * @arg @ref LL_MPU_REGION_NUMBER0
657 * @arg @ref LL_MPU_REGION_NUMBER1
658 * @arg @ref LL_MPU_REGION_NUMBER2
659 * @arg @ref LL_MPU_REGION_NUMBER3
660 * @arg @ref LL_MPU_REGION_NUMBER4
661 * @arg @ref LL_MPU_REGION_NUMBER5
662 * @arg @ref LL_MPU_REGION_NUMBER6
663 * @arg @ref LL_MPU_REGION_NUMBER7
664 * @note cortex-M33 supports 8 secure and 8 non secure regions.
665 * @retval None
666 */
LL_MPU_EnableRegion_NS(uint32_t Region)667 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
668 {
669 /* Set Region number */
670 WRITE_REG(MPU_NS->RNR, Region);
671
672 /* Enable the MPU region */
673 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
674 }
675
676 /**
677 * @brief Check if non-secure MPU region is enabled or not
678 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS
679 * @param Region This parameter can be one of the following values:
680 * @arg @ref LL_MPU_REGION_NUMBER0
681 * @arg @ref LL_MPU_REGION_NUMBER1
682 * @arg @ref LL_MPU_REGION_NUMBER2
683 * @arg @ref LL_MPU_REGION_NUMBER3
684 * @arg @ref LL_MPU_REGION_NUMBER4
685 * @arg @ref LL_MPU_REGION_NUMBER5
686 * @arg @ref LL_MPU_REGION_NUMBER6
687 * @arg @ref LL_MPU_REGION_NUMBER7
688 * @note cortex-M33 supports 8 secure and 8 non secure regions.
689 * @retval State of bit (1 or 0).
690 */
LL_MPU_IsEnabled_Region_NS(uint32_t Region)691 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
692 {
693 /* Set region index */
694 WRITE_REG(MPU_NS->RNR, Region);
695
696 /* Return non-secure MPU region status */
697 return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
698 }
699 #endif /* __ARM_FEATURE_CMSE */
700
701 /**
702 * @brief Disable a MPU region
703 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
704 * MPU_RLAR ENABLE LL_MPU_DisableRegion
705 * @param Region This parameter can be one of the following values:
706 * @arg @ref LL_MPU_REGION_NUMBER0
707 * @arg @ref LL_MPU_REGION_NUMBER1
708 * @arg @ref LL_MPU_REGION_NUMBER2
709 * @arg @ref LL_MPU_REGION_NUMBER3
710 * @arg @ref LL_MPU_REGION_NUMBER4
711 * @arg @ref LL_MPU_REGION_NUMBER5
712 * @arg @ref LL_MPU_REGION_NUMBER6
713 * @arg @ref LL_MPU_REGION_NUMBER7
714 * @note cortex-M33 supports 8 secure and 8 non secure regions.
715 * @retval None
716 */
LL_MPU_DisableRegion(uint32_t Region)717 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
718 {
719 /* Set Region number */
720 WRITE_REG(MPU->RNR, Region);
721
722 /* Disable the MPU region */
723 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
724 }
725
726 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
727 /**
728 * @brief Disable a non-secure MPU region
729 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
730 * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
731 * @param Region This parameter can be one of the following values:
732 * @arg @ref LL_MPU_REGION_NUMBER0
733 * @arg @ref LL_MPU_REGION_NUMBER1
734 * @arg @ref LL_MPU_REGION_NUMBER2
735 * @arg @ref LL_MPU_REGION_NUMBER3
736 * @arg @ref LL_MPU_REGION_NUMBER4
737 * @arg @ref LL_MPU_REGION_NUMBER5
738 * @arg @ref LL_MPU_REGION_NUMBER6
739 * @arg @ref LL_MPU_REGION_NUMBER7
740 * @note cortex-M33 supports 8 secure and 8 non secure regions.
741 * @retval None
742 */
LL_MPU_DisableRegion_NS(uint32_t Region)743 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
744 {
745 /* Set Region number */
746 WRITE_REG(MPU_NS->RNR, Region);
747
748 /* Disable the MPU region */
749 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
750 }
751 #endif /* __ARM_FEATURE_CMSE */
752
753 /**
754 * @brief Configure and enable a MPU region
755 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
756 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
757 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
758 * MPU_RBAR XN LL_MPU_ConfigRegion\n
759 * MPU_RBAR AP LL_MPU_ConfigRegion\n
760 * MPU_RBAR SH LL_MPU_ConfigRegion\n
761 * MPU_RLAR EN LL_MPU_ConfigRegion\n
762 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
763 * @param Region This parameter can be one of the following values:
764 * @arg @ref LL_MPU_REGION_NUMBER0
765 * @arg @ref LL_MPU_REGION_NUMBER1
766 * @arg @ref LL_MPU_REGION_NUMBER2
767 * @arg @ref LL_MPU_REGION_NUMBER3
768 * @arg @ref LL_MPU_REGION_NUMBER4
769 * @arg @ref LL_MPU_REGION_NUMBER5
770 * @arg @ref LL_MPU_REGION_NUMBER6
771 * @arg @ref LL_MPU_REGION_NUMBER7
772 * @param Attributes This parameter can be a combination of the following values:
773 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
774 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
775 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
776 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
777 * or @ref LL_MPU_REGION_ALL_RO
778 * @param AttrIndx This parameter can be one of the following values:
779 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
780 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
781 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
782 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
783 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
784 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
785 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
786 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
787 * @param BaseAddress Value of region base address
788 * @param LimitAddress Value of region limit address
789 * @note cortex-M33 supports 8 secure and 8 non secure regions.
790 * @retval None
791 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)792 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
793 uint32_t LimitAddress)
794 {
795 /* Set region index */
796 WRITE_REG(MPU->RNR, Region);
797
798 /* Set region base address and region access attributes */
799 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
800
801 /* Set region limit address, memory attributes index and enable region */
802 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
803 }
804
805 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
806 /**
807 * @brief Configure and enable a non-secure MPU region
808 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
809 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
810 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
811 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
812 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
813 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
814 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
815 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
816 * @param Region This parameter can be one of the following values:
817 * @arg @ref LL_MPU_REGION_NUMBER0
818 * @arg @ref LL_MPU_REGION_NUMBER1
819 * @arg @ref LL_MPU_REGION_NUMBER2
820 * @arg @ref LL_MPU_REGION_NUMBER3
821 * @arg @ref LL_MPU_REGION_NUMBER4
822 * @arg @ref LL_MPU_REGION_NUMBER5
823 * @arg @ref LL_MPU_REGION_NUMBER6
824 * @arg @ref LL_MPU_REGION_NUMBER7
825 * @param Attributes This parameter can be a combination of the following values:
826 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
827 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
828 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
829 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
830 * or @ref LL_MPU_REGION_ALL_RO
831 * @param AttrIndx This parameter can be one of the following values:
832 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
833 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
834 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
835 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
836 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
837 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
838 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
839 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
840 * @param BaseAddress Value of region base address
841 * @param LimitAddress Value of region limit address
842 * @note cortex-M33 supports 8 secure and 8 non secure regions.
843 * @retval None
844 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)845 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
846 uint32_t BaseAddress, uint32_t LimitAddress)
847 {
848 /* Set Region number */
849 WRITE_REG(MPU_NS->RNR, Region);
850
851 /* Set region base address and region access attributes */
852 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
853
854 /* Set region limit address, memory attributes index and enable region */
855 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
856 }
857 #endif /* __ARM_FEATURE_CMSE */
858
859 /**
860 * @brief Configure a MPU region address range
861 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
862 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
863 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
864 * @param Region This parameter can be one of the following values:
865 * @arg @ref LL_MPU_REGION_NUMBER0
866 * @arg @ref LL_MPU_REGION_NUMBER1
867 * @arg @ref LL_MPU_REGION_NUMBER2
868 * @arg @ref LL_MPU_REGION_NUMBER3
869 * @arg @ref LL_MPU_REGION_NUMBER4
870 * @arg @ref LL_MPU_REGION_NUMBER5
871 * @arg @ref LL_MPU_REGION_NUMBER6
872 * @arg @ref LL_MPU_REGION_NUMBER7
873 * @param BaseAddress Value of region base address
874 * @param LimitAddress Value of region limit address
875 * @note cortex-M33 supports 8 secure and 8 non secure regions.
876 * @retval None
877 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)878 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
879 {
880 /* Set Region number */
881 WRITE_REG(MPU->RNR, Region);
882
883 /* Modify region base address */
884 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
885
886 /* Modify region limit address */
887 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
888 }
889
890 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
891 /**
892 * @brief Configure a non-secure MPU region address range
893 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
894 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
895 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
896 * @param Region This parameter can be one of the following values:
897 * @arg @ref LL_MPU_REGION_NUMBER0
898 * @arg @ref LL_MPU_REGION_NUMBER1
899 * @arg @ref LL_MPU_REGION_NUMBER2
900 * @arg @ref LL_MPU_REGION_NUMBER3
901 * @arg @ref LL_MPU_REGION_NUMBER4
902 * @arg @ref LL_MPU_REGION_NUMBER5
903 * @arg @ref LL_MPU_REGION_NUMBER6
904 * @arg @ref LL_MPU_REGION_NUMBER7
905 * @param BaseAddress Value of region base address
906 * @param LimitAddress Value of region limit address
907 * @note cortex-M33 supports 8 secure and 8 non secure regions.
908 * @retval None
909 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)910 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
911 {
912 /* Set Region number */
913 WRITE_REG(MPU_NS->RNR, Region);
914
915 /* Set base address */
916 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
917
918 /* Set limit address */
919 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
920 }
921 #endif /* __ARM_FEATURE_CMSE */
922
923 /**
924 * @brief Configure a MPU attributes index
925 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
926 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
927 * @param AttIndex This parameter can be one of the following values:
928 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
929 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
930 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
931 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
932 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
933 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
934 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
935 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
936 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
937 * @retval None
938 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)939 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
940 {
941 /* When selected index is in range [0;3] */
942 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
943 {
944 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
945 MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
946 }
947 /* When selected index is in range [4;7] */
948 else
949 {
950 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
951 MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
952 }
953 }
954
955 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
956 /**
957 * @brief Configure a non-secure MPU attributes index
958 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
959 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
960 * @param AttIndex This parameter can be one of the following values:
961 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
962 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
963 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
964 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
965 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
966 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
967 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
968 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
969 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
970 * @retval None
971 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)972 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
973 {
974 /* When selected index is in range [0;3] */
975 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
976 {
977 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
978 MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
979 }
980 /* When selected index is in range [4;7] */
981 else
982 {
983 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
984 MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
985 }
986 }
987 #endif /* __ARM_FEATURE_CMSE */
988
989 /**
990 * @brief Configure a MPU region limit address
991 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
992 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
993 * @param Region This parameter can be one of the following values:
994 * @arg @ref LL_MPU_REGION_NUMBER0
995 * @arg @ref LL_MPU_REGION_NUMBER1
996 * @arg @ref LL_MPU_REGION_NUMBER2
997 * @arg @ref LL_MPU_REGION_NUMBER3
998 * @arg @ref LL_MPU_REGION_NUMBER4
999 * @arg @ref LL_MPU_REGION_NUMBER5
1000 * @arg @ref LL_MPU_REGION_NUMBER6
1001 * @arg @ref LL_MPU_REGION_NUMBER7
1002 * @param LimitAddress Value of region limit address
1003 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1004 * @retval None
1005 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)1006 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
1007 {
1008 /* Set Region number */
1009 WRITE_REG(MPU->RNR, Region);
1010
1011 /* Set limit address */
1012 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1013 }
1014
1015 /**
1016 * @brief Get a MPU region limit address
1017 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
1018 * @param Region This parameter can be one of the following values:
1019 * @arg @ref LL_MPU_REGION_NUMBER0
1020 * @arg @ref LL_MPU_REGION_NUMBER1
1021 * @arg @ref LL_MPU_REGION_NUMBER2
1022 * @arg @ref LL_MPU_REGION_NUMBER3
1023 * @arg @ref LL_MPU_REGION_NUMBER4
1024 * @arg @ref LL_MPU_REGION_NUMBER5
1025 * @arg @ref LL_MPU_REGION_NUMBER6
1026 * @arg @ref LL_MPU_REGION_NUMBER7
1027 * @retval None
1028 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)1029 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
1030 {
1031 /* Set Region number */
1032 WRITE_REG(MPU->RNR, Region);
1033
1034 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
1035 }
1036
1037 /**
1038 * @brief Configure a MPU region base address
1039 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1040 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
1041 * @param Region This parameter can be one of the following values:
1042 * @arg @ref LL_MPU_REGION_NUMBER0
1043 * @arg @ref LL_MPU_REGION_NUMBER1
1044 * @arg @ref LL_MPU_REGION_NUMBER2
1045 * @arg @ref LL_MPU_REGION_NUMBER3
1046 * @arg @ref LL_MPU_REGION_NUMBER4
1047 * @arg @ref LL_MPU_REGION_NUMBER5
1048 * @arg @ref LL_MPU_REGION_NUMBER6
1049 * @arg @ref LL_MPU_REGION_NUMBER7
1050 * @param BaseAddress Value of region base address
1051 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1052 * @retval None
1053 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1054 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1055 {
1056 /* Set Region number */
1057 WRITE_REG(MPU->RNR, Region);
1058
1059 /* Set base address */
1060 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1061 }
1062
1063 /**
1064 * @brief Get a MPU region base address
1065 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1066 * @param Region This parameter can be one of the following values:
1067 * @arg @ref LL_MPU_REGION_NUMBER0
1068 * @arg @ref LL_MPU_REGION_NUMBER1
1069 * @arg @ref LL_MPU_REGION_NUMBER2
1070 * @arg @ref LL_MPU_REGION_NUMBER3
1071 * @arg @ref LL_MPU_REGION_NUMBER4
1072 * @arg @ref LL_MPU_REGION_NUMBER5
1073 * @arg @ref LL_MPU_REGION_NUMBER6
1074 * @arg @ref LL_MPU_REGION_NUMBER7
1075 * @retval None
1076 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1077 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1078 {
1079 /* Set Region number */
1080 WRITE_REG(MPU->RNR, Region);
1081
1082 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1083 }
1084
1085 /**
1086 * @brief Configure a MPU region access attributes and enable a region
1087 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1088 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1089 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1090 * MPU_RBAR SH LL_MPU_SetRegionAccess\n
1091 * @param Region This parameter can be one of the following values:
1092 * @arg @ref LL_MPU_REGION_NUMBER0
1093 * @arg @ref LL_MPU_REGION_NUMBER1
1094 * @arg @ref LL_MPU_REGION_NUMBER2
1095 * @arg @ref LL_MPU_REGION_NUMBER3
1096 * @arg @ref LL_MPU_REGION_NUMBER4
1097 * @arg @ref LL_MPU_REGION_NUMBER5
1098 * @arg @ref LL_MPU_REGION_NUMBER6
1099 * @arg @ref LL_MPU_REGION_NUMBER7
1100 * @param Attributes This parameter can be a combination of the following values:
1101 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1102 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1103 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1104 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1105 * or @ref LL_MPU_REGION_ALL_RO
1106 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1107 * @retval None
1108 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1109 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1110 {
1111 /* Set Region number */
1112 WRITE_REG(MPU->RNR, Region);
1113
1114 /* Set base address */
1115 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1116 }
1117
1118 /**
1119 * @brief Get a MPU region access attributes
1120 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1121 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1122 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1123 * MPU_RBAR SH LL_MPU_GetRegionAccess\n
1124 * @param Region This parameter can be one of the following values:
1125 * @arg @ref LL_MPU_REGION_NUMBER0
1126 * @arg @ref LL_MPU_REGION_NUMBER1
1127 * @arg @ref LL_MPU_REGION_NUMBER2
1128 * @arg @ref LL_MPU_REGION_NUMBER3
1129 * @arg @ref LL_MPU_REGION_NUMBER4
1130 * @arg @ref LL_MPU_REGION_NUMBER5
1131 * @arg @ref LL_MPU_REGION_NUMBER6
1132 * @arg @ref LL_MPU_REGION_NUMBER7
1133 * @retval None
1134 */
LL_MPU_GetRegionAccess(uint32_t Region)1135 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1136 {
1137 /* Set Region number */
1138 WRITE_REG(MPU->RNR, Region);
1139
1140 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1141 }
1142
1143 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1144 /**
1145 * @brief Configure a non-secure MPU region limit address
1146 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1147 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
1148 * @param Region This parameter can be one of the following values:
1149 * @arg @ref LL_MPU_REGION_NUMBER0
1150 * @arg @ref LL_MPU_REGION_NUMBER1
1151 * @arg @ref LL_MPU_REGION_NUMBER2
1152 * @arg @ref LL_MPU_REGION_NUMBER3
1153 * @arg @ref LL_MPU_REGION_NUMBER4
1154 * @arg @ref LL_MPU_REGION_NUMBER5
1155 * @arg @ref LL_MPU_REGION_NUMBER6
1156 * @arg @ref LL_MPU_REGION_NUMBER7
1157 * @param LimitAddress Value of region limit address
1158 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1159 * @retval None
1160 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1161 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1162 {
1163 /* Set Region number */
1164 WRITE_REG(MPU_NS->RNR, Region);
1165
1166 /* Set limit address */
1167 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1168 }
1169
1170 /**
1171 * @brief Get a non-secure MPU region limit address
1172 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1173 * @param Region This parameter can be one of the following values:
1174 * @arg @ref LL_MPU_REGION_NUMBER0
1175 * @arg @ref LL_MPU_REGION_NUMBER1
1176 * @arg @ref LL_MPU_REGION_NUMBER2
1177 * @arg @ref LL_MPU_REGION_NUMBER3
1178 * @arg @ref LL_MPU_REGION_NUMBER4
1179 * @arg @ref LL_MPU_REGION_NUMBER5
1180 * @arg @ref LL_MPU_REGION_NUMBER6
1181 * @arg @ref LL_MPU_REGION_NUMBER7
1182 * @retval None
1183 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1184 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1185 {
1186 /* Set Region number */
1187 WRITE_REG(MPU_NS->RNR, Region);
1188
1189 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1190 }
1191
1192 /**
1193 * @brief Configure a non-secure MPU region base address
1194 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1195 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
1196 * @param Region This parameter can be one of the following values:
1197 * @arg @ref LL_MPU_REGION_NUMBER0
1198 * @arg @ref LL_MPU_REGION_NUMBER1
1199 * @arg @ref LL_MPU_REGION_NUMBER2
1200 * @arg @ref LL_MPU_REGION_NUMBER3
1201 * @arg @ref LL_MPU_REGION_NUMBER4
1202 * @arg @ref LL_MPU_REGION_NUMBER5
1203 * @arg @ref LL_MPU_REGION_NUMBER6
1204 * @arg @ref LL_MPU_REGION_NUMBER7
1205 * @param BaseAddress Value of region base address
1206 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1207 * @retval None
1208 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1209 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1210 {
1211 /* Set Region number */
1212 WRITE_REG(MPU_NS->RNR, Region);
1213
1214 /* Set base address */
1215 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1216 }
1217
1218 /**
1219 * @brief Get a non-secure MPU region base address
1220 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1221 * @param Region This parameter can be one of the following values:
1222 * @arg @ref LL_MPU_REGION_NUMBER0
1223 * @arg @ref LL_MPU_REGION_NUMBER1
1224 * @arg @ref LL_MPU_REGION_NUMBER2
1225 * @arg @ref LL_MPU_REGION_NUMBER3
1226 * @arg @ref LL_MPU_REGION_NUMBER4
1227 * @arg @ref LL_MPU_REGION_NUMBER5
1228 * @arg @ref LL_MPU_REGION_NUMBER6
1229 * @arg @ref LL_MPU_REGION_NUMBER7
1230 * @retval None
1231 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1232 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1233 {
1234 /* Set Region number */
1235 WRITE_REG(MPU_NS->RNR, Region);
1236
1237 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1238 }
1239
1240 /**
1241 * @brief Configure a non-secure MPU region access attributes and enable a region
1242 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1243 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1244 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1245 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
1246 * @param Region This parameter can be one of the following values:
1247 * @arg @ref LL_MPU_REGION_NUMBER0
1248 * @arg @ref LL_MPU_REGION_NUMBER1
1249 * @arg @ref LL_MPU_REGION_NUMBER2
1250 * @arg @ref LL_MPU_REGION_NUMBER3
1251 * @arg @ref LL_MPU_REGION_NUMBER4
1252 * @arg @ref LL_MPU_REGION_NUMBER5
1253 * @arg @ref LL_MPU_REGION_NUMBER6
1254 * @arg @ref LL_MPU_REGION_NUMBER7
1255 * @param Attributes This parameter can be a combination of the following values:
1256 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1257 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1258 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1259 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1260 * or @ref LL_MPU_REGION_ALL_RO
1261 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1262 * @retval None
1263 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1264 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1265 {
1266 /* Set Region number */
1267 WRITE_REG(MPU_NS->RNR, Region);
1268
1269 /* Set base address Attributes */
1270 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1271 }
1272
1273 /**
1274 * @brief Get a non-secure MPU region access attributes
1275 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1276 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1277 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1278 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
1279 * @param Region This parameter can be one of the following values:
1280 * @arg @ref LL_MPU_REGION_NUMBER0
1281 * @arg @ref LL_MPU_REGION_NUMBER1
1282 * @arg @ref LL_MPU_REGION_NUMBER2
1283 * @arg @ref LL_MPU_REGION_NUMBER3
1284 * @arg @ref LL_MPU_REGION_NUMBER4
1285 * @arg @ref LL_MPU_REGION_NUMBER5
1286 * @arg @ref LL_MPU_REGION_NUMBER6
1287 * @arg @ref LL_MPU_REGION_NUMBER7
1288 * @retval None
1289 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1290 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1291 {
1292 /* Set Region number */
1293 WRITE_REG(MPU_NS->RNR, Region);
1294
1295 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1296 }
1297 #endif /* __ARM_FEATURE_CMSE */
1298
1299 /**
1300 * @}
1301 */
1302
1303 /**
1304 * @}
1305 */
1306
1307 /**
1308 * @}
1309 */
1310
1311 /**
1312 * @}
1313 */
1314
1315 #ifdef __cplusplus
1316 }
1317 #endif
1318
1319 #endif /* STM32U5xx_LL_CORTEX_H */
1320
1321
