1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) API to access to MCU info (CPUID register)
28 (+) API to enable fault handler (SHCSR accesses)
29 (+) API to enable and disable the MPU secure and non-secure
30 (+) API to configure the region of MPU secure and non-secure
31 (+) API to configure the attributes region of MPU secure and non-secure
32
33 @endverbatim
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32U5xx_LL_CORTEX_H
38 #define STM32U5xx_LL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32u5xx.h"
46
47 /** @addtogroup STM32U5xx_LL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX_LL CORTEX
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57 /* Private constants ---------------------------------------------------------*/
58 /* Private macros ------------------------------------------------------------*/
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
62 * @{
63 */
64
65 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
66 * @{
67 */
68 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
69 clock source */
70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
71 clock source */
72 /**
73 * @}
74 */
75
76 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
77 * @{
78 */
79 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
80 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
81 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
82 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
83 /**
84 * @}
85 */
86
87 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
88 * @{
89 */
90 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
91 #define LL_MPU_CTRL_HARDFAULT_NMI 2U
92 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
93 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
94 /**
95 * @}
96 */
97
98 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
99 * @{
100 */
101 #define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
102 #define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
103 #define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
104 #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
105
106 #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
107 #define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
108 #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
109
110 #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
111 #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
112
113 #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
114 #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
115 #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
116 #define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
117 /**
118 * @}
119 */
120
121 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
122 * @{
123 */
124 #define LL_MPU_REGION_ENABLE 1U
125 #define LL_MPU_REGION_DISABLE 0U
126 /**
127 * @}
128 */
129
130 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
131 * @{
132 */
133 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
134 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
135 /**
136 * @}
137 */
138
139 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
140 * @{
141 */
142 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
143 #define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
144 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
145 /**
146 * @}
147 */
148
149 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
150 * @{
151 */
152 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
153 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
154 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
155 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
156 /**
157 * @}
158 */
159
160 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
161 * @{
162 */
163 #define LL_MPU_REGION_NUMBER0 0U
164 #define LL_MPU_REGION_NUMBER1 1U
165 #define LL_MPU_REGION_NUMBER2 2U
166 #define LL_MPU_REGION_NUMBER3 3U
167 #define LL_MPU_REGION_NUMBER4 4U
168 #define LL_MPU_REGION_NUMBER5 5U
169 #define LL_MPU_REGION_NUMBER6 6U
170 #define LL_MPU_REGION_NUMBER7 7U
171 /**
172 * @}
173 */
174
175 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
176 * @{
177 */
178 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
179 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
180 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
181 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
182 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
183 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
184 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
185 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
186 /**
187 * @}
188 */
189
190 /**
191 * @}
192 */
193
194 /* Exported macro ------------------------------------------------------------*/
195
196 /* Exported functions --------------------------------------------------------*/
197 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
198 * @{
199 */
200
201 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
202 * @brief CORTEX SYSTICK LL module driver
203 * @{
204 */
205
206 /**
207 * @brief This function checks if the Systick counter flag is active or not.
208 * @note It can be used in timeout function on application side.
209 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
210 * @retval State of bit (1 or 0).
211 */
LL_SYSTICK_IsActiveCounterFlag(void)212 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
213 {
214 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
215 }
216
217 /**
218 * @brief Configures the SysTick clock source
219 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
220 * @param Source This parameter can be one of the following values:
221 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
222 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
223 * @retval None
224 */
LL_SYSTICK_SetClkSource(uint32_t Source)225 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
226 {
227 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
228 {
229 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
230 }
231 else
232 {
233 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
234 }
235 }
236
237 /**
238 * @brief Get the SysTick clock source
239 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
240 * @retval Returned value can be one of the following values:
241 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
242 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
243 */
LL_SYSTICK_GetClkSource(void)244 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
245 {
246 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
247 }
248
249 /**
250 * @brief Enable SysTick exception request
251 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
252 * @retval None
253 */
LL_SYSTICK_EnableIT(void)254 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
255 {
256 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
257 }
258
259 /**
260 * @brief Disable SysTick exception request
261 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
262 * @retval None
263 */
LL_SYSTICK_DisableIT(void)264 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
265 {
266 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
267 }
268
269 /**
270 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
271 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
272 * @retval State of bit (1 or 0).
273 */
LL_SYSTICK_IsEnabledIT(void)274 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
275 {
276 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
277 }
278
279 /**
280 * @}
281 */
282
283 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
284 * @{
285 */
286
287 /**
288 * @brief Processor uses sleep as its low power mode
289 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
290 * @retval None
291 */
LL_LPM_EnableSleep(void)292 __STATIC_INLINE void LL_LPM_EnableSleep(void)
293 {
294 /* Clear SLEEPDEEP bit of Cortex System Control Register */
295 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
296 }
297
298 /**
299 * @brief Processor uses deep sleep as its low power mode
300 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
301 * @retval None
302 */
LL_LPM_EnableDeepSleep(void)303 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
304 {
305 /* Set SLEEPDEEP bit of Cortex System Control Register */
306 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
307 }
308
309 /**
310 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
311 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
312 * empty main application.
313 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
314 * @retval None
315 */
LL_LPM_EnableSleepOnExit(void)316 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
317 {
318 /* Set SLEEPONEXIT bit of Cortex System Control Register */
319 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
320 }
321
322 /**
323 * @brief Do not sleep when returning to Thread mode.
324 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
325 * @retval None
326 */
LL_LPM_DisableSleepOnExit(void)327 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
328 {
329 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
330 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
331 }
332
333 /**
334 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
335 * processor.
336 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
337 * @retval None
338 */
LL_LPM_EnableEventOnPend(void)339 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
340 {
341 /* Set SEVEONPEND bit of Cortex System Control Register */
342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
343 }
344
345 /**
346 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
347 * excluded
348 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
349 * @retval None
350 */
LL_LPM_DisableEventOnPend(void)351 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
352 {
353 /* Clear SEVEONPEND bit of Cortex System Control Register */
354 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
355 }
356
357 /**
358 * @}
359 */
360
361 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
362 * @{
363 */
364
365 /**
366 * @brief Enable a fault in System handler control register (SHCSR)
367 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
368 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
369 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
370 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
371 * @param Fault This parameter can be a combination of the following values:
372 * @arg @ref LL_HANDLER_FAULT_USG
373 * @arg @ref LL_HANDLER_FAULT_BUS
374 * @arg @ref LL_HANDLER_FAULT_MEM
375 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
376 *
377 * (*) value applicable in secure when the system implements the security.
378 * @retval None
379 */
LL_HANDLER_EnableFault(uint32_t Fault)380 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
381 {
382 /* Enable the system handler fault */
383 SET_BIT(SCB->SHCSR, Fault);
384 }
385
386 /**
387 * @brief Disable a fault in System handler control register (SHCSR)
388 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
389 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
390 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
391 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
392 * @param Fault This parameter can be a combination of the following values:
393 * @arg @ref LL_HANDLER_FAULT_USG
394 * @arg @ref LL_HANDLER_FAULT_BUS
395 * @arg @ref LL_HANDLER_FAULT_MEM
396 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
397 *
398 * (*) value applicable in secure when the system implements the security.
399 * @retval None
400 */
LL_HANDLER_DisableFault(uint32_t Fault)401 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
402 {
403 /* Disable the system handler fault */
404 CLEAR_BIT(SCB->SHCSR, Fault);
405 }
406
407 /**
408 * @}
409 */
410
411 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
412 * @{
413 */
414
415 /**
416 * @brief Get Implementer code
417 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
418 * @retval Value should be equal to 0x41 for ARM
419 */
LL_CPUID_GetImplementer(void)420 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
421 {
422 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
423 }
424
425 /**
426 * @brief Get Variant number (The r value in the rnpn product revision identifier)
427 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
428 * @retval Value between 0 and 255 (0x0: revision 0)
429 */
LL_CPUID_GetVariant(void)430 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
431 {
432 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
433 }
434
435 /**
436 * @brief Get Constant number
437 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
438 * @retval Value should be equal to 0xF for Cortex-M33 devices
439 */
LL_CPUID_GetConstant(void)440 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
441 {
442 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
443 }
444
445 /**
446 * @brief Get Part number
447 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
448 * @retval Value should be equal to 0xD21 for Cortex-M33
449 */
LL_CPUID_GetParNo(void)450 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
451 {
452 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
453 }
454
455 /**
456 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
457 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
458 * @retval Value between 0 and 255 (0x1: patch 1)
459 */
LL_CPUID_GetRevision(void)460 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
461 {
462 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
463 }
464
465 /**
466 * @}
467 */
468
469 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
470 * @{
471 */
472
473 /**
474 * @brief Enable MPU with input options
475 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
476 * @param MPU_Control This parameter can be one of the following values:
477 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
478 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
479 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
480 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
481 * @retval None
482 */
LL_MPU_Enable(uint32_t MPU_Control)483 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
484 {
485 /* Enable the MPU*/
486 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
487
488 /* Ensure MPU settings take effects */
489 __DSB();
490
491 /* Sequence instruction fetches using update settings */
492 __ISB();
493 }
494
495 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
496 /**
497 * @brief Enable non-secure MPU with input options
498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
499 * @param MPU_Control This parameter can be one of the following values:
500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
504 * @retval None
505 */
LL_MPU_Enable_NS(uint32_t MPU_Control)506 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
507 {
508 /* Enable the MPU*/
509 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
510
511 /* Ensure MPU settings take effects */
512 __DSB();
513
514 /* Sequence instruction fetches using update settings */
515 __ISB();
516 }
517 #endif /* __ARM_FEATURE_CMSE */
518
519 /**
520 * @brief Disable MPU
521 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
522 * @retval None
523 */
LL_MPU_Disable(void)524 __STATIC_INLINE void LL_MPU_Disable(void)
525 {
526 /* Make sure outstanding transfers are done */
527 __DMB();
528 /* Disable MPU*/
529 WRITE_REG(MPU->CTRL, 0U);
530 }
531
532 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
533 /**
534 * @brief Disable the non-secure MPU
535 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
536 * @retval None
537 */
LL_MPU_Disable_NS(void)538 __STATIC_INLINE void LL_MPU_Disable_NS(void)
539 {
540 /* Make sure outstanding transfers are done */
541 __DMB();
542 /* Disable MPU*/
543 WRITE_REG(MPU_NS->CTRL, 0U);
544 }
545 #endif /* __ARM_FEATURE_CMSE */
546
547
548 /**
549 * @brief Check if MPU is enabled or not
550 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
551 * @retval State of bit (1 or 0).
552 */
LL_MPU_IsEnabled(void)553 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
554 {
555 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
556 }
557
558 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
559 /**
560 * @brief Check if non-secure MPU is enabled or not
561 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
562 * @retval State of bit (1 or 0).
563 */
LL_MPU_IsEnabled_NS(void)564 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
565 {
566 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
567 }
568 #endif /* __ARM_FEATURE_CMSE */
569
570 /**
571 * @brief Enable a MPU region
572 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
573 * @param Region This parameter can be one of the following values:
574 * @arg @ref LL_MPU_REGION_NUMBER0
575 * @arg @ref LL_MPU_REGION_NUMBER1
576 * @arg @ref LL_MPU_REGION_NUMBER2
577 * @arg @ref LL_MPU_REGION_NUMBER3
578 * @arg @ref LL_MPU_REGION_NUMBER4
579 * @arg @ref LL_MPU_REGION_NUMBER5
580 * @arg @ref LL_MPU_REGION_NUMBER6
581 * @arg @ref LL_MPU_REGION_NUMBER7
582 * @note cortex-M33 supports 8 secure and 8 non secure regions.
583 * @retval None
584 */
LL_MPU_EnableRegion(uint32_t Region)585 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
586 {
587 /* Set Region number */
588 WRITE_REG(MPU->RNR, Region);
589
590 /* Enable the MPU region */
591 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
592 }
593
594 /**
595 * @brief Check if MPU region is enabled or not
596 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabledRegion
597 * @param Region This parameter can be one of the following values:
598 * @arg @ref LL_MPU_REGION_NUMBER0
599 * @arg @ref LL_MPU_REGION_NUMBER1
600 * @arg @ref LL_MPU_REGION_NUMBER2
601 * @arg @ref LL_MPU_REGION_NUMBER3
602 * @arg @ref LL_MPU_REGION_NUMBER4
603 * @arg @ref LL_MPU_REGION_NUMBER5
604 * @arg @ref LL_MPU_REGION_NUMBER6
605 * @arg @ref LL_MPU_REGION_NUMBER7
606 * @note cortex-M33 supports 8 secure and 8 non secure regions.
607 * @retval State of bit (1 or 0).
608 */
LL_MPU_IsEnabled_Region(uint32_t Region)609 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
610 {
611 return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL);
612 }
613
614 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
615 /**
616 * @brief Enable a non-secure MPU region
617 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
618 * @param Region This parameter can be one of the following values:
619 * @arg @ref LL_MPU_REGION_NUMBER0
620 * @arg @ref LL_MPU_REGION_NUMBER1
621 * @arg @ref LL_MPU_REGION_NUMBER2
622 * @arg @ref LL_MPU_REGION_NUMBER3
623 * @arg @ref LL_MPU_REGION_NUMBER4
624 * @arg @ref LL_MPU_REGION_NUMBER5
625 * @arg @ref LL_MPU_REGION_NUMBER6
626 * @arg @ref LL_MPU_REGION_NUMBER7
627 * @note cortex-M33 supports 8 secure and 8 non secure regions.
628 * @retval None
629 */
LL_MPU_EnableRegion_NS(uint32_t Region)630 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
631 {
632 /* Set Region number */
633 WRITE_REG(MPU_NS->RNR, Region);
634
635 /* Enable the MPU region */
636 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
637 }
638
639 /**
640 * @brief Check if non-secure MPU region is enabled or not
641 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnableRegion_NS
642 * @param Region This parameter can be one of the following values:
643 * @arg @ref LL_MPU_REGION_NUMBER0
644 * @arg @ref LL_MPU_REGION_NUMBER1
645 * @arg @ref LL_MPU_REGION_NUMBER2
646 * @arg @ref LL_MPU_REGION_NUMBER3
647 * @arg @ref LL_MPU_REGION_NUMBER4
648 * @arg @ref LL_MPU_REGION_NUMBER5
649 * @arg @ref LL_MPU_REGION_NUMBER6
650 * @arg @ref LL_MPU_REGION_NUMBER7
651 * @note cortex-M33 supports 8 secure and 8 non secure regions.
652 * @retval State of bit (1 or 0).
653 */
LL_MPU_IsEnabled_Region_NS(uint32_t Region)654 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
655 {
656 return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL);
657 }
658 #endif /* __ARM_FEATURE_CMSE */
659
660 /**
661 * @brief Disable a MPU region
662 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
663 * MPU_RLAR ENABLE LL_MPU_DisableRegion
664 * @param Region This parameter can be one of the following values:
665 * @arg @ref LL_MPU_REGION_NUMBER0
666 * @arg @ref LL_MPU_REGION_NUMBER1
667 * @arg @ref LL_MPU_REGION_NUMBER2
668 * @arg @ref LL_MPU_REGION_NUMBER3
669 * @arg @ref LL_MPU_REGION_NUMBER4
670 * @arg @ref LL_MPU_REGION_NUMBER5
671 * @arg @ref LL_MPU_REGION_NUMBER6
672 * @arg @ref LL_MPU_REGION_NUMBER7
673 * @note cortex-M33 supports 8 secure and 8 non secure regions.
674 * @retval None
675 */
LL_MPU_DisableRegion(uint32_t Region)676 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
677 {
678 /* Set Region number */
679 WRITE_REG(MPU->RNR, Region);
680
681 /* Disable the MPU region */
682 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
683 }
684
685 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
686 /**
687 * @brief Disable a non-secure MPU region
688 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
689 * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
690 * @param Region This parameter can be one of the following values:
691 * @arg @ref LL_MPU_REGION_NUMBER0
692 * @arg @ref LL_MPU_REGION_NUMBER1
693 * @arg @ref LL_MPU_REGION_NUMBER2
694 * @arg @ref LL_MPU_REGION_NUMBER3
695 * @arg @ref LL_MPU_REGION_NUMBER4
696 * @arg @ref LL_MPU_REGION_NUMBER5
697 * @arg @ref LL_MPU_REGION_NUMBER6
698 * @arg @ref LL_MPU_REGION_NUMBER7
699 * @note cortex-M33 supports 8 secure and 8 non secure regions.
700 * @retval None
701 */
LL_MPU_DisableRegion_NS(uint32_t Region)702 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
703 {
704 /* Set Region number */
705 WRITE_REG(MPU_NS->RNR, Region);
706
707 /* Disable the MPU region */
708 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
709 }
710 #endif /* __ARM_FEATURE_CMSE */
711
712 /**
713 * @brief Configure and enable a MPU region
714 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
715 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
716 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
717 * MPU_RBAR XN LL_MPU_ConfigRegion\n
718 * MPU_RBAR AP LL_MPU_ConfigRegion\n
719 * MPU_RBAR SH LL_MPU_ConfigRegion\n
720 * MPU_RLAR EN LL_MPU_ConfigRegion\n
721 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
722 * @param Region This parameter can be one of the following values:
723 * @arg @ref LL_MPU_REGION_NUMBER0
724 * @arg @ref LL_MPU_REGION_NUMBER1
725 * @arg @ref LL_MPU_REGION_NUMBER2
726 * @arg @ref LL_MPU_REGION_NUMBER3
727 * @arg @ref LL_MPU_REGION_NUMBER4
728 * @arg @ref LL_MPU_REGION_NUMBER5
729 * @arg @ref LL_MPU_REGION_NUMBER6
730 * @arg @ref LL_MPU_REGION_NUMBER7
731 * @param Attributes This parameter can be a combination of the following values:
732 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
733 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
734 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
735 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
736 * or @ref LL_MPU_REGION_ALL_RO
737 * @param AttrIndx This parameter can be one of the following values:
738 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
739 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
740 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
741 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
742 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
743 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
744 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
745 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
746 * @param BaseAddress Value of region base address
747 * @param LimitAddress Value of region limit address
748 * @note cortex-M33 supports 8 secure and 8 non secure regions.
749 * @retval None
750 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)751 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
752 uint32_t LimitAddress)
753 {
754 /* Set Region number */
755 WRITE_REG(MPU->RNR, Region);
756
757 /* Set base address */
758 MPU->RBAR |= Attributes;
759 /* Set base address */
760 MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
761
762 /* Set limit address */
763 MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
764 /* Configure MPU */
765 MPU->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
766 }
767
768 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
769 /**
770 * @brief Configure and enable a non-secure MPU region
771 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
772 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
773 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
774 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
775 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
776 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
777 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
778 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
779 * @param Region This parameter can be one of the following values:
780 * @arg @ref LL_MPU_REGION_NUMBER0
781 * @arg @ref LL_MPU_REGION_NUMBER1
782 * @arg @ref LL_MPU_REGION_NUMBER2
783 * @arg @ref LL_MPU_REGION_NUMBER3
784 * @arg @ref LL_MPU_REGION_NUMBER4
785 * @arg @ref LL_MPU_REGION_NUMBER5
786 * @arg @ref LL_MPU_REGION_NUMBER6
787 * @arg @ref LL_MPU_REGION_NUMBER7
788 * @param Attributes This parameter can be a combination of the following values:
789 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
790 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
791 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
792 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
793 * or @ref LL_MPU_REGION_ALL_RO
794 * @param AttrIndx This parameter can be one of the following values:
795 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
796 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
797 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
798 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
799 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
800 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
801 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
802 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
803 * @param BaseAddress Value of region base address
804 * @param LimitAddress Value of region limit address
805 * @note cortex-M33 supports 8 secure and 8 non secure regions.
806 * @retval None
807 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)808 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
809 uint32_t BaseAddress, uint32_t LimitAddress)
810 {
811 /* Set Region number */
812 WRITE_REG(MPU_NS->RNR, Region);
813
814 /* Set base address */
815 MPU_NS->RBAR |= Attributes;
816
817 /* Set base address */
818 MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
819
820 /* Set limit address */
821 MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
822 /* Configure MPU */
823 MPU_NS->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
824 }
825 #endif /* __ARM_FEATURE_CMSE */
826
827 /**
828 * @brief Configure a MPU region address range
829 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
830 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
831 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
832 * @param Region This parameter can be one of the following values:
833 * @arg @ref LL_MPU_REGION_NUMBER0
834 * @arg @ref LL_MPU_REGION_NUMBER1
835 * @arg @ref LL_MPU_REGION_NUMBER2
836 * @arg @ref LL_MPU_REGION_NUMBER3
837 * @arg @ref LL_MPU_REGION_NUMBER4
838 * @arg @ref LL_MPU_REGION_NUMBER5
839 * @arg @ref LL_MPU_REGION_NUMBER6
840 * @arg @ref LL_MPU_REGION_NUMBER7
841 * @param BaseAddress Value of region base address
842 * @param LimitAddress Value of region limit address
843 * @note cortex-M33 supports 8 secure and 8 non secure regions.
844 * @retval None
845 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)846 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
847 {
848 /* Set Region number */
849 WRITE_REG(MPU->RNR, Region);
850 /* Set base address */
851 MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U) ;
852
853 /* Set limit address */
854 MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
855 }
856
857 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
858 /**
859 * @brief Configure a non-secure MPU region address range
860 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
861 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
862 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
863 * @param Region This parameter can be one of the following values:
864 * @arg @ref LL_MPU_REGION_NUMBER0
865 * @arg @ref LL_MPU_REGION_NUMBER1
866 * @arg @ref LL_MPU_REGION_NUMBER2
867 * @arg @ref LL_MPU_REGION_NUMBER3
868 * @arg @ref LL_MPU_REGION_NUMBER4
869 * @arg @ref LL_MPU_REGION_NUMBER5
870 * @arg @ref LL_MPU_REGION_NUMBER6
871 * @arg @ref LL_MPU_REGION_NUMBER7
872 * @param BaseAddress Value of region base address
873 * @param LimitAddress Value of region limit address
874 * @note cortex-M33 supports 8 secure and 8 non secure regions.
875 * @retval None
876 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)877 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
878 {
879 /* Set Region number */
880 WRITE_REG(MPU_NS->RNR, Region);
881 /* Set base address */
882 MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
883
884 /* Set limit address */
885 MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
886 }
887 #endif /* __ARM_FEATURE_CMSE */
888
889 /**
890 * @brief Configure a MPU attributes index
891 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
892 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
893 * @param AttIndex This parameter can be one of the following values:
894 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
895 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
896 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
897 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
898 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
899 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
900 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
901 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
902 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
903 * @retval None
904 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)905 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
906 {
907 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
908 {
909 /* Program MPU_MAIR0 */
910 WRITE_REG(MPU->MAIR0, (Attributes << (AttIndex * 8U)));
911 }
912 else
913 {
914 /* Program MPU_MAIR1 */
915 WRITE_REG(MPU->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
916 }
917 }
918
919 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
920 /**
921 * @brief Configure a non-secure MPU attributes index
922 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
923 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
924 * @param AttIndex This parameter can be one of the following values:
925 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
926 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
927 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
928 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
929 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
930 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
931 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
932 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
933 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
934 * @retval None
935 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)936 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
937 {
938 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
939 {
940 /* Program MPU_MAIR0 */
941 WRITE_REG(MPU_NS->MAIR0, (Attributes << (AttIndex * 8U)));
942 }
943 else
944 {
945 /* Program MPU_MAIR1 */
946 WRITE_REG(MPU_NS->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
947 }
948 }
949 #endif /* __ARM_FEATURE_CMSE */
950
951 /**
952 * @brief Configure a MPU region limit address
953 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
954 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
955 * @param Region This parameter can be one of the following values:
956 * @arg @ref LL_MPU_REGION_NUMBER0
957 * @arg @ref LL_MPU_REGION_NUMBER1
958 * @arg @ref LL_MPU_REGION_NUMBER2
959 * @arg @ref LL_MPU_REGION_NUMBER3
960 * @arg @ref LL_MPU_REGION_NUMBER4
961 * @arg @ref LL_MPU_REGION_NUMBER5
962 * @arg @ref LL_MPU_REGION_NUMBER6
963 * @arg @ref LL_MPU_REGION_NUMBER7
964 * @param LimitAddress Value of region limit address
965 * @note cortex-M33 supports 8 secure and 8 non secure regions.
966 * @retval None
967 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)968 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
969 {
970 /* Set Region number */
971 WRITE_REG(MPU->RNR, Region);
972 /* Set limit address */
973 MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
974 }
975
976 /**
977 * @brief Get a MPU region limit address
978 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
979 * @param Region This parameter can be one of the following values:
980 * @arg @ref LL_MPU_REGION_NUMBER0
981 * @arg @ref LL_MPU_REGION_NUMBER1
982 * @arg @ref LL_MPU_REGION_NUMBER2
983 * @arg @ref LL_MPU_REGION_NUMBER3
984 * @arg @ref LL_MPU_REGION_NUMBER4
985 * @arg @ref LL_MPU_REGION_NUMBER5
986 * @arg @ref LL_MPU_REGION_NUMBER6
987 * @arg @ref LL_MPU_REGION_NUMBER7
988 * @retval None
989 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)990 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
991 {
992 /* Set Region number */
993 WRITE_REG(MPU->RNR, Region);
994 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
995 }
996
997 /**
998 * @brief Configure a MPU region base address
999 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1000 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
1001 * @param Region This parameter can be one of the following values:
1002 * @arg @ref LL_MPU_REGION_NUMBER0
1003 * @arg @ref LL_MPU_REGION_NUMBER1
1004 * @arg @ref LL_MPU_REGION_NUMBER2
1005 * @arg @ref LL_MPU_REGION_NUMBER3
1006 * @arg @ref LL_MPU_REGION_NUMBER4
1007 * @arg @ref LL_MPU_REGION_NUMBER5
1008 * @arg @ref LL_MPU_REGION_NUMBER6
1009 * @arg @ref LL_MPU_REGION_NUMBER7
1010 * @param BaseAddress Value of region base address
1011 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1012 * @retval None
1013 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1014 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1015 {
1016 /* Set Region number */
1017 WRITE_REG(MPU->RNR, Region);
1018 /* Set base address */
1019 MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
1020 }
1021
1022 /**
1023 * @brief Get a MPU region base address
1024 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1025 * @param Region This parameter can be one of the following values:
1026 * @arg @ref LL_MPU_REGION_NUMBER0
1027 * @arg @ref LL_MPU_REGION_NUMBER1
1028 * @arg @ref LL_MPU_REGION_NUMBER2
1029 * @arg @ref LL_MPU_REGION_NUMBER3
1030 * @arg @ref LL_MPU_REGION_NUMBER4
1031 * @arg @ref LL_MPU_REGION_NUMBER5
1032 * @arg @ref LL_MPU_REGION_NUMBER6
1033 * @arg @ref LL_MPU_REGION_NUMBER7
1034 * @retval None
1035 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1036 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1037 {
1038 /* Set Region number */
1039 WRITE_REG(MPU->RNR, Region);
1040 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1041 }
1042
1043 /**
1044 * @brief Configure a MPU region access attributes and enable a region
1045 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1046 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1047 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1048 * MPU_RBAR SH LL_MPU_SetRegionAccess\n
1049 * @param Region This parameter can be one of the following values:
1050 * @arg @ref LL_MPU_REGION_NUMBER0
1051 * @arg @ref LL_MPU_REGION_NUMBER1
1052 * @arg @ref LL_MPU_REGION_NUMBER2
1053 * @arg @ref LL_MPU_REGION_NUMBER3
1054 * @arg @ref LL_MPU_REGION_NUMBER4
1055 * @arg @ref LL_MPU_REGION_NUMBER5
1056 * @arg @ref LL_MPU_REGION_NUMBER6
1057 * @arg @ref LL_MPU_REGION_NUMBER7
1058 * @param Attributes This parameter can be a combination of the following values:
1059 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1060 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1061 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1062 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1063 * or @ref LL_MPU_REGION_ALL_RO
1064 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1065 * @retval None
1066 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1067 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1068 {
1069 /* Set Region number */
1070 WRITE_REG(MPU->RNR, Region);
1071 /* Set base address */
1072 MPU->RBAR |= Attributes;
1073 }
1074
1075 /**
1076 * @brief Get a MPU region access attributes
1077 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1078 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1079 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1080 * MPU_RBAR SH LL_MPU_GetRegionAccess\n
1081 * @param Region This parameter can be one of the following values:
1082 * @arg @ref LL_MPU_REGION_NUMBER0
1083 * @arg @ref LL_MPU_REGION_NUMBER1
1084 * @arg @ref LL_MPU_REGION_NUMBER2
1085 * @arg @ref LL_MPU_REGION_NUMBER3
1086 * @arg @ref LL_MPU_REGION_NUMBER4
1087 * @arg @ref LL_MPU_REGION_NUMBER5
1088 * @arg @ref LL_MPU_REGION_NUMBER6
1089 * @arg @ref LL_MPU_REGION_NUMBER7
1090 * @retval None
1091 */
LL_MPU_GetRegionAccess(uint32_t Region)1092 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1093 {
1094 /* Set Region number */
1095 WRITE_REG(MPU->RNR, Region);
1096 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1097 }
1098
1099 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1100 /**
1101 * @brief Configure a non-secure MPU region limit address
1102 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1103 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
1104 * @param Region This parameter can be one of the following values:
1105 * @arg @ref LL_MPU_REGION_NUMBER0
1106 * @arg @ref LL_MPU_REGION_NUMBER1
1107 * @arg @ref LL_MPU_REGION_NUMBER2
1108 * @arg @ref LL_MPU_REGION_NUMBER3
1109 * @arg @ref LL_MPU_REGION_NUMBER4
1110 * @arg @ref LL_MPU_REGION_NUMBER5
1111 * @arg @ref LL_MPU_REGION_NUMBER6
1112 * @arg @ref LL_MPU_REGION_NUMBER7
1113 * @param LimitAddress Value of region limit address
1114 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1115 * @retval None
1116 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1117 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1118 {
1119 /* Set Region number */
1120 WRITE_REG(MPU_NS->RNR, Region);
1121 /* Set limit address */
1122 MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
1123 }
1124
1125 /**
1126 * @brief Get a non-secure MPU region limit address
1127 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1128 * @param Region This parameter can be one of the following values:
1129 * @arg @ref LL_MPU_REGION_NUMBER0
1130 * @arg @ref LL_MPU_REGION_NUMBER1
1131 * @arg @ref LL_MPU_REGION_NUMBER2
1132 * @arg @ref LL_MPU_REGION_NUMBER3
1133 * @arg @ref LL_MPU_REGION_NUMBER4
1134 * @arg @ref LL_MPU_REGION_NUMBER5
1135 * @arg @ref LL_MPU_REGION_NUMBER6
1136 * @arg @ref LL_MPU_REGION_NUMBER7
1137 * @retval None
1138 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1139 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1140 {
1141 /* Set Region number */
1142 WRITE_REG(MPU_NS->RNR, Region);
1143 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1144 }
1145
1146 /**
1147 * @brief Configure a non-secure MPU region base address
1148 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1149 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
1150 * @param Region This parameter can be one of the following values:
1151 * @arg @ref LL_MPU_REGION_NUMBER0
1152 * @arg @ref LL_MPU_REGION_NUMBER1
1153 * @arg @ref LL_MPU_REGION_NUMBER2
1154 * @arg @ref LL_MPU_REGION_NUMBER3
1155 * @arg @ref LL_MPU_REGION_NUMBER4
1156 * @arg @ref LL_MPU_REGION_NUMBER5
1157 * @arg @ref LL_MPU_REGION_NUMBER6
1158 * @arg @ref LL_MPU_REGION_NUMBER7
1159 * @param BaseAddress Value of region base address
1160 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1161 * @retval None
1162 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1163 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1164 {
1165 /* Set Region number */
1166 WRITE_REG(MPU_NS->RNR, Region);
1167 /* Set base address */
1168 MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
1169 }
1170
1171 /**
1172 * @brief Get a non-secure MPU region base address
1173 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1174 * @param Region This parameter can be one of the following values:
1175 * @arg @ref LL_MPU_REGION_NUMBER0
1176 * @arg @ref LL_MPU_REGION_NUMBER1
1177 * @arg @ref LL_MPU_REGION_NUMBER2
1178 * @arg @ref LL_MPU_REGION_NUMBER3
1179 * @arg @ref LL_MPU_REGION_NUMBER4
1180 * @arg @ref LL_MPU_REGION_NUMBER5
1181 * @arg @ref LL_MPU_REGION_NUMBER6
1182 * @arg @ref LL_MPU_REGION_NUMBER7
1183 * @retval None
1184 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1185 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1186 {
1187 /* Set Region number */
1188 WRITE_REG(MPU_NS->RNR, Region);
1189 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1190 }
1191
1192 /**
1193 * @brief Configure a non-secure MPU region access attributes and enable a region
1194 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1195 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1196 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1197 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
1198 * @param Region This parameter can be one of the following values:
1199 * @arg @ref LL_MPU_REGION_NUMBER0
1200 * @arg @ref LL_MPU_REGION_NUMBER1
1201 * @arg @ref LL_MPU_REGION_NUMBER2
1202 * @arg @ref LL_MPU_REGION_NUMBER3
1203 * @arg @ref LL_MPU_REGION_NUMBER4
1204 * @arg @ref LL_MPU_REGION_NUMBER5
1205 * @arg @ref LL_MPU_REGION_NUMBER6
1206 * @arg @ref LL_MPU_REGION_NUMBER7
1207 * @param Attributes This parameter can be a combination of the following values:
1208 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1209 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1210 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1211 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1212 * or @ref LL_MPU_REGION_ALL_RO
1213 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1214 * @retval None
1215 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1216 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1217 {
1218 /* Set Region number */
1219 WRITE_REG(MPU_NS->RNR, Region);
1220 /* Set base address Attributes */
1221 MPU_NS->RBAR |= Attributes;
1222 }
1223
1224 /**
1225 * @brief Get a non-secure MPU region access attributes
1226 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1227 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1228 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1229 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
1230 * @param Region This parameter can be one of the following values:
1231 * @arg @ref LL_MPU_REGION_NUMBER0
1232 * @arg @ref LL_MPU_REGION_NUMBER1
1233 * @arg @ref LL_MPU_REGION_NUMBER2
1234 * @arg @ref LL_MPU_REGION_NUMBER3
1235 * @arg @ref LL_MPU_REGION_NUMBER4
1236 * @arg @ref LL_MPU_REGION_NUMBER5
1237 * @arg @ref LL_MPU_REGION_NUMBER6
1238 * @arg @ref LL_MPU_REGION_NUMBER7
1239 * @retval None
1240 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1241 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1242 {
1243 /* Set Region number */
1244 WRITE_REG(MPU_NS->RNR, Region);
1245 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1246 }
1247 #endif /* __ARM_FEATURE_CMSE */
1248
1249 /**
1250 * @}
1251 */
1252
1253 /**
1254 * @}
1255 */
1256
1257 /**
1258 * @}
1259 */
1260
1261 /**
1262 * @}
1263 */
1264
1265 #ifdef __cplusplus
1266 }
1267 #endif
1268
1269 #endif /* STM32U5xx_LL_CORTEX_H */
1270
1271
