1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_TIM_H 21 #define STM32U5xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 50 Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 58 (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), 59 __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), 60 __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ 61 62 uint32_t ClockDivision; /*!< Specifies the clock division. 63 This parameter can be a value of @ref TIM_ClockDivision */ 64 65 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 66 reaches zero, an update event is generated and counting restarts 67 from the RCR value (N). 68 This means in PWM mode that (N+1) corresponds to: 69 - the number of PWM periods in edge-aligned mode 70 - the number of half PWM period in center-aligned mode 71 GP timers: this parameter must be a number between Min_Data = 0x00 and 72 Max_Data = 0xFF. 73 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 74 Max_Data = 0xFFFF. */ 75 76 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 77 This parameter can be a value of @ref TIM_AutoReloadPreload */ 78 } TIM_Base_InitTypeDef; 79 80 /** 81 * @brief TIM Output Compare Configuration Structure definition 82 */ 83 typedef struct 84 { 85 uint32_t OCMode; /*!< Specifies the TIM mode. 86 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 87 88 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 89 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 90 (or 0xFFEF if dithering is activated) 91 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate 92 Pulse value */ 93 94 uint32_t OCPolarity; /*!< Specifies the output polarity. 95 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 96 97 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 98 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 99 @note This parameter is valid only for timer instances supporting break feature. */ 100 101 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 102 This parameter can be a value of @ref TIM_Output_Fast_State 103 @note This parameter is valid only in PWM1 and PWM2 mode. */ 104 105 106 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 108 @note This parameter is valid only for timer instances supporting break feature. */ 109 110 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 112 @note This parameter is valid only for timer instances supporting break feature. */ 113 } TIM_OC_InitTypeDef; 114 115 /** 116 * @brief TIM One Pulse Mode Configuration Structure definition 117 */ 118 typedef struct 119 { 120 uint32_t OCMode; /*!< Specifies the TIM mode. 121 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 122 123 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 124 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 125 (or 0xFFEF if dithering is activated) 126 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate 127 Pulse value */ 128 129 uint32_t OCPolarity; /*!< Specifies the output polarity. 130 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 131 132 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 133 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 134 @note This parameter is valid only for timer instances supporting break feature. */ 135 136 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 137 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 138 @note This parameter is valid only for timer instances supporting break feature. */ 139 140 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 141 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 142 @note This parameter is valid only for timer instances supporting break feature. */ 143 144 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 145 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 146 147 uint32_t ICSelection; /*!< Specifies the input. 148 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 149 150 uint32_t ICFilter; /*!< Specifies the input capture filter. 151 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 152 } TIM_OnePulse_InitTypeDef; 153 154 /** 155 * @brief TIM Input Capture Configuration Structure definition 156 */ 157 typedef struct 158 { 159 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 160 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 161 162 uint32_t ICSelection; /*!< Specifies the input. 163 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 164 165 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 166 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 167 168 uint32_t ICFilter; /*!< Specifies the input capture filter. 169 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 170 } TIM_IC_InitTypeDef; 171 172 /** 173 * @brief TIM Encoder Configuration Structure definition 174 */ 175 typedef struct 176 { 177 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 178 This parameter can be a value of @ref TIM_Encoder_Mode */ 179 180 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 181 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 182 183 uint32_t IC1Selection; /*!< Specifies the input. 184 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 185 186 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 187 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 188 189 uint32_t IC1Filter; /*!< Specifies the input capture filter. 190 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 191 192 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 193 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 194 195 uint32_t IC2Selection; /*!< Specifies the input. 196 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 197 198 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 199 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 200 201 uint32_t IC2Filter; /*!< Specifies the input capture filter. 202 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 203 } TIM_Encoder_InitTypeDef; 204 205 /** 206 * @brief Clock Configuration Handle Structure definition 207 */ 208 typedef struct 209 { 210 uint32_t ClockSource; /*!< TIM clock sources 211 This parameter can be a value of @ref TIM_Clock_Source */ 212 uint32_t ClockPolarity; /*!< TIM clock polarity 213 This parameter can be a value of @ref TIM_Clock_Polarity */ 214 uint32_t ClockPrescaler; /*!< TIM clock prescaler 215 This parameter can be a value of @ref TIM_Clock_Prescaler */ 216 uint32_t ClockFilter; /*!< TIM clock filter 217 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 218 } TIM_ClockConfigTypeDef; 219 220 /** 221 * @brief TIM Clear Input Configuration Handle Structure definition 222 */ 223 typedef struct 224 { 225 uint32_t ClearInputState; /*!< TIM clear Input state 226 This parameter can be ENABLE or DISABLE */ 227 uint32_t ClearInputSource; /*!< TIM clear Input sources 228 This parameter can be a value of @ref TIM_ClearInput_Source */ 229 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 230 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 231 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 232 This parameter must be 0: When OCRef clear feature is used with ETR source, 233 ETR prescaler must be off */ 234 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 235 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 236 } TIM_ClearInputConfigTypeDef; 237 238 /** 239 * @brief TIM Master configuration Structure definition 240 * @note Advanced timers provide TRGO2 internal line which is redirected 241 * to the ADC 242 */ 243 typedef struct 244 { 245 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 246 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 247 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 248 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 249 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 250 This parameter can be a value of @ref TIM_Master_Slave_Mode 251 @note When the Master/slave mode is enabled, the effect of 252 an event on the trigger input (TRGI) is delayed to allow a 253 perfect synchronization between the current timer and its 254 slaves (through TRGO). It is not mandatory in case of timer 255 synchronization mode. */ 256 } TIM_MasterConfigTypeDef; 257 258 /** 259 * @brief TIM Slave configuration Structure definition 260 */ 261 typedef struct 262 { 263 uint32_t SlaveMode; /*!< Slave mode selection 264 This parameter can be a value of @ref TIM_Slave_Mode */ 265 uint32_t InputTrigger; /*!< Input Trigger source 266 This parameter can be a value of @ref TIM_Trigger_Selection */ 267 uint32_t TriggerPolarity; /*!< Input Trigger polarity 268 This parameter can be a value of @ref TIM_Trigger_Polarity */ 269 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 270 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 271 uint32_t TriggerFilter; /*!< Input trigger filter 272 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 273 274 } TIM_SlaveConfigTypeDef; 275 276 /** 277 * @brief TIM Break input(s) and Dead time configuration Structure definition 278 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 279 * filter and polarity. 280 */ 281 typedef struct 282 { 283 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 284 285 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 286 287 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 288 289 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 290 291 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 292 293 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 294 295 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 296 297 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 298 299 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 300 301 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 302 303 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 304 305 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ 306 307 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 308 309 } TIM_BreakDeadTimeConfigTypeDef; 310 311 /** 312 * @brief HAL State structures definition 313 */ 314 typedef enum 315 { 316 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 317 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 318 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 319 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 320 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 321 } HAL_TIM_StateTypeDef; 322 323 /** 324 * @brief TIM Channel States definition 325 */ 326 typedef enum 327 { 328 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 329 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 330 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 331 } HAL_TIM_ChannelStateTypeDef; 332 333 /** 334 * @brief DMA Burst States definition 335 */ 336 typedef enum 337 { 338 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 339 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 340 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 341 } HAL_TIM_DMABurstStateTypeDef; 342 343 /** 344 * @brief HAL Active channel structures definition 345 */ 346 typedef enum 347 { 348 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 349 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 350 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 351 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 352 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 353 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 354 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 355 } HAL_TIM_ActiveChannel; 356 357 /** 358 * @brief TIM Time Base Handle Structure definition 359 */ 360 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 361 typedef struct __TIM_HandleTypeDef 362 #else 363 typedef struct 364 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 365 { 366 TIM_TypeDef *Instance; /*!< Register base address */ 367 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 368 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 369 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 370 This array is accessed by a @ref DMA_Handle_index */ 371 HAL_LockTypeDef Lock; /*!< Locking object */ 372 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 373 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 374 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 375 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 376 377 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 378 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 379 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 380 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 381 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 382 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 383 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 384 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 385 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 386 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 387 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 388 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 389 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 390 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 391 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 392 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 393 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 394 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 395 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 396 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 397 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 398 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 399 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 400 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 401 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 402 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 403 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 404 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 405 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 406 void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ 407 void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ 408 void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ 409 void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ 410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 411 } TIM_HandleTypeDef; 412 413 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 414 /** 415 * @brief HAL TIM Callback ID enumeration definition 416 */ 417 typedef enum 418 { 419 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 420 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 421 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 422 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 423 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 424 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 425 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 426 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 427 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 428 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 429 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 430 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 431 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 432 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 433 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 434 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 435 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 436 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 437 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 438 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 439 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 440 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 441 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 442 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 443 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 444 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 445 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 446 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 447 , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ 448 , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ 449 , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ 450 , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ 451 } HAL_TIM_CallbackIDTypeDef; 452 453 /** 454 * @brief HAL TIM Callback pointer definition 455 */ 456 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 457 458 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 459 460 /** 461 * @} 462 */ 463 /* End of exported types -----------------------------------------------------*/ 464 465 /* Exported constants --------------------------------------------------------*/ 466 /** @defgroup TIM_Exported_Constants TIM Exported Constants 467 * @{ 468 */ 469 470 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 471 * @{ 472 */ 473 #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ 474 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 475 #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ 476 #if defined(COMP2) 477 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ 478 #endif /* COMP2 */ 479 /** 480 * @} 481 */ 482 483 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 484 * @{ 485 */ 486 #define TIM_DMABASE_CR1 0x00000000U 487 #define TIM_DMABASE_CR2 0x00000001U 488 #define TIM_DMABASE_SMCR 0x00000002U 489 #define TIM_DMABASE_DIER 0x00000003U 490 #define TIM_DMABASE_SR 0x00000004U 491 #define TIM_DMABASE_EGR 0x00000005U 492 #define TIM_DMABASE_CCMR1 0x00000006U 493 #define TIM_DMABASE_CCMR2 0x00000007U 494 #define TIM_DMABASE_CCER 0x00000008U 495 #define TIM_DMABASE_CNT 0x00000009U 496 #define TIM_DMABASE_PSC 0x0000000AU 497 #define TIM_DMABASE_ARR 0x0000000BU 498 #define TIM_DMABASE_RCR 0x0000000CU 499 #define TIM_DMABASE_CCR1 0x0000000DU 500 #define TIM_DMABASE_CCR2 0x0000000EU 501 #define TIM_DMABASE_CCR3 0x0000000FU 502 #define TIM_DMABASE_CCR4 0x00000010U 503 #define TIM_DMABASE_BDTR 0x00000011U 504 #define TIM_DMABASE_CCR5 0x00000012U 505 #define TIM_DMABASE_CCR6 0x00000013U 506 #define TIM_DMABASE_CCMR3 0x00000014U 507 #define TIM_DMABASE_DTR2 0x00000015U 508 #define TIM_DMABASE_ECR 0x00000016U 509 #define TIM_DMABASE_TISEL 0x00000017U 510 #define TIM_DMABASE_AF1 0x00000018U 511 #define TIM_DMABASE_AF2 0x00000019U 512 #define TIM_DMABASE_OR1 0x0000001AU 513 /** 514 * @} 515 */ 516 517 /** @defgroup TIM_Event_Source TIM Event Source 518 * @{ 519 */ 520 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 521 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 522 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 523 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 524 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 525 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 526 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 527 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 528 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 534 * @{ 535 */ 536 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 537 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 538 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 539 /** 540 * @} 541 */ 542 543 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 544 * @{ 545 */ 546 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 547 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 548 /** 549 * @} 550 */ 551 552 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 553 * @{ 554 */ 555 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 556 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 557 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 558 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup TIM_Counter_Mode TIM Counter Mode 564 * @{ 565 */ 566 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 567 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 568 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 569 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 570 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 571 /** 572 * @} 573 */ 574 575 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 576 * @{ 577 */ 578 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 579 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 580 /** 581 * @} 582 */ 583 584 /** @defgroup TIM_ClockDivision TIM Clock Division 585 * @{ 586 */ 587 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 588 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 589 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 595 * @{ 596 */ 597 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 598 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 604 * @{ 605 */ 606 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 607 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 608 609 /** 610 * @} 611 */ 612 613 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 614 * @{ 615 */ 616 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 617 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 618 /** 619 * @} 620 */ 621 622 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 623 * @{ 624 */ 625 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 626 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 627 /** 628 * @} 629 */ 630 631 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 632 * @{ 633 */ 634 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 635 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 641 * @{ 642 */ 643 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 644 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 650 * @{ 651 */ 652 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 653 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 654 /** 655 * @} 656 */ 657 658 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 659 * @{ 660 */ 661 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 662 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 663 /** 664 * @} 665 */ 666 667 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 668 * @{ 669 */ 670 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 671 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 672 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 673 /** 674 * @} 675 */ 676 677 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 678 * @{ 679 */ 680 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 681 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 682 /** 683 * @} 684 */ 685 686 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 687 * @{ 688 */ 689 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 690 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 691 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 697 * @{ 698 */ 699 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 700 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 701 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 702 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 703 /** 704 * @} 705 */ 706 707 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 708 * @{ 709 */ 710 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 711 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 712 /** 713 * @} 714 */ 715 716 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 717 * @{ 718 */ 719 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 720 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 721 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 722 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ 723 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ 724 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ 725 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ 726 #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ 727 #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ 728 /** 729 * @} 730 */ 731 732 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 733 * @{ 734 */ 735 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 736 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 737 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 738 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 739 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 740 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 741 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 742 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 743 #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ 744 #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ 745 #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ 746 #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ 747 /** 748 * @} 749 */ 750 751 /** @defgroup TIM_Commutation_Source TIM Commutation Source 752 * @{ 753 */ 754 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 755 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 756 /** 757 * @} 758 */ 759 760 /** @defgroup TIM_DMA_sources TIM DMA Sources 761 * @{ 762 */ 763 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 764 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 765 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 766 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 767 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 768 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 769 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 770 /** 771 * @} 772 */ 773 774 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 775 * @{ 776 */ 777 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 778 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 779 /** 780 * @} 781 */ 782 783 /** @defgroup TIM_Flag_definition TIM Flag Definition 784 * @{ 785 */ 786 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 787 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 788 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 789 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 790 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 791 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 792 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 793 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 794 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 795 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 796 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 797 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 798 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 799 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 800 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 801 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 802 #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ 803 #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ 804 #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ 805 #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ 806 /** 807 * @} 808 */ 809 810 /** @defgroup TIM_Channel TIM Channel 811 * @{ 812 */ 813 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 814 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 815 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 816 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 817 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 818 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 819 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 820 /** 821 * @} 822 */ 823 824 /** @defgroup TIM_Clock_Source TIM Clock Source 825 * @{ 826 */ 827 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 828 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 829 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 830 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 831 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 832 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 833 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 834 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 835 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 836 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 837 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ 838 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ 839 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ 840 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ 841 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ 842 #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ 843 /** 844 * @} 845 */ 846 847 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 848 * @{ 849 */ 850 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 851 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 852 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 853 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 854 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 855 /** 856 * @} 857 */ 858 859 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 860 * @{ 861 */ 862 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 863 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 864 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 865 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 866 /** 867 * @} 868 */ 869 870 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 871 * @{ 872 */ 873 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 874 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 875 /** 876 * @} 877 */ 878 879 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 880 * @{ 881 */ 882 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 883 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 884 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 885 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 886 /** 887 * @} 888 */ 889 890 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 891 * @{ 892 */ 893 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 894 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 895 /** 896 * @} 897 */ 898 899 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 900 * @{ 901 */ 902 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 903 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 904 /** 905 * @} 906 */ 907 /** @defgroup TIM_Lock_level TIM Lock level 908 * @{ 909 */ 910 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 911 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 912 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 913 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 914 /** 915 * @} 916 */ 917 918 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 919 * @{ 920 */ 921 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 922 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 923 /** 924 * @} 925 */ 926 927 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 928 * @{ 929 */ 930 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 931 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 932 /** 933 * @} 934 */ 935 936 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 937 * @{ 938 */ 939 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 940 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 941 /** 942 * @} 943 */ 944 945 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 946 * @{ 947 */ 948 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 949 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 950 /** 951 * @} 952 */ 953 954 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 955 * @{ 956 */ 957 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 958 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 959 /** 960 * @} 961 */ 962 963 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode 964 * @{ 965 */ 966 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 967 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 968 /** 969 * @} 970 */ 971 972 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 973 * @{ 974 */ 975 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 976 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 977 /** 978 * @} 979 */ 980 981 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 982 * @{ 983 */ 984 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 985 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 986 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 987 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 988 /** 989 * @} 990 */ 991 992 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 993 * @{ 994 */ 995 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 996 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 997 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 998 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 999 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 1000 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 1001 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 1002 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 1003 #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ 1004 /** 1005 * @} 1006 */ 1007 1008 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 1009 * @{ 1010 */ 1011 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 1012 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 1013 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 1014 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 1015 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 1016 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 1017 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 1018 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 1019 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 1020 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 1021 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 1022 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 1023 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 1024 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 1025 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1026 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 1032 * @{ 1033 */ 1034 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 1035 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 1036 /** 1037 * @} 1038 */ 1039 1040 /** @defgroup TIM_Slave_Mode TIM Slave mode 1041 * @{ 1042 */ 1043 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 1044 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 1045 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 1046 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 1047 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 1048 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 1049 #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 1055 * @{ 1056 */ 1057 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 1058 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 1059 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 1060 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 1061 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 1062 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 1063 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 1064 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 1065 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 1066 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 1067 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 1068 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 1069 #define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 1070 #define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 1071 #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ 1072 #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1078 * @{ 1079 */ 1080 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1081 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1082 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1083 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1084 #define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ 1085 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ 1086 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ 1087 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ 1088 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ 1089 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ 1090 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1091 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1092 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1093 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1094 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 1095 /** 1096 * @} 1097 */ 1098 1099 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1100 * @{ 1101 */ 1102 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1103 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1104 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1105 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1106 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1107 /** 1108 * @} 1109 */ 1110 1111 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1112 * @{ 1113 */ 1114 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1115 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1116 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1117 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1118 /** 1119 * @} 1120 */ 1121 1122 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1123 * @{ 1124 */ 1125 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1126 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1127 /** 1128 * @} 1129 */ 1130 1131 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1132 * @{ 1133 */ 1134 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1135 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1136 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1137 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1138 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1139 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1140 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1141 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1142 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1143 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1144 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1145 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1146 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1147 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1148 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1149 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1150 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1151 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1152 #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1153 #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1154 #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1155 #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1156 #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1157 #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1158 #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1159 #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1160 /** 1161 * @} 1162 */ 1163 1164 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1165 * @{ 1166 */ 1167 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1168 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1169 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1170 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1171 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1172 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1173 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1174 /** 1175 * @} 1176 */ 1177 1178 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1179 * @{ 1180 */ 1181 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1182 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1183 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1184 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1185 /** 1186 * @} 1187 */ 1188 1189 /** @defgroup TIM_Break_System TIM Break System 1190 * @{ 1191 */ 1192 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ 1193 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1194 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ 1195 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ 1196 /** 1197 * @} 1198 */ 1199 1200 /** 1201 * @} 1202 */ 1203 /* End of exported constants -------------------------------------------------*/ 1204 1205 /* Exported macros -----------------------------------------------------------*/ 1206 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1207 * @{ 1208 */ 1209 1210 /** @brief Reset TIM handle state. 1211 * @param __HANDLE__ TIM handle. 1212 * @retval None 1213 */ 1214 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1215 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1216 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1217 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1218 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1219 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1220 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1221 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1222 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1223 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1224 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1225 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1226 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1227 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1228 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1229 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1230 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1231 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1232 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1233 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1234 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1235 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1236 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1237 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1238 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1239 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1240 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1241 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1242 } while(0) 1243 #else 1244 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1245 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1246 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1247 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1248 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1249 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1250 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1251 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1252 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1253 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1254 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1255 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1256 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1257 } while(0) 1258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1259 1260 /** 1261 * @brief Enable the TIM peripheral. 1262 * @param __HANDLE__ TIM handle 1263 * @retval None 1264 */ 1265 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1266 1267 /** 1268 * @brief Enable the TIM main Output. 1269 * @param __HANDLE__ TIM handle 1270 * @retval None 1271 */ 1272 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1273 1274 /** 1275 * @brief Disable the TIM peripheral. 1276 * @param __HANDLE__ TIM handle 1277 * @retval None 1278 */ 1279 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1280 do { \ 1281 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1282 { \ 1283 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1284 { \ 1285 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1286 } \ 1287 } \ 1288 } while(0) 1289 1290 /** 1291 * @brief Disable the TIM main Output. 1292 * @param __HANDLE__ TIM handle 1293 * @retval None 1294 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1295 * disabled 1296 */ 1297 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1298 do { \ 1299 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1300 { \ 1301 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1302 { \ 1303 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1304 } \ 1305 } \ 1306 } while(0) 1307 1308 /** 1309 * @brief Disable the TIM main Output. 1310 * @param __HANDLE__ TIM handle 1311 * @retval None 1312 * @note The Main Output Enable of a timer instance is disabled unconditionally 1313 */ 1314 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1315 1316 /** @brief Enable the specified TIM interrupt. 1317 * @param __HANDLE__ specifies the TIM Handle. 1318 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1319 * This parameter can be one of the following values: 1320 * @arg TIM_IT_UPDATE: Update interrupt 1321 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1322 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1323 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1324 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1325 * @arg TIM_IT_COM: Commutation interrupt 1326 * @arg TIM_IT_TRIGGER: Trigger interrupt 1327 * @arg TIM_IT_BREAK: Break interrupt 1328 * @arg TIM_IT_IDX: Index interrupt 1329 * @arg TIM_IT_DIR: Direction change interrupt 1330 * @arg TIM_IT_IERR: Index error interrupt 1331 * @arg TIM_IT_TERR: Transition error interrupt 1332 * @retval None 1333 */ 1334 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1335 1336 /** @brief Disable the specified TIM interrupt. 1337 * @param __HANDLE__ specifies the TIM Handle. 1338 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1339 * This parameter can be one of the following values: 1340 * @arg TIM_IT_UPDATE: Update interrupt 1341 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1342 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1343 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1344 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1345 * @arg TIM_IT_COM: Commutation interrupt 1346 * @arg TIM_IT_TRIGGER: Trigger interrupt 1347 * @arg TIM_IT_BREAK: Break interrupt 1348 * @arg TIM_IT_IDX: Index interrupt 1349 * @arg TIM_IT_DIR: Direction change interrupt 1350 * @arg TIM_IT_IERR: Index error interrupt 1351 * @arg TIM_IT_TERR: Transition error interrupt 1352 * @retval None 1353 */ 1354 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1355 1356 /** @brief Enable the specified DMA request. 1357 * @param __HANDLE__ specifies the TIM Handle. 1358 * @param __DMA__ specifies the TIM DMA request to enable. 1359 * This parameter can be one of the following values: 1360 * @arg TIM_DMA_UPDATE: Update DMA request 1361 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1362 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1363 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1364 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1365 * @arg TIM_DMA_COM: Commutation DMA request 1366 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1367 * @retval None 1368 */ 1369 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1370 1371 /** @brief Disable the specified DMA request. 1372 * @param __HANDLE__ specifies the TIM Handle. 1373 * @param __DMA__ specifies the TIM DMA request to disable. 1374 * This parameter can be one of the following values: 1375 * @arg TIM_DMA_UPDATE: Update DMA request 1376 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1377 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1378 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1379 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1380 * @arg TIM_DMA_COM: Commutation DMA request 1381 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1382 * @retval None 1383 */ 1384 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1385 1386 /** @brief Check whether the specified TIM interrupt flag is set or not. 1387 * @param __HANDLE__ specifies the TIM Handle. 1388 * @param __FLAG__ specifies the TIM interrupt flag to check. 1389 * This parameter can be one of the following values: 1390 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1391 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1392 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1393 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1394 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1395 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1396 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1397 * @arg TIM_FLAG_COM: Commutation interrupt flag 1398 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1399 * @arg TIM_FLAG_BREAK: Break interrupt flag 1400 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1401 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1402 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1403 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1404 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1405 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1406 * @arg TIM_FLAG_IDX: Index interrupt flag 1407 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1408 * @arg TIM_FLAG_IERR: Index error interrupt flag 1409 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1410 * @retval The new state of __FLAG__ (TRUE or FALSE). 1411 */ 1412 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1413 1414 /** @brief Clear the specified TIM interrupt flag. 1415 * @param __HANDLE__ specifies the TIM Handle. 1416 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1417 * This parameter can be one of the following values: 1418 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1419 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1420 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1421 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1422 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1423 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1424 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1425 * @arg TIM_FLAG_COM: Commutation interrupt flag 1426 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1427 * @arg TIM_FLAG_BREAK: Break interrupt flag 1428 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1429 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1430 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1431 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1432 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1433 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1434 * @arg TIM_FLAG_IDX: Index interrupt flag 1435 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1436 * @arg TIM_FLAG_IERR: Index error interrupt flag 1437 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1438 * @retval The new state of __FLAG__ (TRUE or FALSE). 1439 */ 1440 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1441 1442 /** 1443 * @brief Check whether the specified TIM interrupt source is enabled or not. 1444 * @param __HANDLE__ TIM handle 1445 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1446 * This parameter can be one of the following values: 1447 * @arg TIM_IT_UPDATE: Update interrupt 1448 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1449 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1450 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1451 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1452 * @arg TIM_IT_COM: Commutation interrupt 1453 * @arg TIM_IT_TRIGGER: Trigger interrupt 1454 * @arg TIM_IT_BREAK: Break interrupt 1455 * @arg TIM_IT_IDX: Index interrupt 1456 * @arg TIM_IT_DIR: Direction change interrupt 1457 * @arg TIM_IT_IERR: Index error interrupt 1458 * @arg TIM_IT_TERR: Transition error interrupt 1459 * @retval The state of TIM_IT (SET or RESET). 1460 */ 1461 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1462 == (__INTERRUPT__)) ? SET : RESET) 1463 1464 /** @brief Clear the TIM interrupt pending bits. 1465 * @param __HANDLE__ TIM handle 1466 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1467 * This parameter can be one of the following values: 1468 * @arg TIM_IT_UPDATE: Update interrupt 1469 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1470 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1471 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1472 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1473 * @arg TIM_IT_COM: Commutation interrupt 1474 * @arg TIM_IT_TRIGGER: Trigger interrupt 1475 * @arg TIM_IT_BREAK: Break interrupt 1476 * @arg TIM_IT_IDX: Index interrupt 1477 * @arg TIM_IT_DIR: Direction change interrupt 1478 * @arg TIM_IT_IERR: Index error interrupt 1479 * @arg TIM_IT_TERR: Transition error interrupt 1480 * @retval None 1481 */ 1482 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1483 1484 /** 1485 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1486 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1487 * in an atomic way. 1488 * @param __HANDLE__ TIM handle. 1489 * @retval None 1490 mode. 1491 */ 1492 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1493 1494 /** 1495 * @brief Disable update interrupt flag (UIF) remapping. 1496 * @param __HANDLE__ TIM handle. 1497 * @retval None 1498 mode. 1499 */ 1500 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1501 1502 /** 1503 * @brief Get update interrupt flag (UIF) copy status. 1504 * @param __COUNTER__ Counter value. 1505 * @retval The state of UIFCPY (TRUE or FALSE). 1506 mode. 1507 */ 1508 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1509 1510 /** 1511 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1512 * @param __HANDLE__ TIM handle. 1513 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1514 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1515 * or Encoder mode. 1516 */ 1517 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1518 1519 /** 1520 * @brief Set the TIM Prescaler on runtime. 1521 * @param __HANDLE__ TIM handle. 1522 * @param __PRESC__ specifies the Prescaler new value. 1523 * @retval None 1524 */ 1525 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1526 1527 /** 1528 * @brief Set the TIM Counter Register value on runtime. 1529 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 1530 * case of 32 bits counter TIM instance. 1531 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1532 * @param __HANDLE__ TIM handle. 1533 * @param __COUNTER__ specifies the Counter register new value. 1534 * @retval None 1535 */ 1536 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1537 1538 /** 1539 * @brief Get the TIM Counter Register value on runtime. 1540 * @param __HANDLE__ TIM handle. 1541 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1542 */ 1543 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1544 1545 /** 1546 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1547 * @param __HANDLE__ TIM handle. 1548 * @param __AUTORELOAD__ specifies the Counter register new value. 1549 * @retval None 1550 */ 1551 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1552 do{ \ 1553 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1554 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1555 } while(0) 1556 1557 /** 1558 * @brief Get the TIM Autoreload Register value on runtime. 1559 * @param __HANDLE__ TIM handle. 1560 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1561 */ 1562 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1563 1564 /** 1565 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1566 * @param __HANDLE__ TIM handle. 1567 * @param __CKD__ specifies the clock division value. 1568 * This parameter can be one of the following value: 1569 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1570 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1571 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1572 * @retval None 1573 */ 1574 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1575 do{ \ 1576 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1577 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1578 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1579 } while(0) 1580 1581 /** 1582 * @brief Get the TIM Clock Division value on runtime. 1583 * @param __HANDLE__ TIM handle. 1584 * @retval The clock division can be one of the following values: 1585 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1586 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1587 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1588 */ 1589 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1590 1591 /** 1592 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1593 * function. 1594 * @param __HANDLE__ TIM handle. 1595 * @param __CHANNEL__ TIM Channels to be configured. 1596 * This parameter can be one of the following values: 1597 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1598 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1599 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1600 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1601 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1602 * This parameter can be one of the following values: 1603 * @arg TIM_ICPSC_DIV1: no prescaler 1604 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1605 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1606 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1607 * @retval None 1608 */ 1609 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1610 do{ \ 1611 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1612 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1613 } while(0) 1614 1615 /** 1616 * @brief Get the TIM Input Capture prescaler on runtime. 1617 * @param __HANDLE__ TIM handle. 1618 * @param __CHANNEL__ TIM Channels to be configured. 1619 * This parameter can be one of the following values: 1620 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1621 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1622 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1623 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1624 * @retval The input capture prescaler can be one of the following values: 1625 * @arg TIM_ICPSC_DIV1: no prescaler 1626 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1627 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1628 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1629 */ 1630 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1631 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1632 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1633 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1634 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1635 1636 /** 1637 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1638 * @param __HANDLE__ TIM handle. 1639 * @param __CHANNEL__ TIM Channels to be configured. 1640 * This parameter can be one of the following values: 1641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1645 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1646 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1647 * @param __COMPARE__ specifies the Capture Compare register new value. 1648 * @retval None 1649 */ 1650 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1651 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1652 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1653 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1654 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1655 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1656 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1657 1658 /** 1659 * @brief Get the TIM Capture Compare Register value on runtime. 1660 * @param __HANDLE__ TIM handle. 1661 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1662 * This parameter can be one of the following values: 1663 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1664 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1665 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1666 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1667 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1668 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1669 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1670 */ 1671 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1672 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1673 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1674 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1675 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1676 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1677 ((__HANDLE__)->Instance->CCR6)) 1678 1679 /** 1680 * @brief Set the TIM Output compare preload. 1681 * @param __HANDLE__ TIM handle. 1682 * @param __CHANNEL__ TIM Channels to be configured. 1683 * This parameter can be one of the following values: 1684 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1685 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1686 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1687 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1688 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1689 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1690 * @retval None 1691 */ 1692 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1693 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1694 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1695 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1696 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1697 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1698 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1699 1700 /** 1701 * @brief Reset the TIM Output compare preload. 1702 * @param __HANDLE__ TIM handle. 1703 * @param __CHANNEL__ TIM Channels to be configured. 1704 * This parameter can be one of the following values: 1705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1709 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1710 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1711 * @retval None 1712 */ 1713 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1714 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1715 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1716 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1717 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1718 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1719 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1720 1721 /** 1722 * @brief Enable fast mode for a given channel. 1723 * @param __HANDLE__ TIM handle. 1724 * @param __CHANNEL__ TIM Channels to be configured. 1725 * This parameter can be one of the following values: 1726 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1727 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1728 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1729 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1730 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1731 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1732 * @note When fast mode is enabled an active edge on the trigger input acts 1733 * like a compare match on CCx output. Delay to sample the trigger 1734 * input and to activate CCx output is reduced to 3 clock cycles. 1735 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1736 * @retval None 1737 */ 1738 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1739 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1740 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1741 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1742 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1743 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1744 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1745 1746 /** 1747 * @brief Disable fast mode for a given channel. 1748 * @param __HANDLE__ TIM handle. 1749 * @param __CHANNEL__ TIM Channels to be configured. 1750 * This parameter can be one of the following values: 1751 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1752 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1753 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1754 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1755 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1756 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1757 * @note When fast mode is disabled CCx output behaves normally depending 1758 * on counter and CCRx values even when the trigger is ON. The minimum 1759 * delay to activate CCx output when an active edge occurs on the 1760 * trigger input is 5 clock cycles. 1761 * @retval None 1762 */ 1763 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1764 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1765 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1766 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1767 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1768 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1769 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1770 1771 /** 1772 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1773 * @param __HANDLE__ TIM handle. 1774 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1775 * overflow/underflow generates an update interrupt or DMA request (if 1776 * enabled) 1777 * @retval None 1778 */ 1779 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1780 1781 /** 1782 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1783 * @param __HANDLE__ TIM handle. 1784 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1785 * following events generate an update interrupt or DMA request (if 1786 * enabled): 1787 * _ Counter overflow underflow 1788 * _ Setting the UG bit 1789 * _ Update generation through the slave mode controller 1790 * @retval None 1791 */ 1792 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1793 1794 /** 1795 * @brief Set the TIM Capture x input polarity on runtime. 1796 * @param __HANDLE__ TIM handle. 1797 * @param __CHANNEL__ TIM Channels to be configured. 1798 * This parameter can be one of the following values: 1799 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1800 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1801 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1802 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1803 * @param __POLARITY__ Polarity for TIx source 1804 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1805 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1806 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1807 * @retval None 1808 */ 1809 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1810 do{ \ 1811 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1812 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1813 }while(0) 1814 1815 /** @brief Select the Capture/compare DMA request source. 1816 * @param __HANDLE__ specifies the TIM Handle. 1817 * @param __CCDMA__ specifies Capture/compare DMA request source 1818 * This parameter can be one of the following values: 1819 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1820 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1821 * @retval None 1822 */ 1823 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1824 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1825 1826 /** 1827 * @} 1828 */ 1829 /* End of exported macros ----------------------------------------------------*/ 1830 1831 /* Private constants ---------------------------------------------------------*/ 1832 /** @defgroup TIM_Private_Constants TIM Private Constants 1833 * @{ 1834 */ 1835 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1836 channels have been disabled */ 1837 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1838 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) 1839 /** 1840 * @} 1841 */ 1842 /* End of private constants --------------------------------------------------*/ 1843 1844 /* Private macros ------------------------------------------------------------*/ 1845 /** @defgroup TIM_Private_Macros TIM Private Macros 1846 * @{ 1847 */ 1848 #if defined(COMP2) 1849 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1850 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1851 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ 1852 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1853 #else 1854 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1855 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1856 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1857 #endif /* COMP2 */ 1858 1859 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1860 ((__BASE__) == TIM_DMABASE_CR2) || \ 1861 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1862 ((__BASE__) == TIM_DMABASE_DIER) || \ 1863 ((__BASE__) == TIM_DMABASE_SR) || \ 1864 ((__BASE__) == TIM_DMABASE_EGR) || \ 1865 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1866 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1867 ((__BASE__) == TIM_DMABASE_CCER) || \ 1868 ((__BASE__) == TIM_DMABASE_CNT) || \ 1869 ((__BASE__) == TIM_DMABASE_PSC) || \ 1870 ((__BASE__) == TIM_DMABASE_ARR) || \ 1871 ((__BASE__) == TIM_DMABASE_RCR) || \ 1872 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1873 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1874 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1875 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1876 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1877 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1878 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1879 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1880 ((__BASE__) == TIM_DMABASE_AF1) || \ 1881 ((__BASE__) == TIM_DMABASE_AF2) || \ 1882 ((__BASE__) == TIM_DMABASE_TISEL) || \ 1883 ((__BASE__) == TIM_DMABASE_DTR2) || \ 1884 ((__BASE__) == TIM_DMABASE_ECR) || \ 1885 ((__BASE__) == TIM_DMABASE_OR1)) 1886 1887 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1888 1889 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1890 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1891 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1892 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1893 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1894 1895 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1896 ((__MODE__) == TIM_UIFREMAP_ENABLE)) 1897 1898 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1899 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1900 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1901 1902 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1903 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1904 1905 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1906 ((__STATE__) == TIM_OCFAST_ENABLE)) 1907 1908 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1909 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1910 1911 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1912 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1913 1914 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1915 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1916 1917 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1918 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1919 1920 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1921 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1922 1923 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1924 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1925 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1926 1927 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1928 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1929 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1930 1931 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1932 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1933 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1934 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1935 1936 #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ 1937 ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ 1938 ((__CHANNEL__) != (TIM_CHANNEL_6))) 1939 1940 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1941 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1942 1943 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1944 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1945 ((__MODE__) == TIM_ENCODERMODE_TI12) || \ 1946 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ 1947 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ 1948 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ 1949 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ 1950 ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ 1951 ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) 1952 1953 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1954 1955 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1956 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1957 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1958 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1959 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1960 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1961 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1962 1963 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1964 ((__CHANNEL__) == TIM_CHANNEL_2)) 1965 1966 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ 1967 ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ 1968 (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ 1969 (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ 1970 ((__PERIOD__) > 0U )) 1971 1972 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1973 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1974 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1975 ((__CHANNEL__) == TIM_CHANNEL_4)) 1976 1977 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1978 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1979 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1980 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1981 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1982 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1983 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1984 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1985 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1986 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1987 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 1988 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 1989 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 1990 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 1991 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 1992 1993 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1994 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1995 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1996 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1997 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1998 1999 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 2000 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 2001 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 2002 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 2003 2004 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2005 2006 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 2007 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 2008 2009 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 2010 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 2011 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 2012 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 2013 2014 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2015 2016 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 2017 ((__STATE__) == TIM_OSSR_DISABLE)) 2018 2019 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 2020 ((__STATE__) == TIM_OSSI_DISABLE)) 2021 2022 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 2023 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 2024 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 2025 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 2026 2027 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 2028 2029 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 2030 ((__STATE__) == TIM_BREAK_DISABLE)) 2031 2032 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 2033 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 2034 2035 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 2036 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 2037 2038 2039 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 2040 ((__STATE__) == TIM_BREAK2_DISABLE)) 2041 2042 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 2043 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 2044 2045 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ 2046 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) 2047 2048 2049 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 2050 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 2051 2052 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 2053 2054 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 2055 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 2056 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 2057 ((__SOURCE__) == TIM_TRGO_OC1) || \ 2058 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 2059 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 2060 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 2061 ((__SOURCE__) == TIM_TRGO_OC4REF) || \ 2062 ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) 2063 2064 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 2065 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 2066 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 2067 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 2068 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 2069 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 2070 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2071 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2072 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 2073 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 2074 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 2075 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 2076 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 2077 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 2078 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 2079 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 2080 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 2081 2082 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 2083 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 2084 2085 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2086 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2087 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2088 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2089 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 2090 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ 2091 ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) 2092 2093 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2094 ((__MODE__) == TIM_OCMODE_PWM2) || \ 2095 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 2096 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 2097 ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ 2098 ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) 2099 2100 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2101 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2102 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2103 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2104 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2105 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 2106 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 2107 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ 2108 ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ 2109 ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) 2110 2111 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2112 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2113 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2114 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2115 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2116 2117 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2118 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2119 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2120 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2121 2122 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2123 2124 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2125 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2126 2127 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2128 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2129 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2130 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2131 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2132 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2133 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2134 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2135 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2136 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2137 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2138 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2139 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2140 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2141 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2142 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2143 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2144 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ 2145 ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ 2146 ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ 2147 ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ 2148 ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ 2149 ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ 2150 ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ 2151 ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ 2152 ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) 2153 2154 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2155 2156 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2157 2158 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2159 2160 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 2161 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 2162 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ 2163 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 2164 2165 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2166 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2167 2168 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2169 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2170 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2171 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2172 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2173 2174 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2175 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2176 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2177 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2178 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2179 2180 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2181 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2182 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2183 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2184 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2185 2186 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2187 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2188 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2189 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2190 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2191 2192 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2193 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2194 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2195 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2196 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2197 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2198 (__HANDLE__)->ChannelState[5]) 2199 2200 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2201 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2202 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2203 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2204 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2205 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2206 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2207 2208 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2209 (__HANDLE__)->ChannelState[0] = \ 2210 (__CHANNEL_STATE__); \ 2211 (__HANDLE__)->ChannelState[1] = \ 2212 (__CHANNEL_STATE__); \ 2213 (__HANDLE__)->ChannelState[2] = \ 2214 (__CHANNEL_STATE__); \ 2215 (__HANDLE__)->ChannelState[3] = \ 2216 (__CHANNEL_STATE__); \ 2217 (__HANDLE__)->ChannelState[4] = \ 2218 (__CHANNEL_STATE__); \ 2219 (__HANDLE__)->ChannelState[5] = \ 2220 (__CHANNEL_STATE__); \ 2221 } while(0) 2222 2223 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2224 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2225 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2226 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2227 (__HANDLE__)->ChannelNState[3]) 2228 2229 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2230 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2231 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2232 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2233 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2234 2235 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2236 (__HANDLE__)->ChannelNState[0] = \ 2237 (__CHANNEL_STATE__); \ 2238 (__HANDLE__)->ChannelNState[1] = \ 2239 (__CHANNEL_STATE__); \ 2240 (__HANDLE__)->ChannelNState[2] = \ 2241 (__CHANNEL_STATE__); \ 2242 (__HANDLE__)->ChannelNState[3] = \ 2243 (__CHANNEL_STATE__); \ 2244 } while(0) 2245 2246 /** 2247 * @} 2248 */ 2249 /* End of private macros -----------------------------------------------------*/ 2250 2251 /* Include TIM HAL Extended module */ 2252 #include "stm32u5xx_hal_tim_ex.h" 2253 2254 /* Exported functions --------------------------------------------------------*/ 2255 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2256 * @{ 2257 */ 2258 2259 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2260 * @brief Time Base functions 2261 * @{ 2262 */ 2263 /* Time Base functions ********************************************************/ 2264 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2265 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2266 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2267 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2268 /* Blocking mode: Polling */ 2269 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2270 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2271 /* Non-Blocking mode: Interrupt */ 2272 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2273 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2274 /* Non-Blocking mode: DMA */ 2275 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); 2276 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2277 /** 2278 * @} 2279 */ 2280 2281 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2282 * @brief TIM Output Compare functions 2283 * @{ 2284 */ 2285 /* Timer Output Compare functions *********************************************/ 2286 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2287 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2288 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2289 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2290 /* Blocking mode: Polling */ 2291 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2292 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2293 /* Non-Blocking mode: Interrupt */ 2294 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2295 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2296 /* Non-Blocking mode: DMA */ 2297 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2298 uint16_t Length); 2299 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2300 /** 2301 * @} 2302 */ 2303 2304 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2305 * @brief TIM PWM functions 2306 * @{ 2307 */ 2308 /* Timer PWM functions ********************************************************/ 2309 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2310 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2311 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2312 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2313 /* Blocking mode: Polling */ 2314 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2315 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2316 /* Non-Blocking mode: Interrupt */ 2317 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2318 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2319 /* Non-Blocking mode: DMA */ 2320 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2321 uint16_t Length); 2322 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2323 /** 2324 * @} 2325 */ 2326 2327 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2328 * @brief TIM Input Capture functions 2329 * @{ 2330 */ 2331 /* Timer Input Capture functions **********************************************/ 2332 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2333 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2334 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2335 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2336 /* Blocking mode: Polling */ 2337 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2338 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2339 /* Non-Blocking mode: Interrupt */ 2340 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2341 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2342 /* Non-Blocking mode: DMA */ 2343 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2344 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2345 /** 2346 * @} 2347 */ 2348 2349 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2350 * @brief TIM One Pulse functions 2351 * @{ 2352 */ 2353 /* Timer One Pulse functions **************************************************/ 2354 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2355 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2356 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2357 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2358 /* Blocking mode: Polling */ 2359 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2360 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2361 /* Non-Blocking mode: Interrupt */ 2362 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2363 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2364 /** 2365 * @} 2366 */ 2367 2368 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2369 * @brief TIM Encoder functions 2370 * @{ 2371 */ 2372 /* Timer Encoder functions ****************************************************/ 2373 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); 2374 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2375 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2376 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2377 /* Blocking mode: Polling */ 2378 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2379 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2380 /* Non-Blocking mode: Interrupt */ 2381 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2382 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2383 /* Non-Blocking mode: DMA */ 2384 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2385 uint32_t *pData2, uint16_t Length); 2386 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2387 /** 2388 * @} 2389 */ 2390 2391 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2392 * @brief IRQ handler management 2393 * @{ 2394 */ 2395 /* Interrupt Handler functions ***********************************************/ 2396 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2397 /** 2398 * @} 2399 */ 2400 2401 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2402 * @brief Peripheral Control functions 2403 * @{ 2404 */ 2405 /* Control functions *********************************************************/ 2406 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2407 uint32_t Channel); 2408 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2409 uint32_t Channel); 2410 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, 2411 uint32_t Channel); 2412 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2413 uint32_t OutputChannel, uint32_t InputChannel); 2414 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 2415 const TIM_ClearInputConfigTypeDef *sClearInputConfig, 2416 uint32_t Channel); 2417 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); 2418 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2419 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2420 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2421 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2422 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 2423 uint32_t BurstLength); 2424 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2425 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 2426 uint32_t BurstLength, uint32_t DataLength); 2427 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2428 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2429 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2430 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2431 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2432 uint32_t BurstLength, uint32_t DataLength); 2433 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2434 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2435 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); 2436 /** 2437 * @} 2438 */ 2439 2440 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2441 * @brief TIM Callbacks functions 2442 * @{ 2443 */ 2444 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2445 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2446 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2447 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2448 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2449 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2450 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2451 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2452 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2453 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2454 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2455 2456 /* Callbacks Register/UnRegister functions ***********************************/ 2457 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2458 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2459 pTIM_CallbackTypeDef pCallback); 2460 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2461 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2462 2463 /** 2464 * @} 2465 */ 2466 2467 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2468 * @brief Peripheral State functions 2469 * @{ 2470 */ 2471 /* Peripheral State functions ************************************************/ 2472 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); 2473 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); 2474 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); 2475 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); 2476 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); 2477 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); 2478 2479 /* Peripheral Channel state functions ************************************************/ 2480 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); 2481 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); 2482 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); 2483 /** 2484 * @} 2485 */ 2486 2487 /** 2488 * @} 2489 */ 2490 /* End of exported functions -------------------------------------------------*/ 2491 2492 /* Private functions----------------------------------------------------------*/ 2493 /** @defgroup TIM_Private_Functions TIM Private Functions 2494 * @{ 2495 */ 2496 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); 2497 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2498 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); 2499 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2500 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2501 2502 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2503 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2504 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2505 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2506 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2507 HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, 2508 uint32_t length); 2509 2510 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2511 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2512 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2513 2514 /** 2515 * @} 2516 */ 2517 /* End of private functions --------------------------------------------------*/ 2518 2519 /** 2520 * @} 2521 */ 2522 2523 /** 2524 * @} 2525 */ 2526 2527 #ifdef __cplusplus 2528 } 2529 #endif 2530 2531 #endif /* STM32U5xx_HAL_TIM_H */ 2532
