1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_ramcfg.h 4 * @author MCD Application Team 5 * @brief Header file of RAMCFG HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_RAMCFG_H 21 #define STM32U5xx_HAL_RAMCFG_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RAMCFG 35 * @{ 36 */ 37 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup RAMCFG_Exported_Types RAMCFG Exported Types 42 * @brief RAMCFG Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL RAMCFG State Enumeration Definition 48 */ 49 typedef enum 50 { 51 HAL_RAMCFG_STATE_RESET = 0x00U, /*!< RAMCFG not yet initialized or disabled */ 52 HAL_RAMCFG_STATE_READY = 0x01U, /*!< RAMCFG initialized and ready for use */ 53 HAL_RAMCFG_STATE_BUSY = 0x02U, /*!< RAMCFG process is ongoing */ 54 HAL_RAMCFG_STATE_ERROR = 0x03U, /*!< RAMCFG error state */ 55 } HAL_RAMCFG_StateTypeDef; 56 57 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 58 /** 59 * @brief HAL RAMCFG Callbacks IDs Enumeration Definition 60 */ 61 typedef enum 62 { 63 HAL_RAMCFG_MSPINIT_CB_ID = 0x00U, /*!< RAMCFG MSP Init Callback ID */ 64 HAL_RAMCFG_MSPDEINIT_CB_ID = 0x01U, /*!< RAMCFG MSP DeInit Callback ID */ 65 HAL_RAMCFG_SE_DETECT_CB_ID = 0x02U, /*!< RAMCFG Single Error Detect Callback ID */ 66 HAL_RAMCFG_DE_DETECT_CB_ID = 0x03U, /*!< RAMCFG Double Error Detect Callback ID */ 67 HAL_RAMCFG_ALL_CB_ID = 0x04U, /*!< RAMCFG All callback ID */ 68 } HAL_RAMCFG_CallbackIDTypeDef; 69 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 70 71 /** 72 * @brief RAMCFG Handle Structure Definition 73 */ 74 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 75 typedef struct __RAMCFG_HandleTypeDef 76 #else 77 typedef struct 78 #endif /* (USE_HAL_RAMCFG_REGISTER_CALLBACKS) */ 79 { 80 RAMCFG_TypeDef *Instance; /*!< RAMCFG Register Base Address */ 81 __IO HAL_RAMCFG_StateTypeDef State; /*!< RAMCFG State */ 82 __IO uint32_t ErrorCode; /*!< RAMCFG Error Code */ 83 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 84 void (* MspInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP Init Callback */ 85 void (* MspDeInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP DeInit Callback */ 86 void (* DetectSingleErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);/*!< RAMCFG Single Error Detect Callback */ 87 void (* DetectDoubleErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);/*!< RAMCFG Double Error Detect Callback */ 88 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 89 } RAMCFG_HandleTypeDef; 90 91 /** 92 * @} 93 */ 94 95 96 /* Exported constants --------------------------------------------------------*/ 97 98 /** @defgroup RAMCFG_Exported_Constants RAMCFG Exported Constants 99 * @brief RAMCFG Exported Constants 100 * @{ 101 */ 102 103 /** @defgroup RAMCFG_Error_Codes RAMCFG Error Codes 104 * @brief RAMCFG Error Codes 105 * @{ 106 */ 107 #define HAL_RAMCFG_ERROR_NONE 0x00000000U /*!< RAMCFG No Error */ 108 #define HAL_RAMCFG_ERROR_TIMEOUT 0x00000001U /*!< RAMCFG Timeout Error */ 109 #define HAL_RAMCFG_ERROR_BUSY 0x00000002U /*!< RAMCFG Busy Error */ 110 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 111 #define HAL_RAMCFG_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */ 112 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 113 /** 114 * @} 115 */ 116 117 /** @defgroup RAMCFG_Interrupt RAMCFG Interrupts 118 * @brief RAMCFG Interrupts 119 * @{ 120 */ 121 #define RAMCFG_IT_SINGLEERR RAMCFG_IER_SEIE /*!< RAMCFG Single Error Interrupt */ 122 #define RAMCFG_IT_DOUBLEERR RAMCFG_IER_DEIE /*!< RAMCFG Double Error Interrupt */ 123 #define RAMCFG_IT_NMIERR RAMCFG_IER_ECCNMI /*!< RAMCFG Double Error redirected to NMI Interrupt */ 124 #define RAMCFG_IT_ALL \ 125 (RAMCFG_IER_SEIE | RAMCFG_IER_DEIE |RAMCFG_IER_ECCNMI) /*!< RAMCFG All RAMCFG interrupt */ 126 /** 127 * @} 128 */ 129 130 /** @defgroup RAMCFG_FLAG RAMCFG Monitor Flags 131 * @brief RAMCFG Monitor Flags 132 * @{ 133 */ 134 #define RAMCFG_FLAG_SINGLEERR RAMCFG_ISR_SEDC /*!< RAMCFG Single Error Detected and Corrected Flag */ 135 #define RAMCFG_FLAG_DOUBLEERR RAMCFG_ISR_DED /*!< RAMCFG Double Error Detected Flag */ 136 #define RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /*!< RAMCFG SRAM busy Flag */ 137 #define RAMCFG_FLAGS_ALL \ 138 (RAMCFG_ISR_SEDC | RAMCFG_ISR_DED | RAMCFG_ISR_SRAMBUSY) /*!< RAMCFG All Flags */ 139 /** 140 * @} 141 */ 142 143 /** @defgroup RAMCFG_WaitState RAMCFG Wait State 144 * @brief RAMCFG Wait State 145 * @{ 146 */ 147 #define RAMCFG_WAITSTATE_0 (0U) /*!< RAMCFG 0 Wait State */ 148 #define RAMCFG_WAITSTATE_1 (RAMCFG_CR_WSC_0) /*!< RAMCFG 1 Wait State */ 149 #define RAMCFG_WAITSTATE_2 (RAMCFG_CR_WSC_1) /*!< RAMCFG 2 Wait State */ 150 #define RAMCFG_WAITSTATE_3 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1) /*!< RAMCFG 3 Wait State */ 151 #define RAMCFG_WAITSTATE_4 (RAMCFG_CR_WSC_2) /*!< RAMCFG 4 Wait State */ 152 #define RAMCFG_WAITSTATE_5 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_2) /*!< RAMCFG 5 Wait State */ 153 #define RAMCFG_WAITSTATE_6 (RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 6 Wait State */ 154 #define RAMCFG_WAITSTATE_7 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 7 Wait State */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup RAMCFG_Keys RAMCFG Keys 160 * @brief RAMCFG Keys 161 * @{ 162 */ 163 #define RAMCFG_ERASE_KEY1 (0xCAU) /*!< RAMCFG launch Erase Key 1 */ 164 #define RAMCFG_ERASE_KEY2 (0x53U) /*!< RAMCFG launch Erase Key 2 */ 165 166 #define RAMCFG_ECC_KEY1 (0xAEU) /*!< RAMCFG launch ECC Key 1 */ 167 #define RAMCFG_ECC_KEY2 (0x75U) /*!< RAMCFG launch ECC Key 2 */ 168 /** 169 * @} 170 */ 171 172 173 /** 174 * @} 175 */ 176 177 178 /* Exported macro ------------------------------------------------------------*/ 179 180 /** @defgroup RAMCFG_Exported_Macros RAMCFG Exported Macros 181 * @brief RAMCFG Exported Macros 182 * @{ 183 */ 184 185 /** 186 * @brief Enable the specified RAMCFG interrupts. 187 * @param __HANDLE__ : Specifies RAMCFG handle. 188 * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be enabled. 189 * This parameter can be one of the following values: 190 * @arg RAMCFG_IT_SINGLEERR : Single Error Interrupt Mask. 191 * @arg RAMCFG_IT_DOUBLEERR : Double Error Interrupt Mask. 192 * @arg RAMCFG_IT_NMIERR : Double Error Interrupt redirection to NMI Mask. 193 * @arg RAMCFG_IT_ALL : All Interrupt Mask. 194 * @retval None 195 */ 196 #define __HAL_RAMCFG_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 197 ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 198 199 /** 200 * @brief Disable the specified RAMCFG interrupts. 201 * @note This macros is used only to disable RAMCFG_IT_SINGLEERR and RAMCFG_IT_DOUBLEERR 202 * interrupts. RAMCFG_IT_NMIERR interrupt can only be disabled by global peripheral reset or system reset. 203 * @param __HANDLE__ : Specifies RAMCFG handle. 204 * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be disabled. 205 * This parameter can be one of the following values: 206 * @arg RAMCFG_IT_SINGLEERR : Single Error Interrupt Mask. 207 * @arg RAMCFG_IT_DOUBLEERR : Double Error Interrupt Mask. 208 * @retval None 209 */ 210 #define __HAL_RAMCFG_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 211 ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) 212 213 /** 214 * @brief Check whether the specified RAMCFG interrupt source is enabled or not. 215 * @param __HANDLE__ : Specifies the RAMCFG Handle. 216 * @param __INTERRUPT__ : Specifies the RAMCFG interrupt source to check. 217 * This parameter can be one of the following values: 218 * @arg RAMCFG_IT_SINGLEERR : Single Error Interrupt Mask. 219 * @arg RAMCFG_IT_DOUBLEERR : Double Error Interrupt Mask. 220 * @arg RAMCFG_IT_NMIERR : Double Error Interrupt Redirection to NMI Mask. 221 * @retval The new state of __INTERRUPT__ (SET or RESET). 222 */ 223 #define __HAL_RAMCFG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 224 ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) 225 226 /** 227 * @brief Get the RAMCFG pending flags. 228 * @param __HANDLE__ : Specifies RAMCFG handle. 229 * @param __FLAG__ : Specifies the flag to be checked. 230 * This parameter can be one of the following values: 231 * @arg RAMCFG_FLAG_SINGLEERR : Single Error Detected and Corrected Flag. 232 * @arg RAMCFG_FLAG_DOUBLEERR : Double Error Detected Flag. 233 * @arg RAMCFG_FLAG_SRAMBUSY : SRAM Busy Flag. 234 * @retval The state of FLAG (SET or RESET). 235 */ 236 #define __HAL_RAMCFG_GET_FLAG(__HANDLE__, __FLAG__) \ 237 (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__)) 238 239 /** 240 * @brief Clear the RAMCFG pending flags. 241 * @param __HANDLE__ : Specifies RAMCFG handle. 242 * @param __FLAG__ : Specifies the flag to be cleared. 243 * This parameter can be any combination of the following values: 244 * @arg RAMCFG_FLAG_SINGLEERR : Single Error Detected and Corrected Flag. 245 * @arg RAMCFG_FLAG_DOUBLEERR : Double Error Detected Flag. 246 * @retval None. 247 */ 248 #define __HAL_RAMCFG_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 249 ((__HANDLE__)->Instance->ICR |= (__FLAG__)) 250 251 /** @brief Reset the RAMCFG handle state. 252 * @param __HANDLE__ : Specifies the RAMCFG Handle. 253 * @retval None. 254 */ 255 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 256 #define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) \ 257 do{\ 258 (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \ 259 (__HANDLE__)->MspInitCallback = NULL; \ 260 (__HANDLE__)->MspDeInitCallback = NULL; \ 261 }while(0) 262 #else 263 #define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) \ 264 do{\ 265 (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \ 266 }while(0) 267 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 268 269 /** 270 * @} 271 */ 272 273 /* Exported functions --------------------------------------------------------*/ 274 275 /** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions 276 * @brief RAMCFG Exported Functions 277 * @{ 278 */ 279 280 /** @defgroup RAMCFG_Exported_Functions_Group1 Initialization and De-Initialization Functions 281 * @brief Initialization and De-Initialization Functions 282 * @{ 283 */ 284 HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg); 285 HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg); 286 void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg); 287 void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg); 288 /** 289 * @} 290 */ 291 292 /** @defgroup RAMCFG_Exported_Functions_Group2 ECC Operation Functions 293 * @brief ECC Operation Functions 294 * @{ 295 */ 296 HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg); 297 HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg); 298 HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications); 299 HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications); 300 uint32_t HAL_RAMCFG_IsECCSingleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg); 301 uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg); 302 uint32_t HAL_RAMCFG_GetSingleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg); 303 uint32_t HAL_RAMCFG_GetDoubleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg); 304 /** 305 * @} 306 */ 307 308 /** @defgroup RAMCFG_Exported_Functions_Group3 Configure Wait State Functions 309 * @brief Configure Wait State Functions 310 * @{ 311 */ 312 HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState); 313 uint32_t HAL_RAMCFG_GetWaitState(const RAMCFG_HandleTypeDef *hramcfg); 314 /** 315 * @} 316 */ 317 318 /** @defgroup RAMCFG_Exported_Functions_Group4 Write Protection Functions 319 * @brief Write Protection Functions 320 * @{ 321 */ 322 HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage); 323 /** 324 * @} 325 */ 326 327 /** @defgroup RAMCFG_Exported_Functions_Group5 Erase Operation Functions 328 * @brief Erase Operation Functions 329 * @{ 330 */ 331 HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg); 332 /** 333 * @} 334 */ 335 336 /** @defgroup RAMCFG_Exported_Functions_Group6 Handle Interrupt and Callbacks Functions 337 * @brief Handle Interrupt and Callbacks Functions 338 * @{ 339 */ 340 void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg); 341 void HAL_RAMCFG_DetectSingleErrorCallback(RAMCFG_HandleTypeDef *hramcfg); 342 void HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg); 343 #if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) 344 HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, 345 HAL_RAMCFG_CallbackIDTypeDef CallbackID, 346 void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg)); 347 HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID); 348 #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup RAMCFG_Exported_Functions_Group7 State and Error Functions 354 * @brief State and Error Functions 355 * @{ 356 */ 357 uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg); 358 HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg); 359 /** 360 * @} 361 */ 362 363 /** 364 * @} 365 */ 366 367 368 /* Private Constants ---------------------------------------------------------*/ 369 370 /** @defgroup RAMCFG_Private_Constants RAMCFG Private Defines and Constants 371 * @brief RAMCFG Private Defines and Constants 372 * @{ 373 */ 374 /** 375 * @} 376 */ 377 378 379 /* Private macros ------------------------------------------------------------*/ 380 381 /** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros 382 * @brief RAMCFG Private Macros 383 * @{ 384 */ 385 #define IS_RAMCFG_INTERRUPT(INTERRUPT) \ 386 (((INTERRUPT) != 0U) && (((INTERRUPT) & ~(RAMCFG_IT_SINGLEERR | RAMCFG_IT_DOUBLEERR | RAMCFG_IT_NMIERR)) == 0U)) 387 388 389 #define IS_RAMCFG_WAITSTATE(WAITSTATE) \ 390 (((WAITSTATE) == RAMCFG_WAITSTATE_0) || ((WAITSTATE) == RAMCFG_WAITSTATE_1) || \ 391 ((WAITSTATE) == RAMCFG_WAITSTATE_2) || ((WAITSTATE) == RAMCFG_WAITSTATE_3) || \ 392 ((WAITSTATE) == RAMCFG_WAITSTATE_4) || ((WAITSTATE) == RAMCFG_WAITSTATE_5) || \ 393 ((WAITSTATE) == RAMCFG_WAITSTATE_6) || ((WAITSTATE) == RAMCFG_WAITSTATE_7)) 394 395 #define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) 396 397 398 /** 399 * @} 400 */ 401 402 403 /* Private functions ---------------------------------------------------------*/ 404 405 /** @defgroup RAMCFG_Private_Functions RAMCFG Private Functions 406 * @brief RAMCFG Private Functions 407 * @{ 408 */ 409 /** 410 * @} 411 */ 412 413 /** 414 * @} 415 */ 416 417 /** 418 * @} 419 */ 420 421 #ifdef __cplusplus 422 } 423 #endif 424 425 #endif /* STM32U5xx_HAL_RAMCFG_H */ 426
