1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32U5xx_HAL_PWR_EX_H 22 #define STM32U5xx_HAL_PWR_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_def.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup PWREx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief PWR PVM configuration structure definition 47 */ 48 typedef struct 49 { 50 uint32_t PVMType; /*!< Specifies which voltage is monitored. 51 This parameter can be a value of 52 @ref PWREx_PVM_Type. */ 53 54 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 55 This parameter can be a value of 56 @ref PWREx_PVM_Mode. */ 57 } PWR_PVMTypeDef; 58 /** 59 * @} 60 */ 61 62 /* Exported constants --------------------------------------------------------*/ 63 64 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 65 * @{ 66 */ 67 68 /** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type 69 * @{ 70 */ 71 #define PWR_UVM PWR_SVMCR_UVMEN /*!< Independent USB voltage monitor (VDDUSB versus 1.2 V) */ 72 #define PWR_IO2VM PWR_SVMCR_IO2VMEN /*!< Independent VDDIO2 voltage monitor (VDDIO2 versus 0.9 V) */ 73 #define PWR_AVM1 PWR_SVMCR_AVM1EN /*!< Independent VDDA voltage monitor (VDDA versus 1.6 V) */ 74 #define PWR_AVM2 PWR_SVMCR_AVM2EN /*!< Independent VDDA voltage monitor (VDDA versus 1.8 V) */ 75 /** 76 * @} 77 */ 78 79 /** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode 80 * @{ 81 */ 82 #define PWR_PVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ 83 #define PWR_PVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ 84 #define PWR_PVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ 85 #define PWR_PVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 86 #define PWR_PVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ 87 #define PWR_PVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ 88 #define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ 89 /** 90 * @} 91 */ 92 93 /** @defgroup PWREx_SRD_State PWREx SRD Domain State 94 * @{ 95 */ 96 #define PWR_SRD_DOMAIN_STOP (0U) /*!< SRD in Stop mode when system goes to Stop 0/1/2 mode */ 97 #define PWR_SRD_DOMAIN_RUN PWR_CR2_SRDRUN /*!< SRD in Run mode when system goes to Stop 0/1/2 mode */ 98 /** 99 * @} 100 */ 101 102 /** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended RAM Contents Stop Retention 103 * @{ 104 */ 105 /* SRAM1 pages retention defines */ 106 #define PWR_SRAM1_PAGE1_STOP_RETENTION (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 107 #define PWR_SRAM1_PAGE2_STOP_RETENTION (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 108 #define PWR_SRAM1_PAGE3_STOP_RETENTION (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 109 #define PWR_SRAM1_FULL_STOP_RETENTION (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 110 111 /* SRAM2 pages retention defines */ 112 #define PWR_SRAM2_PAGE1_STOP_RETENTION (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ 113 #define PWR_SRAM2_PAGE2_STOP_RETENTION (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ 114 #define PWR_SRAM2_FULL_STOP_RETENTION (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ 115 116 /* SRAM3 pages retention defines */ 117 #define PWR_SRAM3_PAGE1_STOP_RETENTION (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 118 #define PWR_SRAM3_PAGE2_STOP_RETENTION (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 119 #define PWR_SRAM3_PAGE3_STOP_RETENTION (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 120 #define PWR_SRAM3_PAGE4_STOP_RETENTION (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 121 #define PWR_SRAM3_PAGE5_STOP_RETENTION (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 122 #define PWR_SRAM3_PAGE6_STOP_RETENTION (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 123 #define PWR_SRAM3_PAGE7_STOP_RETENTION (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 124 #define PWR_SRAM3_PAGE8_STOP_RETENTION (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 125 #define PWR_SRAM3_FULL_STOP_RETENTION (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 126 127 /* SRAM4 page retention defines */ 128 #define PWR_SRAM4_FULL_STOP_RETENTION (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ 129 130 /* Cache RAMs retention defines */ 131 #define PWR_ICACHE_FULL_STOP_RETENTION (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ 132 #define PWR_DCACHE1_FULL_STOP_RETENTION (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ 133 134 /* DMA2D RAM retention defines */ 135 #define PWR_DMA2DRAM_FULL_STOP_RETENTION (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 136 137 /* FMAC, FDCAN and USB RAMs retention defines */ 138 #define PWR_PERIPHRAM_FULL_STOP_RETENTION (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 139 140 /* PKA32 RAM retention defines */ 141 #define PWR_PKA32RAM_FULL_STOP_RETENTION (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 142 /** 143 * @} 144 */ 145 146 /** @defgroup PWREx_SRAM2_Contents_Standby_Retention PWR Extended SRAM2 Contents Standby Retention 147 * @note For some products of the U5 family (please see the Reference Manual), 148 * the SRAM2 content is preserved based on the same defines in Stop 3 mode. 149 * @{ 150 */ 151 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ 152 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ 153 #define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ 154 /** 155 * @} 156 */ 157 158 /** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention 159 * @{ 160 */ 161 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ 162 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ 163 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ 164 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ 165 /** 166 * @} 167 */ 168 169 /** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration 170 * @{ 171 */ 172 #define PWR_LDO_SUPPLY (0U) /*!< LDO supply */ 173 #define PWR_SMPS_SUPPLY (PWR_CR3_REGSEL) /*!< SMPS supply */ 174 /** 175 * @} 176 */ 177 178 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale 179 * @{ 180 */ 181 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1) /*!< Voltage scaling range 1 */ 182 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */ 183 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */ 184 #define PWR_REGULATOR_VOLTAGE_SCALE4 (0U) /*!< Voltage scaling range 4 */ 185 /** 186 * @} 187 */ 188 189 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection 190 * @{ 191 */ 192 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */ 193 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 194 /** 195 * @} 196 */ 197 198 /** @defgroup PWREx_VBAT_Battery_Charging_State PWR Extended Battery Charging State 199 * @{ 200 */ 201 #define PWR_BATTERY_CHARGING_DISABLE (0U) /*!< Disable battery charging */ 202 #define PWR_BATTERY_CHARGING_ENABLE PWR_BDCR2_VBE /*!< Enable battery charging */ 203 /** 204 * @} 205 */ 206 207 /** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port 208 * @{ 209 */ 210 #define PWR_GPIO_A (0x00U) /*!< GPIO port A */ 211 #define PWR_GPIO_B (0x01U) /*!< GPIO port B */ 212 #define PWR_GPIO_C (0x02U) /*!< GPIO port C */ 213 #define PWR_GPIO_D (0x03U) /*!< GPIO port D */ 214 #define PWR_GPIO_E (0x04U) /*!< GPIO port E */ 215 #define PWR_GPIO_F (0x05U) /*!< GPIO port F */ 216 #define PWR_GPIO_G (0x06U) /*!< GPIO port G */ 217 #define PWR_GPIO_H (0x07U) /*!< GPIO port H */ 218 #define PWR_GPIO_I (0x08U) /*!< GPIO port I */ 219 /** 220 * @} 221 */ 222 223 /** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask 224 * @{ 225 */ 226 #define PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */ 227 #define PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */ 228 #define PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */ 229 #define PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */ 230 #define PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */ 231 #define PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */ 232 #define PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */ 233 #define PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */ 234 #define PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */ 235 #define PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */ 236 #define PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */ 237 #define PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */ 238 #define PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */ 239 #define PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */ 240 #define PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */ 241 #define PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */ 242 /** 243 * @} 244 */ 245 246 /** 247 * @} 248 */ 249 250 /* Exported macros -----------------------------------------------------------*/ 251 252 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 253 * @{ 254 */ 255 256 /** 257 * @brief Enable the UVM Extended Interrupt Line. 258 * @retval None. 259 */ 260 #define __HAL_PWR_UVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) 261 262 /** 263 * @brief Disable the UVM Extended Interrupt Line. 264 * @retval None. 265 */ 266 #define __HAL_PWR_UVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) 267 268 /** 269 * @brief Enable the UVM Event Line. 270 * @retval None. 271 */ 272 #define __HAL_PWR_UVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) 273 274 /** 275 * @brief Disable the UVM Event Line. 276 * @retval None. 277 */ 278 #define __HAL_PWR_UVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) 279 280 /** 281 * @brief Enable the UVM Extended Interrupt Rising Trigger. 282 * @retval None. 283 */ 284 #define __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) 285 286 /** 287 * @brief Disable the UVM Extended Interrupt Rising Trigger. 288 * @retval None. 289 */ 290 #define __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) 291 292 /** 293 * @brief Enable the UVM Extended Interrupt Falling Trigger. 294 * @retval None. 295 */ 296 #define __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) 297 298 /** 299 * @brief Disable the UVM Extended Interrupt Falling Trigger. 300 * @retval None. 301 */ 302 #define __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) 303 304 /** 305 * @brief Enable the UVM Extended Interrupt Rising & Falling Trigger. 306 * @retval None. 307 */ 308 #define __HAL_PWR_UVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ 309 do \ 310 { \ 311 __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); \ 312 __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); \ 313 } while(0) 314 315 /** 316 * @brief Disable the UVM Extended Interrupt Rising & Falling Trigger. 317 * @retval None. 318 */ 319 #define __HAL_PWR_UVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ 320 do \ 321 { \ 322 __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); \ 323 __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); \ 324 } while(0) 325 326 /** 327 * @brief Generate a Software Interrupt on UVM EXTI Line. 328 * @retval None 329 */ 330 #define __HAL_PWR_UVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_UVM) 331 332 /** 333 * @brief Check whether the specified UVM EXTI flag is set or not. 334 * @retval EXTI UVM Line Status. 335 */ 336 #define __HAL_PWR_UVM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_UVM) 337 338 /** 339 * @brief Clear the UVM EXTI flag. 340 * @retval None. 341 */ 342 #define __HAL_PWR_UVM_EXTI_CLEAR_FLAG() \ 343 do \ 344 { \ 345 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); \ 346 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); \ 347 } while(0) 348 349 /** 350 * @brief Enable the IO2VM Extended Interrupt Line. 351 * @retval None. 352 */ 353 #define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) 354 355 /** 356 * @brief Disable the IO2VM Extended Interrupt Line. 357 * @retval None. 358 */ 359 #define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) 360 361 /** 362 * @brief Enable the IO2VM Event Line. 363 * @retval None. 364 */ 365 #define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) 366 367 /** 368 * @brief Disable the IO2VM Event Line. 369 * @retval None. 370 */ 371 #define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) 372 373 /** 374 * @brief Enable the IO2VM Extended Interrupt Rising Trigger. 375 * @retval None. 376 */ 377 #define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) 378 379 /** 380 * @brief Disable the IO2VM Extended Interrupt Rising Trigger. 381 * @retval None. 382 */ 383 #define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) 384 385 /** 386 * @brief Enable the IO2VM Extended Interrupt Falling Trigger. 387 * @retval None. 388 */ 389 #define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) 390 391 /** 392 * @brief Disable the IO2VM Extended Interrupt Falling Trigger. 393 * @retval None. 394 */ 395 #define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) 396 397 /** 398 * @brief Enable the IO2VM Extended Interrupt Rising & Falling Trigger. 399 * @retval None. 400 */ 401 #define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ 402 do \ 403 { \ 404 __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); \ 405 __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); \ 406 } while(0) 407 408 /** 409 * @brief Disable the IO2VM Extended Interrupt Rising & Falling Trigger. 410 * @retval None. 411 */ 412 #define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ 413 do \ 414 { \ 415 __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); \ 416 __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); \ 417 } while(0) 418 419 /** 420 * @brief Generate a Software Interrupt on IO2VM EXTI Line. 421 * @retval None 422 */ 423 #define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_IO2VM) 424 425 /** 426 * @brief Check whether the specified IO2VM EXTI flag is set or not. 427 * @retval EXTI IO2VM Line Status. 428 */ 429 #define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_IO2VM) 430 431 /** 432 * @brief Clear the IO2VM EXTI flag. 433 * @retval None. 434 */ 435 #define __HAL_PWR_IO2VM_EXTI_CLEAR_FLAG() \ 436 do \ 437 { \ 438 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); \ 439 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); \ 440 } while(0) 441 442 /** 443 * @brief Enable the AVM1 Extended Interrupt Line. 444 * @retval None. 445 */ 446 #define __HAL_PWR_AVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) 447 448 /** 449 * @brief Disable the AVM1 Extended Interrupt Line. 450 * @retval None. 451 */ 452 #define __HAL_PWR_AVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) 453 454 /** 455 * @brief Enable the AVM1 Event Line. 456 * @retval None. 457 */ 458 #define __HAL_PWR_AVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) 459 460 /** 461 * @brief Disable the AVM1 Event Line. 462 * @retval None. 463 */ 464 #define __HAL_PWR_AVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) 465 466 /** 467 * @brief Enable the AVM1 Extended Interrupt Rising Trigger. 468 * @retval None. 469 */ 470 #define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) 471 472 /** 473 * @brief Disable the AVM1 Extended Interrupt Rising Trigger. 474 * @retval None. 475 */ 476 #define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) 477 478 /** 479 * @brief Enable the AVM1 Extended Interrupt Falling Trigger. 480 * @retval None. 481 */ 482 #define __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) 483 484 /** 485 * @brief Disable the AVM1 Extended Interrupt Falling Trigger. 486 * @retval None. 487 */ 488 #define __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) 489 490 /** 491 * @brief Enable the AVM1 Extended Interrupt Rising & Falling Trigger. 492 * @retval None. 493 */ 494 #define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 495 do \ 496 { \ 497 __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); \ 498 __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); \ 499 } while(0) 500 501 /** 502 * @brief Disable the AVM1 Extended Interrupt Rising & Falling Trigger. 503 * @retval None. 504 */ 505 #define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 506 do \ 507 { \ 508 __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); \ 509 __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); \ 510 } while(0) 511 512 /** 513 * @brief Generate a Software Interrupt on AVM1 EXTI Line. 514 * @retval None 515 */ 516 #define __HAL_PWR_AVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM1) 517 518 /** 519 * @brief Check whether the specified AVM1 EXTI flag is set or not. 520 * @retval EXTI AVM1 Line Status. 521 */ 522 #define __HAL_PWR_AVM1_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM1) 523 524 /** 525 * @brief Clear the AVM1 EXTI flag. 526 * @retval None. 527 */ 528 #define __HAL_PWR_AVM1_EXTI_CLEAR_FLAG() \ 529 do \ 530 { \ 531 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); \ 532 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); \ 533 } while(0) 534 535 /** 536 * @brief Enable the AVM2 Extended Interrupt Line. 537 * @retval None. 538 */ 539 #define __HAL_PWR_AVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) 540 541 /** 542 * @brief Disable the AVM2 Extended Interrupt Line. 543 * @retval None. 544 */ 545 #define __HAL_PWR_AVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) 546 547 /** 548 * @brief Enable the AVM2 Event Line. 549 * @retval None. 550 */ 551 #define __HAL_PWR_AVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) 552 553 /** 554 * @brief Disable the AVM2 Event Line. 555 * @retval None. 556 */ 557 #define __HAL_PWR_AVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) 558 559 /** 560 * @brief Enable the AVM2 Extended Interrupt Rising Trigger. 561 * @retval None. 562 */ 563 #define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) 564 565 /** 566 * @brief Disable the AVM2 Extended Interrupt Rising Trigger. 567 * @retval None. 568 */ 569 #define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) 570 571 /** 572 * @brief Enable the AVM2 Extended Interrupt Falling Trigger. 573 * @retval None. 574 */ 575 #define __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) 576 577 /** 578 * @brief Disable the AVM2 Extended Interrupt Falling Trigger. 579 * @retval None. 580 */ 581 #define __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) 582 583 /** 584 * @brief Enable the AVM2 Extended Interrupt Rising & Falling Trigger. 585 * @retval None. 586 */ 587 #define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 588 do \ 589 { \ 590 __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); \ 591 __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); \ 592 } while(0) 593 594 /** 595 * @brief Disable the AVM2 Extended Interrupt Rising & Falling Trigger. 596 * @retval None. 597 */ 598 #define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 599 do \ 600 { \ 601 __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); \ 602 __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); \ 603 } while(0) 604 605 /** 606 * @brief Generate a Software Interrupt on AVM2 EXTI Line. 607 * @retval None 608 */ 609 #define __HAL_PWR_AVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM2) 610 611 /** 612 * @brief Check whether the specified AVM2 EXTI flag is set or not. 613 * @retval EXTI AVM2 Line Status. 614 */ 615 #define __HAL_PWR_AVM2_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM2) 616 617 /** 618 * @brief Clear the AVM2 EXTI flag. 619 * @retval None. 620 */ 621 #define __HAL_PWR_AVM2_EXTI_CLEAR_FLAG() \ 622 do \ 623 { \ 624 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); \ 625 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); \ 626 } while(0) 627 628 /** 629 * @brief Configure the main internal regulator output voltage. 630 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but 631 * doesn't check whether or not VOSREADY flag is set. User may resort 632 * to __HAL_PWR_GET_FLAG() macro to check VOSF bit state. 633 * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a 634 * tradeoff between performance and power consumption. 635 * This parameter can be one of the following values : 636 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. 637 * Provides a typical output voltage at 1.2 V. 638 * Used when system clock frequency is up to 160 MHz. 639 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. 640 * Provides a typical output voltage at 1.1 V. 641 * Used when system clock frequency is up to 100 MHz. 642 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. 643 * Provides a typical output voltage at 1.0 V. 644 * Used when system clock frequency is up to 50 MHz. 645 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4. 646 * Provides a typical output voltage at 0.9 V. 647 * Used when system clock frequency is up to 24 MHz. 648 * @retval None. 649 */ 650 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 651 do \ 652 { \ 653 __IO uint32_t tmpreg; \ 654 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \ 655 tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \ 656 UNUSED(tmpreg); \ 657 } while(0) 658 /** 659 * @} 660 */ 661 662 /* Private constants ---------------------------------------------------------*/ 663 664 /** @addtogroup PWREx_Private_Constants PWR Extended Private Constants 665 * @{ 666 */ 667 /* PVM extended interrupts and event lines defines */ 668 #define PWR_EXTI_LINE_UVM (0x00080000UL) /* UVM EXTI Line */ 669 #define PWR_EXTI_LINE_IO2VM (0x00100000UL) /* IO2VM EXTI Line */ 670 #define PWR_EXTI_LINE_AVM1 (0x00200000UL) /* AVM1 EXTI Line */ 671 #define PWR_EXTI_LINE_AVM2 (0x00400000UL) /* AVM2 EXTI Line */ 672 673 /* SRAM retention IDs */ 674 #define SRAM_ID_MASK (0xFFFFUL << 16U) 675 #define SRAM1_ID (0x01UL << 16U) 676 #define SRAM2_ID (0x01UL << 17U) 677 #define SRAM3_ID (0x01UL << 18U) 678 #define SRAM4_ID (0x01UL << 19U) 679 #define ICACHERAM_ID (0x01UL << 20U) 680 #define DCACHE1RAM_ID (0x01UL << 21U) 681 #define DMA2DRAM_ID (0x01UL << 22U) 682 #define PERIPHRAM_ID (0x01UL << 23U) 683 #define PKARAM_ID (0x01UL << 24U) 684 685 /* SRAM page retention IDs */ 686 #define PAGE01_ID (0x01UL << 0U) 687 #define PAGE02_ID (0x01UL << 1U) 688 #define PAGE03_ID (0x01UL << 2U) 689 #define PAGE04_ID (0x01UL << 3U) 690 #define PAGE05_ID (0x01UL << 4U) 691 #define PAGE06_ID (0x01UL << 5U) 692 #define PAGE07_ID (0x01UL << 6U) 693 #define PAGE08_ID (0x01UL << 7U) 694 #define PAGE09_ID (0x01UL << 8U) 695 #define PAGE10_ID (0x01UL << 9U) 696 #define PAGE11_ID (0x01UL << 10U) 697 #define PAGE12_ID (0x01UL << 11U) 698 #define PAGE13_ID (0x01UL << 12U) 699 700 /* All available RAM retention in Run mode define */ 701 #define PWR_ALL_RAM_RUN_RETENTION_MASK (PWR_SRAM1_FULL_RUN_RETENTION | PWR_SRAM2_FULL_RUN_RETENTION | \ 702 PWR_SRAM3_FULL_RUN_RETENTION | PWR_SRAM4_FULL_RUN_RETENTION) 703 /** 704 * @} 705 */ 706 707 /* Private macros --------------------------------------------------------*/ 708 709 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 710 * @{ 711 */ 712 /* PVM type check macro */ 713 #define IS_PWR_PVM_TYPE(TYPE) \ 714 (((TYPE) == PWR_UVM ) ||\ 715 ((TYPE) == PWR_IO2VM) ||\ 716 ((TYPE) == PWR_AVM1) ||\ 717 ((TYPE) == PWR_AVM2)) 718 719 /* PVM mode check macro */ 720 #define IS_PWR_PVM_MODE(MODE) \ 721 (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 722 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 723 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 724 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 725 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 726 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 727 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 728 729 /* SRD state check macro */ 730 #define IS_PWR_SRD_STATE(SRD_STATE) \ 731 (((SRD_STATE) == PWR_SRD_DOMAIN_STOP) ||\ 732 ((SRD_STATE) == PWR_SRD_DOMAIN_RUN)) 733 734 /* Supply selection check macro */ 735 #define IS_PWR_SUPPLY(PWR_SOURCE) \ 736 (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 737 ((PWR_SOURCE) == PWR_SMPS_SUPPLY)) 738 739 /* Voltage scaling range check macro */ 740 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \ 741 (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ 742 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\ 743 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3) ||\ 744 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE4)) 745 746 /* Battery charging resistor selection check macro */ 747 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \ 748 (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 749 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 750 751 /* Battery charging activation check macro */ 752 #define IS_PWR_BATTERY_CHARGING(CHARGING) \ 753 (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 754 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 755 756 /* GPIO port check macro */ 757 #define IS_PWR_GPIO_PORT(GPIO_PORT) \ 758 (((GPIO_PORT) == PWR_GPIO_A) ||\ 759 ((GPIO_PORT) == PWR_GPIO_B) ||\ 760 ((GPIO_PORT) == PWR_GPIO_C) ||\ 761 ((GPIO_PORT) == PWR_GPIO_D) ||\ 762 ((GPIO_PORT) == PWR_GPIO_E) ||\ 763 ((GPIO_PORT) == PWR_GPIO_F) ||\ 764 ((GPIO_PORT) == PWR_GPIO_G) ||\ 765 ((GPIO_PORT) == PWR_GPIO_H) ||\ 766 ((GPIO_PORT) == PWR_GPIO_I)) 767 768 /* GPIO pin mask check macro */ 769 #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \ 770 ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK)) 771 772 /* SRAM2 retention in Standby mode check macro */ 773 #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \ 774 (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\ 775 ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\ 776 ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION)) 777 778 /* RAMs retention in Stop mode check macros */ 779 #define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \ 780 ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 781 782 #define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \ 783 ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 784 785 #define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \ 786 ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 787 788 #define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \ 789 ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 790 791 #define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \ 792 ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 793 794 #define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \ 795 ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 796 797 #define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \ 798 ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 799 800 #define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \ 801 ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 802 803 #define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \ 804 ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) 805 806 /* RAMs retention in Run mode check macro */ 807 #define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \ 808 ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_RETENTION_MASK)) == 0U) && ((RAMCONTENT) != 0U)) 809 /** 810 * @} 811 */ 812 813 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 814 * @{ 815 */ 816 817 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 818 * @{ 819 */ 820 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 821 uint32_t HAL_PWREx_GetVoltageRange(void); 822 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); 823 uint32_t HAL_PWREx_GetSupplyConfig(void); 824 void HAL_PWREx_EnableFastSoftStart(void); 825 void HAL_PWREx_DisableFastSoftStart(void); 826 /** 827 * @} 828 */ 829 830 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 831 * @{ 832 */ 833 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 834 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 835 void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry); 836 void HAL_PWREx_EnterSHUTDOWNMode(void); 837 void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState); 838 void HAL_PWREx_EnableUltraLowPowerMode(void); 839 void HAL_PWREx_DisableUltraLowPowerMode(void); 840 void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin); 841 void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin); 842 /** 843 * @} 844 */ 845 846 /** @addtogroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions 847 * @{ 848 */ 849 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); 850 void HAL_PWREx_DisableBatteryCharging(void); 851 void HAL_PWREx_EnableVddUSB(void); 852 void HAL_PWREx_DisableVddUSB(void); 853 void HAL_PWREx_EnableVddIO2(void); 854 void HAL_PWREx_DisableVddIO2(void); 855 void HAL_PWREx_EnableVddA(void); 856 void HAL_PWREx_DisableVddA(void); 857 void HAL_PWREx_EnableUVM(void); 858 void HAL_PWREx_DisableUVM(void); 859 void HAL_PWREx_EnableIO2VM(void); 860 void HAL_PWREx_DisableIO2VM(void); 861 void HAL_PWREx_EnableAVM1(void); 862 void HAL_PWREx_DisableAVM1(void); 863 void HAL_PWREx_EnableAVM2(void); 864 void HAL_PWREx_DisableAVM2(void); 865 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM); 866 void HAL_PWREx_EnableMonitoring(void); 867 void HAL_PWREx_DisableMonitoring(void); 868 void HAL_PWREx_EnableUCPDStandbyMode(void); 869 void HAL_PWREx_DisableUCPDStandbyMode(void); 870 void HAL_PWREx_EnableUCPDDeadBattery(void); 871 void HAL_PWREx_DisableUCPDDeadBattery(void); 872 void HAL_PWREx_PVD_PVM_IRQHandler(void); 873 void HAL_PWREx_UVMCallback(void); 874 void HAL_PWREx_IO2VMCallback(void); 875 void HAL_PWREx_AVM1Callback(void); 876 void HAL_PWREx_AVM2Callback(void); 877 /** 878 * @} 879 */ 880 881 /** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions 882 * @{ 883 */ 884 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); 885 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); 886 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); 887 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); 888 void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection); 889 void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection); 890 void HAL_PWREx_EnableFlashFastWakeUp(void); 891 void HAL_PWREx_DisableFlashFastWakeUp(void); 892 void HAL_PWREx_EnableSRAM4FastWakeUp(void); 893 void HAL_PWREx_DisableSRAM4FastWakeUp(void); 894 HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void); 895 void HAL_PWREx_DisableBkupRAMRetention(void); 896 /** 897 * @} 898 */ 899 900 /** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions 901 * @{ 902 */ 903 void HAL_PWREx_EnablePullUpPullDownConfig(void); 904 void HAL_PWREx_DisablePullUpPullDownConfig(void); 905 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); 906 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); 907 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); 908 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); 909 /** 910 * @} 911 */ 912 913 /** 914 * @} 915 */ 916 917 /** 918 * @} 919 */ 920 921 /** 922 * @} 923 */ 924 925 #ifdef __cplusplus 926 } 927 #endif /* __cplusplus */ 928 929 930 #endif /* STM32U5xx_HAL_PWR_EX_H */ 931
