1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_hcd.h
4 * @author MCD Application Team
5 * @brief Header file of HCD HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_HAL_HCD_H
21 #define STM32U5xx_HAL_HCD_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx_ll_usb.h"
29
30 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS)
31 /** @addtogroup STM32U5xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup HCD HCD
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup HCD_Exported_Types HCD Exported Types
41 * @{
42 */
43
44 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
45 * @{
46 */
47 typedef enum
48 {
49 HAL_HCD_STATE_RESET = 0x00,
50 HAL_HCD_STATE_READY = 0x01,
51 HAL_HCD_STATE_ERROR = 0x02,
52 HAL_HCD_STATE_BUSY = 0x03,
53 HAL_HCD_STATE_TIMEOUT = 0x04
54 } HCD_StateTypeDef;
55
56 #if defined (USB_DRD_FS)
57 typedef USB_DRD_TypeDef HCD_TypeDef;
58 typedef USB_DRD_CfgTypeDef HCD_InitTypeDef;
59 typedef USB_DRD_HCTypeDef HCD_HCTypeDef;
60 typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
61 typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef;
62 #else
63 typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
64 typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
65 typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
66 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
67 typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
68 #endif /* defined (USB_DRD_FS) */
69 #if defined (USB_DRD_FS)
70 typedef enum
71 {
72 HCD_HCD_STATE_DISCONNECTED = 0x00U,
73 HCD_HCD_STATE_CONNECTED = 0x01U,
74 HCD_HCD_STATE_RESETED = 0x02U,
75 HCD_HCD_STATE_RUN = 0x03U,
76 HCD_HCD_STATE_SUSPEND = 0x04U,
77 HCD_HCD_STATE_RESUME = 0x05U,
78 } HCD_HostStateTypeDef;
79
80 /* PMA lookup Table size depending on PMA Size
81 * 8Bytes each Block 32Bit in each word
82 */
83 #define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))
84 #endif /* defined (USB_DRD_FS) */
85 /**
86 * @}
87 */
88
89 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
90 * @{
91 */
92 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
93 typedef struct __HCD_HandleTypeDef
94 #else
95 typedef struct
96 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
97 {
98 HCD_TypeDef *Instance; /*!< Register base address */
99 HCD_InitTypeDef Init; /*!< HCD required parameters */
100 HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
101 #if defined (USB_DRD_FS)
102 uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */
103 uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */
104 uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/
105 uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */
106 HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */
107 #endif /* defined (USB_DRD_FS) */
108 HAL_LockTypeDef Lock; /*!< HCD peripheral status */
109 __IO HCD_StateTypeDef State; /*!< HCD communication state */
110 __IO uint32_t ErrorCode; /*!< HCD Error code */
111 void *pData; /*!< Pointer Stack Handler */
112 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
113 void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
114 void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
115 void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
116 void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
117 void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
118 void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
119 HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
120
121 void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
122 void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
123 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
124 } HCD_HandleTypeDef;
125 /**
126 * @}
127 */
128
129 /**
130 * @}
131 */
132
133 /* Exported constants --------------------------------------------------------*/
134 /** @defgroup HCD_Exported_Constants HCD Exported Constants
135 * @{
136 */
137
138 /** @defgroup HCD_Speed HCD Speed
139 * @{
140 */
141 #define HCD_SPEED_HIGH USBH_HS_SPEED
142 #define HCD_SPEED_FULL USBH_FSLS_SPEED
143 #define HCD_SPEED_LOW USBH_FSLS_SPEED
144 /**
145 * @}
146 */
147
148 /** @defgroup HCD_Device_Speed HCD Device Speed
149 * @{
150 */
151 #define HCD_DEVICE_SPEED_HIGH 0U
152 #define HCD_DEVICE_SPEED_FULL 1U
153 #define HCD_DEVICE_SPEED_LOW 2U
154 /**
155 * @}
156 */
157
158 /** @defgroup HCD_PHY_Module HCD PHY Module
159 * @{
160 */
161 #define HCD_PHY_ULPI 1U
162 #define HCD_PHY_EMBEDDED 2U
163 /**
164 * @}
165 */
166
167 /** @defgroup HCD_Error_Code_definition HCD Error Code definition
168 * @brief HCD Error Code definition
169 * @{
170 */
171 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
172 #define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
173 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
174
175 /**
176 * @}
177 */
178
179 /**
180 * @}
181 */
182
183 /* Exported macro ------------------------------------------------------------*/
184 /** @defgroup HCD_Exported_Macros HCD Exported Macros
185 * @brief macros to handle interrupts and specific clock configurations
186 * @{
187 */
188 #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
189 #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
190
191 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
192 & (__INTERRUPT__)) == (__INTERRUPT__))
193 #if defined (USB_DRD_FS)
194 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
195 #else
196 #define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
197 ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
198
199 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
200 #endif /* defined (USB_DRD_FS) */
201 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
202
203 #if defined (USB_DRD_FS)
204 #define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
205 #define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
206 #else
207 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
208 #define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
209 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
210 #define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
211 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
212 #define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
213 #define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
214 #define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
215 #endif /* defined (USB_DRD_FS) */
216 /**
217 * @}
218 */
219
220 /* Exported functions --------------------------------------------------------*/
221 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
222 * @{
223 */
224
225 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
226 * @{
227 */
228 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
229 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
230 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
231 uint8_t epnum, uint8_t dev_address,
232 uint8_t speed, uint8_t ep_type, uint16_t mps);
233
234 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
235 #if defined (USB_DRD_FS)
236 HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
237 #endif /* defined (USB_DRD_FS) */
238 void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
239 void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
240
241 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
242 /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
243 * @brief HAL USB OTG HCD Callback ID enumeration definition
244 * @{
245 */
246 typedef enum
247 {
248 HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
249 HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
250 HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
251 HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
252 HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
253
254 HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
255 HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
256
257 } HAL_HCD_CallbackIDTypeDef;
258 /**
259 * @}
260 */
261
262 /** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
263 * @brief HAL USB OTG HCD Callback pointer definition
264 * @{
265 */
266
267 typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
268 typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
269 uint8_t epnum,
270 HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
271 /**
272 * @}
273 */
274
275 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
276 HAL_HCD_CallbackIDTypeDef CallbackID,
277 pHCD_CallbackTypeDef pCallback);
278
279 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
280 HAL_HCD_CallbackIDTypeDef CallbackID);
281
282 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
283 pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
284
285 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
286 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
287 /**
288 * @}
289 */
290
291 /* I/O operation functions ***************************************************/
292 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
293 * @{
294 */
295 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
296 uint8_t direction, uint8_t ep_type,
297 uint8_t token, uint8_t *pbuff,
298 uint16_t length, uint8_t do_ping);
299
300 HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
301 uint8_t addr, uint8_t PortNbr);
302
303 HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
304
305 /* Non-Blocking mode: Interrupt */
306 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
307 void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
308 void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
309 void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
310 void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
311 void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
312 #if defined (USB_DRD_FS)
313 void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd);
314 void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd);
315 #endif /* defined (USB_DRD_FS) */
316 void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
317 HCD_URBStateTypeDef urb_state);
318 /**
319 * @}
320 */
321
322 /* Peripheral Control functions **********************************************/
323 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
324 * @{
325 */
326 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
327 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
328 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
329 #if defined (USB_DRD_FS)
330 HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd);
331 HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd);
332 HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd);
333 #endif /* defined (USB_DRD_FS) */
334 /**
335 * @}
336 */
337
338 /* Peripheral State functions ************************************************/
339 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
340 * @{
341 */
342 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
343 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
344 HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
345 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
346 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
347 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
348
349 #if defined (USB_DRD_FS)
350 /* PMA Allocation functions **********************************************/
351 /** @addtogroup PMA Allocation
352 * @{
353 */
354 HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
355 uint16_t ch_kind, uint16_t mps);
356
357 HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
358 HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
359
360 /**
361 * @}
362 */
363 #endif /* defined (USB_DRD_FS) */
364
365 /**
366 * @}
367 */
368
369 /* Private macros ------------------------------------------------------------*/
370 /** @defgroup HCD_Private_Macros HCD Private Macros
371 * @{
372 */
373 #if defined (USB_DRD_FS)
374 #define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
375 #define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
376
377 /** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel
378 * @{
379 */
380 #define HCD_LOGICAL_CH_NOT_OPENED 0xFFU
381 #define HCD_FREE_CH_NOT_FOUND 0xFFU
382 /**
383 * @}
384 */
385
386 /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
387 * @{
388 */
389 #define HCD_SNG_BUF 0U
390 #define HCD_DBL_BUF 1U
391 /**
392 * @}
393 */
394
395 /* Powerdown exit count */
396 #define HCD_PDWN_EXIT_CNT 0x100U
397
398 /* Set Channel */
399 #define HCD_SET_CHANNEL USB_DRD_SET_CHEP
400
401 /* Get Channel Register */
402 #define HCD_GET_CHANNEL USB_DRD_GET_CHEP
403
404
405 /**
406 * @brief free buffer used from the application realizing it to the line
407 * toggles bit SW_BUF in the double buffered endpoint register
408 * @param USBx USB device.
409 * @param bChNum, bDir
410 * @retval None
411 */
412 #define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
413
414 /**
415 * @brief Set the Setup bit in the corresponding channel, when a Setup
416 transaction is needed.
417 * @param USBx USB device.
418 * @param bChNum
419 * @retval None
420 */
421 #define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
422
423 /**
424 * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
425 * @param USBx USB peripheral instance register address.
426 * @param bChNum Endpoint Number.
427 * @param wState new state
428 * @retval None
429 */
430 #define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
431
432 /**
433 * @brief sets the status for rx transfer (bits STAT_TX[1:0])
434 * @param USBx USB peripheral instance register address.
435 * @param bChNum Endpoint Number.
436 * @param wState new state
437 * @retval None
438 */
439 #define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
440 /**
441 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
442 * /STAT_RX[1:0])
443 * @param USBx USB peripheral instance register address.
444 * @param bChNum Endpoint Number.
445 * @retval status
446 */
447 #define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
448 #define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
449 /**
450 * @brief Sets/clears CH_KIND bit in the Channel register.
451 * @param USBx USB peripheral instance register address.
452 * @param bChNum Endpoint Number.
453 * @retval None
454 */
455 #define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
456 #define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
457 #define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
458 #define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
459
460 /**
461 * @brief Clears bit ERR_RX in the Channel register
462 * @param USBx USB peripheral instance register address.
463 * @param bChNum Endpoint Number.
464 * @retval None
465 */
466 #define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
467
468 /**
469 * @brief Clears bit ERR_TX in the Channel register
470 * @param USBx USB peripheral instance register address.
471 * @param bChNum Endpoint Number.
472 * @retval None
473 */
474 #define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
475 /**
476 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
477 * @param USBx USB peripheral instance register address.
478 * @param bChNum Endpoint Number.
479 * @retval None
480 */
481 #define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
482 #define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
483
484 /**
485 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
486 * @param USBx USB peripheral instance register address.
487 * @param bChNum Endpoint Number.
488 * @retval None
489 */
490 #define HCD_RX_DTOG USB_DRD_RX_DTOG
491 #define HCD_TX_DTOG USB_DRD_TX_DTOG
492 /**
493 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
494 * @param USBx USB peripheral instance register address.
495 * @param bChNum Endpoint Number.
496 * @retval None
497 */
498 #define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
499 #define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
500
501 /**
502 * @brief sets counter for the tx/rx buffer.
503 * @param USBx USB peripheral instance register address.
504 * @param bChNum Endpoint Number.
505 * @param wCount Counter value.
506 * @retval None
507 */
508 #define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
509 #define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
510
511 /**
512 * @brief gets counter of the tx buffer.
513 * @param USBx USB peripheral instance register address.
514 * @param bChNum channel Number.
515 * @retval Counter value
516 */
517 #define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
518
519 /**
520 * @brief gets counter of the rx buffer.
521 * @param Instance USB peripheral instance register address.
522 * @param bChNum channel Number.
523 * @retval Counter value
524 */
HCD_GET_CH_RX_CNT(HCD_TypeDef * Instance,uint16_t bChNum)525 __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
526 {
527 uint32_t HostCoreSpeed;
528 uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum);
529 __IO uint32_t count = 10U;
530
531 /* Get Host core Speed */
532 HostCoreSpeed = USB_GetHostSpeed(Instance);
533
534 /* Count depends on device LS */
535 if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP))
536 {
537 count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U;
538 }
539
540 if (count > 15U)
541 {
542 count = HCD_MAX(10U, (count - 15U));
543 }
544
545 /* WA: few cycles for RX PMA descriptor to update */
546 while (count > 0U)
547 {
548 count--;
549 }
550
551 return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
552 }
553
554 /**
555 * @brief Gets buffer 0/1 address of a double buffer endpoint.
556 * @param USBx USB peripheral instance register address.
557 * @param bChNum Endpoint Number.
558 * @param bDir endpoint dir EP_DBUF_OUT = OUT
559 * EP_DBUF_IN = IN
560 * @param wCount: Counter value
561 * @retval None
562 */
563 #define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
564 #define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
565 #define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
566
567
568 /**
569 * @brief gets counter of the rx buffer0.
570 * @param Instance USB peripheral instance register address.
571 * @param bChNum channel Number.
572 * @retval Counter value
573 */
HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)574 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
575 {
576 UNUSED(Instance);
577 __IO uint32_t count = 10U;
578
579 /* WA: few cycles for RX PMA descriptor to update */
580 while (count > 0U)
581 {
582 count--;
583 }
584
585 return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
586 }
587
588 /**
589 * @brief gets counter of the rx buffer1.
590 * @param Instance USB peripheral instance register address.
591 * @param bChNum channel Number.
592 * @retval Counter value
593 */
HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)594 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
595 {
596 UNUSED(Instance);
597 __IO uint32_t count = 10U;
598
599 /* WA: few cycles for RX PMA descriptor to update */
600 while (count > 0U)
601 {
602 count--;
603 }
604
605 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
606 }
607 #endif /* defined (USB_DRD_FS) */
608
609 /**
610 * @}
611 */
612 /* Private functions prototypes ----------------------------------------------*/
613
614 /**
615 * @}
616 */
617 /**
618 * @}
619 */
620 /**
621 * @}
622 */
623 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */
624
625 #ifdef __cplusplus
626 }
627 #endif
628
629 #endif /* STM32U5xx_HAL_HCD_H */
630
