1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2021 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27
28 [..]
29 *** How to configure Interrupts using CORTEX HAL driver ***
30 ===========================================================
31 [..]
32 This section provides functions allowing to configure the NVIC interrupts (IRQ).
33 The Cortex-M33 exceptions are managed by CMSIS functions.
34
35 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
36 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
37 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
38
39 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
40 The pending IRQ priority will be managed only by the sub priority.
41
42 -@- IRQ priority order (sorted by highest to lowest priority):
43 (+@) Lowest pre-emption priority
44 (+@) Lowest sub priority
45 (+@) Lowest hardware priority (IRQ number)
46
47 [..]
48 *** How to configure SysTick using CORTEX HAL driver ***
49 ========================================================
50 [..]
51 Setup SysTick Timer for time base.
52
53 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
54 is a CMSIS function that:
55 (++) Configures the SysTick Reload register with value passed as function parameter.
56 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
57 (++) Resets the SysTick Counter register.
58 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
59 (++) Enables the SysTick Interrupt.
60 (++) Starts the SysTick Counter.
61
62 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
63 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
64 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
65 inside the stm32u5xx_hal_cortex.h file.
66
67 (+) You can change the SysTick IRQ priority by calling the
68 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
69 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
70
71 (+) To adjust the SysTick time base, use the following formula:
72
73 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
74 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
75 (++) Reload Value should not exceed 0xFFFFFF
76
77 [..]
78 *** How to configure MPU (secure and non secure) using CORTEX HAL driver ***
79 ===========================================================
80 [..]
81 This section provides functions allowing to Enable and configure the MPU secure and non-secure.
82
83 (#) Enable the MPU using HAL_MPU_Enable() function.
84 (#) Disable the MPU using HAL_MPU_Disable() function.
85 (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU.
86 (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU.
87 (#) Configure the MPU region using HAL_MPU_ConfigRegion()
88 and HAL_MPU_ConfigRegion_NS() to address the non secure MPU.
89 (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes()
90 and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU.
91
92 @endverbatim
93 ******************************************************************************
94
95 The table below gives the allowed values of the pre-emption priority and subpriority according
96 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
97
98 ========================================================================================================================
99 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
100 ========================================================================================================================
101 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
102 | | | 4 bits for subpriority
103 ------------------------------------------------------------------------------------------------------------------------
104 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
105 | | | 3 bits for subpriority
106 ------------------------------------------------------------------------------------------------------------------------
107 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
108 | | | 2 bits for subpriority
109 ------------------------------------------------------------------------------------------------------------------------
110 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
111 | | | 1 bit for subpriority
112 ------------------------------------------------------------------------------------------------------------------------
113 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
114 | | | 0 bit for subpriority
115 ========================================================================================================================
116 */
117
118 /* Includes ------------------------------------------------------------------*/
119 #include "stm32u5xx_hal.h"
120
121 /** @addtogroup STM32U5xx_HAL_Driver
122 * @{
123 */
124
125 /** @addtogroup CORTEX
126 * @{
127 */
128
129 #ifdef HAL_CORTEX_MODULE_ENABLED
130
131 /* Private types -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private constants ---------------------------------------------------------*/
134 /* Private macros ------------------------------------------------------------*/
135 /* Private functions ---------------------------------------------------------*/
136 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
137 * @{
138 */
139 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit);
140 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
141 /**
142 * @}
143 */
144 /* Exported functions --------------------------------------------------------*/
145
146 /** @addtogroup CORTEX_Exported_Functions
147 * @{
148 */
149
150
151 /** @addtogroup CORTEX_Exported_Functions_Group1
152 * @brief Initialization and Configuration functions
153 *
154 @verbatim
155 ==============================================================================
156 ##### Initialization and Configuration functions #####
157 ==============================================================================
158 [..]
159 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
160 SysTick functionalities
161
162 @endverbatim
163 * @{
164 */
165
166
167 /**
168 * @brief Set the priority grouping field (pre-emption priority and subpriority)
169 * using the required unlock sequence.
170 * @param PriorityGroup: The priority grouping bits length.
171 * This parameter can be one of the following values:
172 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
173 * 4 bits for subpriority
174 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
175 * 3 bits for subpriority
176 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
177 * 2 bits for subpriority
178 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
179 * 1 bit for subpriority
180 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
181 * 0 bit for subpriority
182 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
183 * The pending IRQ priority will be managed only by the subpriority.
184 * @retval None
185 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)186 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
187 {
188 /* Check the parameters */
189 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
190
191 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
192 NVIC_SetPriorityGrouping(PriorityGroup);
193 }
194
195 /**
196 * @brief Set the priority of an interrupt.
197 * @param IRQn: External interrupt number.
198 * This parameter can be an enumerator of IRQn_Type enumeration
199 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
200 * CMSIS device file (stm32u5xxxx.h))
201 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
202 * This parameter can be a value between 0 and 15
203 * A lower priority value indicates a higher priority
204 * @param SubPriority: the subpriority level for the IRQ channel.
205 * This parameter can be a value between 0 and 15
206 * A lower priority value indicates a higher priority.
207 * @retval None
208 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)209 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
210 {
211 uint32_t prioritygroup;
212
213 /* Check the parameters */
214 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
215 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
216
217 prioritygroup = NVIC_GetPriorityGrouping();
218
219 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
220 }
221
222 /**
223 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
224 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
225 * function should be called before.
226 * @param IRQn External interrupt number.
227 * This parameter can be an enumerator of IRQn_Type enumeration
228 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
229 * CMSIS device file (stm32u5xxxx.h))
230 * @retval None
231 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)232 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
233 {
234 /* Check the parameters */
235 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
236
237 /* Enable interrupt */
238 NVIC_EnableIRQ(IRQn);
239 }
240
241 /**
242 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
243 * @param IRQn External interrupt number.
244 * This parameter can be an enumerator of IRQn_Type enumeration
245 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
246 * CMSIS device file (stm32u5xxxx.h))
247 * @retval None
248 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)249 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
250 {
251 /* Check the parameters */
252 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
253
254 /* Disable interrupt */
255 NVIC_DisableIRQ(IRQn);
256 }
257
258 /**
259 * @brief Initiate a system reset request to reset the MCU.
260 * @retval None
261 */
HAL_NVIC_SystemReset(void)262 void HAL_NVIC_SystemReset(void)
263 {
264 /* System Reset */
265 NVIC_SystemReset();
266 }
267
268 /**
269 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
270 * Counter is in free running mode to generate periodic interrupts.
271 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
272 * @retval status: - 0 Function succeeded.
273 * - 1 Function failed.
274 */
HAL_SYSTICK_Config(uint32_t TicksNumb)275 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
276 {
277 return SysTick_Config(TicksNumb);
278 }
279 /**
280 * @}
281 */
282
283 /** @addtogroup CORTEX_Exported_Functions_Group2
284 * @brief Cortex control functions
285 *
286 @verbatim
287 ==============================================================================
288 ##### Peripheral Control functions #####
289 ==============================================================================
290 [..]
291 This subsection provides a set of functions allowing to control the CORTEX
292 (NVIC, SYSTICK, MPU) functionalities.
293
294
295 @endverbatim
296 * @{
297 */
298
299 /**
300 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
301 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
302 */
HAL_NVIC_GetPriorityGrouping(void)303 uint32_t HAL_NVIC_GetPriorityGrouping(void)
304 {
305 /* Get the PRIGROUP[10:8] field value */
306 return NVIC_GetPriorityGrouping();
307 }
308
309 /**
310 * @brief Get the priority of an interrupt.
311 * @param IRQn: External interrupt number.
312 * This parameter can be an enumerator of IRQn_Type enumeration
313 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
314 * CMSIS device file (stm32u5xxxx.h))
315 * @param PriorityGroup: the priority grouping bits length.
316 * This parameter can be one of the following values:
317 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
318 * 4 bits for subpriority
319 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
320 * 3 bits for subpriority
321 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
322 * 2 bits for subpriority
323 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
324 * 1 bit for subpriority
325 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
326 * 0 bit for subpriority
327 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
328 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
329 * @retval None
330 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)331 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
332 uint32_t *const pSubPriority)
333 {
334 /* Check the parameters */
335 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
336 /* Get priority for Cortex-M system or device specific interrupts */
337 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
338 }
339
340 /**
341 * @brief Set Pending bit of an external interrupt.
342 * @param IRQn External interrupt number
343 * This parameter can be an enumerator of IRQn_Type enumeration
344 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
345 * CMSIS device file (stm32u5xxxx.h))
346 * @retval None
347 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)348 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
349 {
350 /* Set interrupt pending */
351 NVIC_SetPendingIRQ(IRQn);
352 }
353
354 /**
355 * @brief Get Pending Interrupt (read the pending register in the NVIC
356 * and return the pending bit for the specified interrupt).
357 * @param IRQn External interrupt number.
358 * This parameter can be an enumerator of IRQn_Type enumeration
359 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
360 * CMSIS device file (stm32u5xxxx.h))
361 * @retval status: - 0 Interrupt status is not pending.
362 * - 1 Interrupt status is pending.
363 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)364 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
365 {
366 /* Return 1 if pending else 0 */
367 return NVIC_GetPendingIRQ(IRQn);
368 }
369
370 /**
371 * @brief Clear the pending bit of an external interrupt.
372 * @param IRQn External interrupt number.
373 * This parameter can be an enumerator of IRQn_Type enumeration
374 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
375 * CMSIS device file (stm32u5xxxx.h))
376 * @retval None
377 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)378 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
379 {
380 /* Clear pending interrupt */
381 NVIC_ClearPendingIRQ(IRQn);
382 }
383
384 /**
385 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
386 * @param IRQn External interrupt number
387 * This parameter can be an enumerator of IRQn_Type enumeration
388 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
389 * CMSIS device file (stm32u5xxxx.h))
390 * @retval status: - 0 Interrupt status is not pending.
391 * - 1 Interrupt status is pending.
392 */
HAL_NVIC_GetActive(IRQn_Type IRQn)393 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
394 {
395 /* Return 1 if active else 0 */
396 return NVIC_GetActive(IRQn);
397 }
398
399 /**
400 * @brief Configure the SysTick clock source.
401 * @param CLKSource: specifies the SysTick clock source.
402 * This parameter can be one of the following values:
403 * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
404 * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
405 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
406 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
407 * @retval None
408 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)409 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
410 {
411 /* Check the parameters */
412 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
413 switch (CLKSource)
414 {
415 /* Select HCLK as Systick clock source */
416 case SYSTICK_CLKSOURCE_HCLK:
417 SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
418 break;
419 /* Select HCLK_DIV8 as Systick clock source */
420 case SYSTICK_CLKSOURCE_HCLK_DIV8:
421 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
422 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
423 break;
424 /* Select LSI as Systick clock source */
425 case SYSTICK_CLKSOURCE_LSI:
426 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
427 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
428 break;
429 /* Select LSE as Systick clock source */
430 case SYSTICK_CLKSOURCE_LSE:
431 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
432 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
433 break;
434 default:
435 /* Nothing to do */
436 break;
437 }
438 }
439
440 /**
441 * @brief Handle SYSTICK interrupt request.
442 * @retval None
443 */
HAL_SYSTICK_IRQHandler(void)444 void HAL_SYSTICK_IRQHandler(void)
445 {
446 HAL_SYSTICK_Callback();
447 }
448
449 /**
450 * @brief SYSTICK callback.
451 * @retval None
452 */
HAL_SYSTICK_Callback(void)453 __weak void HAL_SYSTICK_Callback(void)
454 {
455 /* NOTE : This function should not be modified, when the callback is needed,
456 the HAL_SYSTICK_Callback could be implemented in the user file
457 */
458 }
459
460
461 /**
462 * @brief Enable the MPU.
463 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
464 * NMI, FAULTMASK and privileged access to the default memory
465 * This parameter can be one of the following values:
466 * @arg MPU_HFNMI_PRIVDEF_NONE
467 * @arg MPU_HARDFAULT_NMI
468 * @arg MPU_PRIVILEGED_DEFAULT
469 * @arg MPU_HFNMI_PRIVDEF
470 * @retval None
471 */
HAL_MPU_Enable(uint32_t MPU_Control)472 void HAL_MPU_Enable(uint32_t MPU_Control)
473 {
474 /* Enable the MPU */
475 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
476
477 /* Enable fault exceptions */
478 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
479
480 /* Follow ARM recommendation with */
481 /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
482 __DMB(); /* Force memory writes before continuing */
483 __ISB(); /* Flush and refill pipeline with updated permissions */
484 }
485
486 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
487 /**
488 * @brief Enable the non-secure MPU.
489 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
490 * NMI, FAULTMASK and privileged access to the default memory
491 * This parameter can be one of the following values:
492 * @arg MPU_HFNMI_PRIVDEF_NONE
493 * @arg MPU_HARDFAULT_NMI
494 * @arg MPU_PRIVILEGED_DEFAULT
495 * @arg MPU_HFNMI_PRIVDEF
496 * @retval None
497 */
HAL_MPU_Enable_NS(uint32_t MPU_Control)498 void HAL_MPU_Enable_NS(uint32_t MPU_Control)
499 {
500 /* Enable the MPU */
501 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
502
503 /* Enable fault exceptions */
504 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
505
506 /* Follow ARM recommendation with */
507 /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
508 __DMB(); /* Force memory writes before continuing */
509 __ISB(); /* Flush and refill pipeline with updated permissions */
510 }
511 #endif /* __ARM_FEATURE_CMSE */
512
513 /**
514 * @brief Disable the MPU.
515 * @retval None
516 */
HAL_MPU_Disable(void)517 void HAL_MPU_Disable(void)
518 {
519 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
520
521 /* Disable the MPU */
522 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
523 }
524
525 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
526 /**
527 * @brief Disable the non-secure MPU.
528 * @retval None
529 */
HAL_MPU_Disable_NS(void)530 void HAL_MPU_Disable_NS(void)
531 {
532 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
533
534 /* Disable the MPU */
535 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
536 }
537 #endif /* __ARM_FEATURE_CMSE */
538
539 /**
540 * @brief Initialize and configure the Region and the memory to be protected.
541 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
542 * the initialization and configuration information.
543 * @retval None
544 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * const pMPU_RegionInit)545 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
546 {
547 MPU_ConfigRegion(MPU, pMPU_RegionInit);
548 }
549
550 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
551 /**
552 * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
553 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
554 * the initialization and configuration information.
555 * @retval None
556 */
HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef * const pMPU_RegionInit)557 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
558 {
559 MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
560 }
561 #endif /* __ARM_FEATURE_CMSE */
562
563 /**
564 * @brief Initialize and configure the memory attributes.
565 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
566 * the initialization and configuration information.
567 * @retval None
568 */
HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)569 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
570 {
571 MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
572 }
573
574 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
575 /**
576 * @brief Initialize and configure the memory attributes for non-secure MPU.
577 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
578 * the initialization and configuration information.
579 * @retval None
580 */
HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)581 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
582 {
583 MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
584 }
585 #endif /* __ARM_FEATURE_CMSE */
586
587 /**
588 * @}
589 */
590
591 /**
592 * @}
593 */
594
595 /** @addtogroup CORTEX_Private_Functions
596 * @{
597 */
MPU_ConfigRegion(MPU_Type * MPUx,const MPU_Region_InitTypeDef * const pMPU_RegionInit)598 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit)
599 {
600 /* Check the parameters */
601 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
602 assert_param(IS_MPU_INSTANCE(MPUx));
603 #endif /* __ARM_FEATURE_CMSE */
604 assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
605 assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
606
607 /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
608 __DMB();
609
610 /* Set the Region number */
611 MPUx->RNR = pMPU_RegionInit->Number;
612
613 if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE)
614 {
615 /* Check the parameters */
616 assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
617 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
618 assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
619
620 MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
621 ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
622 ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
623 ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
624
625 MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
626 ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
627 ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
628 }
629 else
630 {
631 MPUx->RBAR = 0U;
632 MPUx->RLAR = 0U;
633 }
634 }
635
MPU_ConfigMemoryAttributes(MPU_Type * MPUx,const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)636 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
637 {
638 __IO uint32_t *p_mair;
639 uint32_t attr_values;
640 uint32_t attr_number;
641
642 /* Check the parameters */
643 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
644 assert_param(IS_MPU_INSTANCE(MPUx));
645 #endif /* __ARM_FEATURE_CMSE */
646 assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
647 /* No need to check Attributes value as all 0x0..0xFF possible */
648
649 /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
650 __DMB();
651
652 if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
653 {
654 /* Program MPU_MAIR0 */
655 p_mair = &(MPUx->MAIR0);
656 attr_number = pMPU_AttributesInit->Number;
657 }
658 else
659 {
660 /* Program MPU_MAIR1 */
661 p_mair = &(MPUx->MAIR1);
662 attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
663 }
664
665 attr_values = *(p_mair);
666 attr_values &= ~(0xFFUL << (attr_number * 8U));
667 *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
668 }
669 /**
670 * @}
671 */
672
673 #endif /* HAL_CORTEX_MODULE_ENABLED */
674 /**
675 * @}
676 */
677
678 /**
679 * @}
680 */
681
682
