1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_ADC_EX_H 21 #define STM32U5xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 In case of ADC1 or ADC2 (if available), this parameter can be in the 50 range from 0 to 1023 51 In case of ADC4, this parameter can be a value of 52 @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 } ADC_InjOversamplingTypeDef; 57 58 /** 59 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 60 * @note Parameters of this structure are shared within 2 scopes: 61 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, 62 * InjectedOffsetNumber, InjectedOffset 63 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, 64 * InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConv, 65 * ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 66 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 67 * ADC state can be either: 68 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 69 * 'InjectedSingleDiff') 70 * - For parameters 'InjectedDiscontinuousConvMode', 'InjecOversampling': 71 * ADC enabled without conversion on going on injected group. 72 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': 73 * ADC enabled without conversion on going on regular and injected groups. 74 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 75 * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups 76 * regular and injected. 77 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 78 * without error reporting (as it can be the expected behavior in case of intended action to update another 79 * parameter (which fulfills the ADC state condition) on the fly). 80 */ 81 typedef struct 82 { 83 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 84 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 85 Note: Depending on devices and ADC instances, some channels may not be 86 available on device package pins. Refer to device datasheet for channels 87 availability. */ 88 89 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 90 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 91 Note: to disable a channel or change order of conversion sequencer, 92 rank containing a previous channel setting can be overwritten by 93 the new channel setting (or parameter number of 94 conversions adjusted) */ 95 96 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 97 Unit: ADC clock cycles. 98 Conversion time is the addition of sampling time and processing time 99 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 100 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 101 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 102 Caution: This parameter applies to a channel that can be used in a 103 regular and/or injected group. It overwrites the last setting. 104 Note: In case of usage of internal measurement channels 105 (VrefInt/Vbat/TempSensor), sampling time constraints must be 106 respected (sampling time can be adjusted in function of ADC clock 107 frequency and sampling time setting); 108 Refer to device datasheet for timings values. */ 109 110 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 111 In differential mode: Differential measurement is between the selected 112 channel 'i' (positive input) and channel 'i+1' (negative input). 113 Only channel 'i' has to be configured, channel 'i+1' is configured 114 automatically. 115 This parameter must be a value of: 116 @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 117 Caution: This parameter applies to a channel that can be used in a 118 regular and/or injected group. 119 It overwrites the last setting. 120 Note: Refer to Reference Manual to ensure the selected channel is 121 available in differential mode. 122 Note: When configuring a channel 'i' in differential mode, the channel 123 'i+1' is not usable separately. 124 Note: This parameter must be modified when ADC is disabled (before ADC 125 start conversion or after ADC stop conversion). 126 If ADC is enabled, this parameter setting is bypassed without error 127 reporting (as it can be the expected behavior in case of another parameter 128 update on the fly) */ 129 130 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 131 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 132 Caution: Only one offset is allowed per channel. This parameter overwrites 133 the last setting. */ 134 135 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 136 Offset value must be a positive number. 137 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 138 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 139 0xFF or 0x3F respectively. 140 Note: This parameter must be modified when no conversion is on going on 141 both regular and injected groups (ADC disabled, or ADC enabled 142 without continuous mode or external trigger that could launch a 143 conversion). */ 144 145 FunctionalState InjectedOffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 146 This parameter is only applied when InjectedOffsetSaturation is 147 ENABLE. 148 This parameter is applied only for 14-bit or 8-bit resolution. 149 This parameter can be set to ENABLE or DISABLE. 150 Note: 151 - If InjectedOffsetSignedSaturation is set to DISABLE the unsigned 152 saturation feature is used */ 153 154 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added 155 (positive sign) from or to the raw converted data. 156 This parameter can be a value of @ref ADCEx_OffsetSign. 157 Note: 158 - This parameter must be modified when no conversion is on going on both 159 regular and injected groups (ADC disabled, or ADC enabled without 160 continuous mode or external trigger that could launch a conversion). 161 - This parameter is specific to ADC1 only. */ 162 163 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 164 This parameter value can be ENABLE or DISABLE. 165 Note: 166 - This parameter must be modified when no conversion is on going 167 on both regular and injected groups (ADC disabled, or ADC 168 enabled without continuous mode or external trigger that could 169 launch a conversion). 170 - This parameter is specific to ADC1 only. */ 171 172 173 uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without 174 oversampling. 175 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 176 177 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within 178 the ADC group injected sequencer. 179 To use the injected group sequencer and convert several ranks, 180 parameter 'ScanConvMode' must be enabled. 181 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 182 Caution: this setting impacts the entire injected group. 183 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 184 configure a channel on injected group can impact the 185 configuration of other channels previously set. */ 186 187 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected 188 is performed in Complete-sequence/Discontinuous-sequence 189 (main sequence subdivided in successive parts). 190 Discontinuous mode is used only if sequencer is enabled 191 (parameter 'ScanConvMode'). 192 If sequencer is disabled, this parameter is discarded. 193 Discontinuous mode can be enabled only if continuous 194 mode is disabled. 195 This parameter can be set to ENABLE or DISABLE. 196 Note: This parameter must be modified when ADC is disabled 197 (before ADC start conversion or after ADC stop conversion). 198 Note: For injected group, discontinuous mode converts the 199 sequence channel by channel (discontinuous length 200 fixed to 1 rank). 201 Caution: this setting impacts the entire injected group. 202 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 203 configure a channel on injected group can impact the 204 configuration of other channels previously set. */ 205 206 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion 207 after regular one 208 This parameter can be set to ENABLE or DISABLE. 209 Note: To use Automatic injected conversion, discontinuous mode must be 210 disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' 211 set to DISABLE) 212 Note: To use Automatic injected conversion, injected group external triggers 213 must be disabled ('ExternalTrigInjecConv' set to 214 ADC_INJECTED_SOFTWARE_START) 215 Note: In case of DMA used with regular group: if DMA configured in normal 216 mode (single shot) JAUTO will be stopped upon DMA transfer complete. 217 To maintain JAUTO always enabled, 218 DMA must be configured in circular mode. 219 Caution: this setting impacts the entire injected group. 220 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 221 configure a channel on injected group can impact the configuration 222 of other channels previously set. */ 223 224 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of 225 injected group. 226 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled 227 and software trigger is used instead. 228 This parameter can be a value of @ref ADC_injected_external_trigger_source. 229 Caution: this setting impacts the entire injected group. Therefore, call of 230 HAL_ADCEx_InjectedConfigChannel() to configure a channel on 231 injected group can impact the configuration of other channels 232 previously set. */ 233 234 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 235 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 236 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter 237 is discarded. 238 Caution: this setting impacts the entire injected group. 239 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a 240 channel on injected group can impact the configuration of other 241 channels previously set. */ 242 243 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 244 This parameter can be set to ENABLE or DISABLE. 245 Note: This parameter can be modified only if there is no conversion is 246 ongoing (both ADSTART and JADSTART cleared). */ 247 248 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 249 Caution: this setting overwrites the previous oversampling 250 configuration if oversampling already enabled. 251 Note: This parameter can be modified only if there is no 252 conversion is ongoing (both ADSTART and 253 JADSTART cleared).*/ 254 } ADC_InjectionConfTypeDef; 255 256 #if defined(ADC_MULTIMODE_SUPPORT) 257 /** 258 * @brief Structure definition of ADC multimode 259 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs 260 * state (both Master and Slave ADCs). 261 * Both Master and Slave ADCs must be disabled. 262 */ 263 typedef struct 264 { 265 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 266 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 267 268 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 269 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 270 271 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 272 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 273 Delay range depends on selected resolution: 274 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 275 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 276 } ADC_MultiModeTypeDef; 277 #endif /* ADC_MULTIMODE_SUPPORT */ 278 279 /** 280 * @} 281 */ 282 283 /* Exported constants --------------------------------------------------------*/ 284 285 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 286 * @{ 287 */ 288 289 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 290 * @{ 291 */ 292 /* ADC group regular trigger sources for all ADC instances */ 293 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 294 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 295 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 296 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 297 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 298 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 299 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 300 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 301 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 302 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 303 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 304 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 305 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 306 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 307 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 308 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 309 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 310 #define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 CH2 event. Trigger edge set to rising edge (default setting). */ 311 #define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 CH2 event. Trigger edge set to rising edge (default setting). */ 312 #define ADC_EXTERNALTRIGINJEC_LPTIM3_CH1 (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */ 313 #define ADC_EXTERNALTRIGINJEC_LPTIM4_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */ 314 /** 315 * @} 316 */ 317 318 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 319 * @{ 320 */ 321 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 322 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 323 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 324 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 330 * @{ 331 */ 332 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 333 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 339 * @{ 340 */ 341 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 342 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 343 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 344 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 345 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 346 /** 347 * @} 348 */ 349 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 350 * @{ 351 */ 352 #define ADC_OFFSET_SIGN_NEGATIVE LL_ADC_OFFSET_SIGN_NEGATIVE /*!< Offset sign negative, offset is subtracted */ 353 #define ADC_OFFSET_SIGN_POSITIVE LL_ADC_OFFSET_SIGN_POSITIVE /*!< Offset sign positive, offset is added */ 354 /** 355 * @} 356 */ 357 358 359 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 360 * @{ 361 */ 362 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 363 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 364 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 365 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 366 /** 367 * @} 368 */ 369 370 #if defined(ADC_MULTIMODE_SUPPORT) 371 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 372 * @{ 373 */ 374 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 375 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 376 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 377 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 378 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 379 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 380 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 381 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 387 * @{ 388 */ 389 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 390 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 391 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 392 /** 393 * @} 394 */ 395 396 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 397 * @{ 398 */ 399 #define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */ 400 #define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */ 401 #define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 407 * @{ 408 */ 409 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 410 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 411 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 412 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 413 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 414 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 415 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 416 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 417 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 418 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 419 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 420 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 421 #define ADC_TWOSAMPLINGDELAY_13CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ 422 #define ADC_TWOSAMPLINGDELAY_14CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ 423 #define ADC_TWOSAMPLINGDELAY_15CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ 424 #define ADC_TWOSAMPLINGDELAY_16CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ 425 426 /** 427 * @} 428 */ 429 430 #endif /* ADC_MULTIMODE_SUPPORT */ 431 432 /** 433 * @} 434 */ 435 436 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 437 * @{ 438 */ 439 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 440 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 441 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 442 /** 443 * @} 444 */ 445 446 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 447 * @{ 448 */ 449 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 450 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 451 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 452 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 453 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 454 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 455 /** 456 * @} 457 */ 458 459 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 460 * @{ 461 */ 462 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 463 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 464 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 465 ADC_SMPR1_SMP0) 466 /** 467 * @} 468 */ 469 #if defined(ADC4_CFGR1_DMAEN) 470 /** @defgroup ADC4_CFGR_fields_2 ADC4 CFGR sub fields 471 * @{ 472 */ 473 /* ADC4_CFGR1 fields of parameters that can be updated when no conversion 474 (neither regular nor injected) is on-going */ 475 #define ADC4_CFGR_FIELDS_2 ((ADC4_CFGR1_DMACFG | ADC4_CFGR1_WAIT)) 476 /** 477 * @} 478 */ 479 #endif /* ADC4_CFGR1_DMAEN */ 480 481 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 482 * @{ 483 */ 484 /* ADC_CFGR1 fields of parameters that can be updated when no conversion 485 (neither regular nor injected) is on-going */ 486 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR1_DMNGT | ADC_CFGR1_AUTDLY)) 487 488 /** 489 * @} 490 */ 491 492 /* Exported macros -----------------------------------------------------------*/ 493 494 #if defined(ADC_MULTIMODE_SUPPORT) 495 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 496 * @{ 497 */ 498 499 /** @brief Force ADC instance in multimode mode independent (multimode disable). 500 * @note This macro must be used only in case of transition from multimode 501 * to mode independent and in case of unknown previous state, 502 * to ensure ADC configuration is in mode independent. 503 * @note Standard way of multimode configuration change is done from 504 * HAL ADC handle of ADC master using function 505 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 506 * Usage of this macro is not the Standard way of multimode 507 * configuration and can lead to have HAL ADC handles status 508 * misaligned. Usage of this macro must be limited to cases 509 * mentioned above. 510 * @param __HANDLE__ ADC handle. 511 * @retval None 512 */ 513 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 514 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 515 516 /** 517 * @} 518 */ 519 #endif /* ADC_MULTIMODE_SUPPORT */ 520 521 /* Private macros ------------------------------------------------------------*/ 522 523 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 524 * @{ 525 */ 526 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 527 /* code of final user. */ 528 529 /** 530 * @brief Test if conversion trigger of injected group is software start 531 * or external trigger. 532 * @param __HANDLE__ ADC handle. 533 * @retval SET (software start) or RESET (external trigger). 534 */ 535 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 536 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 537 538 /** 539 * @brief Check if conversion is on going on regular or injected groups. 540 * @param __HANDLE__ ADC handle. 541 * @retval SET (conversion is on going) or RESET (no conversion is on going). 542 */ 543 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 544 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 545 ) ? RESET : SET) 546 547 /** 548 * @brief Check if conversion is on going on injected group. 549 * @param __HANDLE__ ADC handle. 550 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 551 */ 552 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 553 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 554 555 /** 556 * @brief Check whether or not ADC is independent. 557 * @param __HANDLE__ ADC handle. 558 * @note When multimode feature is not available, the macro always returns SET. 559 * @retval SET (ADC is independent) or RESET (ADC is not). 560 */ 561 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 562 ( ( ( ((__HANDLE__)->Instance) == ADC4) \ 563 )? \ 564 SET \ 565 : \ 566 RESET \ 567 ) 568 569 /** 570 * @brief Set the selected injected Channel rank. 571 * @param __CHANNELNB__ Channel number. 572 * @param __RANKNB__ Rank number. 573 * @retval None 574 */ 575 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)& ADC_CHANNEL_ID_NUMBER_MASK)\ 576 >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__)\ 577 & ADC_INJ_RANK_ID_JSQR_MASK)) 578 579 580 /** 581 * @brief Configure ADC discontinuous conversion mode for injected group 582 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 583 * @retval None 584 */ 585 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__)\ 586 ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR1_JDISCEN_Pos) 587 588 /** 589 * @brief Configure ADC discontinuous conversion mode for regular group 590 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 591 * @retval None 592 */ 593 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR1_DISCEN_Pos) 594 595 /** 596 * @brief Configure the number of discontinuous conversions for regular group. 597 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 598 * @retval None 599 */ 600 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__)\ 601 (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR1_DISCNUM_Pos) 602 603 /** 604 * @brief Configure the ADC auto delay mode. 605 * @param __AUTOWAIT__ Auto delay bit enable or disable. 606 * @retval None 607 */ 608 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC4_CFGR1_WAIT_Pos) 609 610 /** 611 * @brief Enable the ADC auto off mode. 612 * @param _AUTOOFF_ Auto off bit enable or disable. 613 * @retval None 614 */ 615 #define ADC4_CFGR_AUTOOFF(_AUTOOFF_)((_AUTOOFF_) << ADC4_PWRR_AUTOOFF_Pos) 616 617 /** 618 * @brief Configure the ADC auto delay mode. 619 * @param __AUTDLY__ Auto delay bit enable or disable. 620 * @retval None 621 */ 622 #define ADC_CFGR_AUTODELAY(__AUTDLY__) ((__AUTDLY__) << ADC_CFGR1_AUTDLY_Pos) 623 624 /** 625 * @brief Configure ADC continuous conversion mode. 626 * @param __CONTINUOUS_MODE__ Continuous mode. 627 * @retval None 628 */ 629 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR1_CONT_Pos) 630 631 /** 632 * @brief Enable the ADC DMA continuous request. 633 * @param __HANDLE__ ADC handle. 634 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 635 * @retval None 636 */ 637 #if defined (ADC2) 638 #define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \ 639 ( (((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 640 )? \ 641 ((__DMACONTREQ_MODE__)) \ 642 : \ 643 ((__DMACONTREQ_MODE__) << 1U) \ 644 ) 645 #else 646 #define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \ 647 ( (((__HANDLE__)->Instance == ADC1) \ 648 )? \ 649 ((__DMACONTREQ_MODE__)) \ 650 : \ 651 ((__DMACONTREQ_MODE__) << 1U) \ 652 ) 653 #endif /*ADC2 */ 654 655 /** 656 * @brief Configure the channel number into offset OFRx register. 657 * @param __CHANNEL__ ADC Channel. 658 * @retval None 659 */ 660 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 661 662 /** 663 * @brief Configure the channel number into differential mode selection register. 664 * @param __CHANNEL__ ADC Channel. 665 * @retval None 666 */ 667 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 668 669 /** 670 * @brief Configure calibration factor in differential mode to be set into calibration register. 671 * @param __CALIBRATION_FACTOR__ Calibration factor value. 672 * @retval None 673 */ 674 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__)\ 675 (((__CALIBRATION_FACTOR__)& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) )\ 676 << ADC_CALFACT_CALFACT_D_Pos) 677 678 /** 679 * @brief Calibration factor in differential mode to be retrieved from calibration register. 680 * @param __CALIBRATION_FACTOR__ Calibration factor value. 681 * @retval None 682 */ 683 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 684 685 /** 686 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 687 * @param __THRESHOLD__ Threshold value. 688 * @retval None 689 */ 690 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 691 692 #if defined(ADC_MULTIMODE_SUPPORT) 693 694 695 /** 696 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with 697 * handle of ADC master. 698 * @param __HANDLE__ ADC handle. 699 * @note Return SET if multimode feature is not available. 700 * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) 701 */ 702 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 703 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \ 704 )? \ 705 SET \ 706 : \ 707 (((__LL_ADC_COMMON_INSTANCE(__HANDLE__))->CCR & ADC_CCR_DUAL) == RESET) \ 708 ) 709 710 711 /** 712 * @brief Configure the ADC DMA continuous request for ADC multimode. 713 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 714 * @retval None 715 */ 716 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 717 #endif /* ADC_MULTIMODE_SUPPORT */ 718 719 /** 720 * @brief Shift the offset in function of the selected ADC resolution. 721 * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 722 * If resolution 14 bits, no shift. 723 * If resolution 12 bits, shift of 2 ranks on the left. 724 * If resolution 10 bits, shift of 4 ranks on the left. 725 * If resolution 8 bits, shift of 6 ranks on the left. 726 * If resolution 6 bits, shift of 8 ranks on the left. 727 * therefore, shift = (14 - resolution) = 14 - (14 - (((RES[2:0]) >> 2)*2)) 728 * @param __HANDLE__: ADC handle 729 * @param __OFFSET__: Value to be shifted 730 * @retval None 731 */ 732 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 733 (((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL))) 734 735 /** 736 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 737 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 738 * If resolution 14 bits, no shift. 739 * If resolution 12 bits, shift of 2 ranks on the left. 740 * If resolution 10 bits, shift of 4 ranks on the left. 741 * If resolution 8 bits, shift of 6 ranks on the left. 742 * If resolution 6 bits, shift of 8 ranks on the left. 743 * therefore, shift = (14 - resolution) = 14 - (14- (((RES[2:0]) >> 2)*2)) 744 * @param __HANDLE__: ADC handle 745 * @param __THRESHOLD__: Value to be shifted 746 * @retval None 747 */ 748 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 749 (((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL)) ) 750 751 /** 752 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 753 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 754 * If resolution 16 bits, no shift. 755 * If resolution 14 bits, shift of 2 ranks on the left. 756 * If resolution 12 bits, shift of 4 ranks on the left. 757 * If resolution 10 bits, shift of 6 ranks on the left. 758 * If resolution 8 bits, shift of 8 ranks on the left. 759 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 760 * @param __HANDLE__: ADC handle 761 * @param __THRESHOLD__: Value to be shifted 762 * @retval None 763 */ 764 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 765 ( ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL))) 766 /** 767 * @brief Clear Common Control Register. 768 * @param __HANDLE__ ADC handle. 769 * @retval None 770 */ 771 /** 772 * @brief Report common register to ADC1 and ADC2 773 * @param __HANDLE__: ADC handle 774 * @retval Common control register 775 */ 776 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 777 /** 778 * @brief Report common register to ADC4 779 * @param __HANDLE__: ADC handle 780 * @retval Common control register 781 */ 782 #define ADC4_COMMON_REGISTER(__HANDLE__) (ADC4_COMMON) 783 /** 784 * @brief Report Master Instance 785 * @param __HANDLE__: ADC handle 786 * @note return same instance if ADC of input handle is independent ADC 787 * @retval Master Instance 788 */ 789 #define ADC_MASTER_REGISTER(__HANDLE__) \ 790 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC4)) \ 791 )? \ 792 ((__HANDLE__)->Instance) \ 793 : \ 794 (ADC1) \ 795 ) 796 797 /** 798 * @brief Check whether or not dual regular conversions are enabled 799 * @param __HANDLE__: ADC handle 800 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular 801 * conversions are enabled) 802 */ 803 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 804 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 805 )? \ 806 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 807 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 808 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 809 : \ 810 RESET \ 811 ) 812 813 /** 814 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or 815 * MultiMode with handle of ADC master 816 * @param __HANDLE__: ADC handle 817 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 818 */ 819 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 820 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 821 )? \ 822 SET \ 823 : \ 824 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 825 ) 826 827 /** 828 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or 829 * MultiMode with handle of ADC master 830 * @param __HANDLE__: ADC handle 831 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 832 */ 833 #define ADC4_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 834 ( ( ((__HANDLE__)->Instance == ADC4) \ 835 )? \ 836 SET \ 837 : \ 838 ((ADC4_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 839 ) 840 841 /** 842 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 843 * @param __HANDLE__: ADC handle 844 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or 845 * RESET (Slave ADC with dual regular conversions enabled) 846 */ 847 848 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 849 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \ 850 )? \ 851 SET \ 852 : \ 853 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 854 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 855 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 856 857 /** 858 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 859 * @param __HANDLE__: ADC handle 860 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or 861 * RESET (Slave ADC with dual injected conversions enabled) 862 */ 863 864 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 865 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \ 866 )? \ 867 SET \ 868 : \ 869 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 870 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 871 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 872 873 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) \ 874 CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_PRESC | \ 875 ADC_CCR_VBATEN | \ 876 ADC_CCR_VSENSEEN | \ 877 ADC_CCR_VREFEN ) 878 879 /** 880 * @brief Set handle instance of the ADC slave associated to the ADC master. 881 * @param __HANDLE_MASTER__ ADC master handle. 882 * @param __HANDLE_SLAVE__ ADC slave handle. 883 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, 884 * __HANDLE_SLAVE__ instance is set to NULL. 885 * @retval None 886 */ 887 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 888 ((((__HANDLE_MASTER__)->Instance == ADC1)) \ 889 ? ((__HANDLE_SLAVE__)->Instance = ADC2) \ 890 : ((__HANDLE_SLAVE__)->Instance = NULL)) 891 892 893 /** 894 * @brief Verify the ADC instance connected to the temperature sensor. 895 * @param __HANDLE__ ADC handle. 896 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 897 */ 898 #if defined(ADC2) 899 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ 900 (((__HANDLE__)->Instance) == ADC2) ||\ 901 (((__HANDLE__)->Instance) == ADC4) ) 902 #else 903 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ 904 (((__HANDLE__)->Instance) == ADC4) ) 905 #endif /* ADC2 */ 906 907 /** 908 * @brief Verify the ADC instance connected to the battery voltage VBAT. 909 * @param __HANDLE__ ADC handle. 910 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 911 */ 912 #if defined(ADC2) 913 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ 914 (((__HANDLE__)->Instance) == ADC2) ||\ 915 (((__HANDLE__)->Instance) == ADC4) ) 916 #else 917 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ 918 (((__HANDLE__)->Instance) == ADC4) ) 919 #endif /* ADC2 */ 920 921 /** 922 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 923 * @param __HANDLE__ ADC handle. 924 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 925 */ 926 #if defined(ADC2) 927 #define ADC_VREFINT_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ 928 (((__HANDLE__)->Instance) == ADC2) ||\ 929 (((__HANDLE__)->Instance) == ADC4) ) 930 #else 931 #define ADC_VREFINT_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ 932 (((__HANDLE__)->Instance) == ADC4) ) 933 #endif /* ADC2 */ 934 935 /** 936 * @brief Verify the ADC instance connected to the internal Vcore. 937 * @param __HANDLE__ ADC handle. 938 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 939 */ 940 #define ADC_VCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC4) 941 942 /** 943 * @brief Verify the length of scheduled injected conversions group. 944 * @param __LENGTH__ number of programmed conversions. 945 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or 946 * RESET (__LENGTH__ is null or too large) 947 */ 948 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 949 950 /** 951 * @brief Calibration factor size verification. 952 * @param __CALIBRATION_FACTOR__ Calibration factor value. 953 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 954 */ 955 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0xFFFFU)) 956 957 958 /** 959 * @brief Verify the ADC channel setting. 960 * @param __CHANNEL__ programmed ADC channel. 961 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 962 */ 963 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 964 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 965 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 966 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 967 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 968 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 969 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 970 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 971 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 972 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 973 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 974 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 975 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 976 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 977 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 978 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 979 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 980 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 981 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 982 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 983 ((__CHANNEL__) == ADC_CHANNEL_20) || \ 984 ((__CHANNEL__) == ADC_CHANNEL_21) || \ 985 ((__CHANNEL__) == ADC_CHANNEL_22) || \ 986 ((__CHANNEL__) == ADC_CHANNEL_23) || \ 987 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 988 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 989 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC4)|| \ 990 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC4)|| \ 991 ((__CHANNEL__) == ADC4_CHANNEL_TEMPSENSOR) || \ 992 ((__CHANNEL__) == ADC4_CHANNEL_VBAT) || \ 993 ((__CHANNEL__) == ADC_CHANNEL_VCORE) || \ 994 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 995 #if defined (ADC2) 996 /** 997 * @brief Verify the ADC channel setting in differential mode for ADC1 and ADC2. 998 * @param __CHANNEL__: programmed ADC channel. 999 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1000 */ 1001 #define IS_ADC12_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 1002 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 1003 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 1004 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 1005 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 1006 ((__CHANNEL__) == ADC_CHANNEL_6) ||\ 1007 ((__CHANNEL__) == ADC_CHANNEL_7) ||\ 1008 ((__CHANNEL__) == ADC_CHANNEL_8) ||\ 1009 ((__CHANNEL__) == ADC_CHANNEL_9) ||\ 1010 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 1011 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 1012 ( (__CHANNEL__) == ADC_CHANNEL_12) ||\ 1013 ((__CHANNEL__) == ADC_CHANNEL_13) ||\ 1014 ((__CHANNEL__) == ADC_CHANNEL_14) ||\ 1015 ((__CHANNEL__) == ADC_CHANNEL_15) ||\ 1016 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 1017 ((__CHANNEL__) == ADC_CHANNEL_17) ) 1018 #else 1019 /** 1020 * @brief Verify the ADC channel setting in differential mode for ADC1. 1021 * @param __CHANNEL__: programmed ADC channel. 1022 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1023 */ 1024 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 1025 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 1026 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 1027 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 1028 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 1029 ((__CHANNEL__) == ADC_CHANNEL_6) ||\ 1030 ((__CHANNEL__) == ADC_CHANNEL_7) ||\ 1031 ((__CHANNEL__) == ADC_CHANNEL_8) ||\ 1032 ((__CHANNEL__) == ADC_CHANNEL_9) ||\ 1033 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 1034 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 1035 ((__CHANNEL__) == ADC_CHANNEL_12) ||\ 1036 ((__CHANNEL__) == ADC_CHANNEL_13) ||\ 1037 ((__CHANNEL__) == ADC_CHANNEL_14) ||\ 1038 ((__CHANNEL__) == ADC_CHANNEL_15) ||\ 1039 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 1040 ((__CHANNEL__) == ADC_CHANNEL_17) ) 1041 #endif /* ADC2 */ 1042 1043 1044 /** 1045 * @brief Verify the ADC single-ended input or differential mode setting. 1046 * @param __SING_DIFF__ programmed channel setting. 1047 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 1048 */ 1049 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 1050 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 1051 1052 1053 /** 1054 * @brief Verify the ADC offset sign setting. 1055 * @param __OFFSET_SIGN__ ADC offset sign. 1056 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 1057 */ 1058 #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ 1059 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) 1060 /** 1061 * @brief Verify the ADC offset management setting. 1062 * @param __OFFSET_NUMBER__ ADC offset management. 1063 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 1064 */ 1065 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 1066 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 1067 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 1068 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 1069 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 1070 1071 /** 1072 * @brief Verify the ADC injected channel setting. 1073 * @param __CHANNEL__ programmed ADC injected channel. 1074 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1075 */ 1076 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 1077 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 1078 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 1079 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 1080 1081 /** 1082 * @brief Verify the ADC injected conversions external trigger. 1083 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 1084 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 1085 */ 1086 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1087 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1088 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1089 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1090 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1091 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1092 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 1093 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1094 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1095 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1096 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1097 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1098 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1099 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1100 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1101 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1102 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2) || \ 1103 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2) || \ 1104 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH1) || \ 1105 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM4_OUT) || \ 1106 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 1107 1108 /** 1109 * @brief Verify the ADC edge trigger setting for injected group. 1110 * @param __EDGE__ programmed ADC edge trigger setting. 1111 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1112 */ 1113 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1114 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1115 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1116 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1117 1118 #if defined(ADC_MULTIMODE_SUPPORT) 1119 /** 1120 * @brief Verify the ADC multimode setting. 1121 * @param __MODE__ programmed ADC multimode setting. 1122 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1123 */ 1124 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1125 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1126 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1127 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1128 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1129 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1130 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1131 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1132 1133 /** 1134 * @brief Verify the ADC dual data mode setting. 1135 * @param MODE: programmed ADC dual mode setting. 1136 * @retval SET (MODE is valid) or RESET (MODE is invalid) 1137 */ 1138 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 1139 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \ 1140 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) ) 1141 1142 /** 1143 * @brief Verify the ADC multimode delay setting. 1144 * @param __DELAY__ programmed ADC multimode delay setting. 1145 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1146 */ 1147 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1148 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1149 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1150 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1151 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1152 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1153 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1154 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1155 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 1156 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 1157 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 1158 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ 1159 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ 1160 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ 1161 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ 1162 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) ) 1163 #endif /* ADC_MULTIMODE_SUPPORT */ 1164 1165 /** 1166 * @brief Verify the ADC analog watchdog setting. 1167 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1168 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1169 */ 1170 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1171 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1172 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1173 1174 /** 1175 * @brief Verify the ADC analog watchdog mode setting. 1176 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1177 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1178 */ 1179 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1180 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1181 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1182 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)|| \ 1183 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1184 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1185 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1186 1187 /** 1188 * @brief Verify the ADC analog watchdog filtering setting. 1189 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 1190 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 1191 */ 1192 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \ 1193 (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ 1194 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ 1195 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ 1196 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ 1197 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ 1198 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ 1199 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ 1200 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) 1201 1202 1203 1204 /** 1205 * @brief Verify the ADC conversion (regular or injected or both). 1206 * @param __CONVERSION__ ADC conversion group. 1207 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1208 */ 1209 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1210 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1211 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1212 1213 /** 1214 * @brief Verify the ADC event type. 1215 * @param __EVENT__ ADC event. 1216 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1217 */ 1218 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1219 ((__EVENT__) == ADC_AWD_EVENT) || \ 1220 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1221 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1222 ((__EVENT__) == ADC_OVR_EVENT) ) 1223 1224 /** 1225 * @brief Verify the ADC oversampling ratio. 1226 * @param __RATIO__: programmed ADC oversampling ratio. 1227 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 1228 */ 1229 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) \ 1230 ((((__RATIO__) & ADC4_OVERSAMPLING_RATIO_PARAMETER) != ADC4_OVERSAMPLING_RATIO_PARAMETER) && \ 1231 ((__RATIO__) < 1024UL)) 1232 1233 /** 1234 * @brief Verify the ADC oversampling ratio. 1235 * @param __RATIO__: programmed ADC oversampling ratio. 1236 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 1237 */ 1238 #define IS_ADC4_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1239 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1240 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1241 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1242 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1243 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1244 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128) || \ 1245 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256)) 1246 /** 1247 * @brief Verify the ADC oversampling shift. 1248 * @param __SHIFT__ programmed ADC oversampling shift. 1249 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1250 */ 1251 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1252 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1253 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1254 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1255 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1256 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1257 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1258 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1259 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1260 1261 /** 1262 * @brief Verify the ADC oversampling shift. 1263 * @param __SHIFT__ programmed ADC oversampling shift. 1264 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1265 */ 1266 #define IS_ADC12_RIGHT_BIT_SHIFT( __SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1267 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1268 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1269 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1270 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1271 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1272 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1273 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1274 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ 1275 ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ 1276 ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \ 1277 ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 )) 1278 1279 /** 1280 * @brief Verify the ADC oversampling triggered mode. 1281 * @param __MODE__ programmed ADC oversampling triggered mode. 1282 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1283 */ 1284 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1285 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1286 1287 /** 1288 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1289 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1290 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1291 */ 1292 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1293 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1294 1295 /** 1296 * @} 1297 */ 1298 1299 1300 /* Exported functions --------------------------------------------------------*/ 1301 /** @addtogroup ADCEx_Exported_Functions 1302 * @{ 1303 */ 1304 1305 /** @addtogroup ADCEx_Exported_Functions_Group1 1306 * @{ 1307 */ 1308 /* IO operation functions *****************************************************/ 1309 1310 /* ADC calibration */ 1311 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, 1312 uint32_t SingleDiff); 1313 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1314 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer); 1315 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1316 uint32_t CalibrationFactor); 1317 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer); 1318 1319 /* Blocking mode: Polling */ 1320 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1321 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1322 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1323 1324 /* Non-blocking mode: Interruption */ 1325 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1326 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1327 1328 #if defined(ADC_MULTIMODE_SUPPORT) 1329 /* ADC multimode */ 1330 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); 1331 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData, 1332 uint32_t Length); 1333 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1334 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); 1335 uint32_t HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef *hadc); 1336 #endif /* ADC_MULTIMODE_SUPPORT */ 1337 1338 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1339 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1340 1341 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1342 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1343 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1344 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1345 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1346 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1347 1348 /* ADC group regular conversions stop */ 1349 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1350 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1351 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1352 #if defined(ADC_MULTIMODE_SUPPORT) 1353 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1354 #endif /* ADC_MULTIMODE_SUPPORT */ 1355 1356 /** 1357 * @} 1358 */ 1359 1360 /** @addtogroup ADCEx_Exported_Functions_Group2 1361 * @{ 1362 */ 1363 /* Peripheral Control functions ***********************************************/ 1364 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1365 ADC_InjectionConfTypeDef *pConfigInjected); 1366 #if defined(ADC_MULTIMODE_SUPPORT) 1367 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode); 1368 #endif /* ADC_MULTIMODE_SUPPORT */ 1369 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1370 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1371 1372 /** 1373 * @} 1374 */ 1375 1376 /** 1377 * @} 1378 */ 1379 1380 /** 1381 * @} 1382 */ 1383 1384 /** 1385 * @} 1386 */ 1387 1388 #ifdef __cplusplus 1389 } 1390 #endif 1391 1392 #endif /* STM32U5xx_HAL_ADC_EX_H */ 1393
