1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32U5xx_HAL_H 22 #define __STM32U5xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_conf.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup REV_ID device revision ID 75 * @{ 76 */ 77 #define REV_ID_A 0x1000U /*!< STM32U5 rev.A */ 78 #define REV_ID_B 0x2000U /*!< STM32U5 rev.B */ 79 /** 80 * @} 81 */ 82 83 84 85 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 86 * @{ 87 */ 88 89 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 90 * @{ 91 */ 92 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 93 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 94 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 95 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 96 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 97 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 98 99 /** 100 * @} 101 */ 102 103 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 104 * @{ 105 */ 106 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 107 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 108 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 109 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 110 111 /** 112 * @} 113 */ 114 115 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 116 * @{ 117 */ 118 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 119 Voltage reference buffer output */ 120 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 121 122 /** 123 * @} 124 */ 125 126 /** @defgroup SYSCFG_flags_definition Flags 127 * @{ 128 */ 129 130 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 131 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 132 133 /** 134 * @} 135 */ 136 137 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 138 * @{ 139 */ 140 141 /** @brief Fast-mode Plus driving capability on a specific GPIO 142 */ 143 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 144 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 145 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 146 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 147 148 /** 149 * @} 150 */ 151 152 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 153 * @brief SYSCFG items to set lock on 154 * @{ 155 */ 156 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 157 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 158 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 159 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 160 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 161 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 162 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 163 #else 164 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 165 #endif /* __ARM_FEATURE_CMSE */ 166 /** 167 * @} 168 */ 169 170 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 171 172 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 173 * @brief SYSCFG items to configure secure or non-secure attributes on 174 * @{ 175 */ 176 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 177 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 178 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 179 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ 180 /** 181 * @} 182 */ 183 184 /** @defgroup SYSCFG_attributes SYSCFG attributes 185 * @brief SYSCFG secure or non-secure attributes 186 * @{ 187 */ 188 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 189 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 190 /** 191 * @} 192 */ 193 194 #endif /* __ARM_FEATURE_CMSE */ 195 196 #ifdef SYSCFG_OTGHSPHYCR_EN 197 /** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection 198 * @{ 199 */ 200 201 /** @brief OTG HS PHY reference clock frequency selection 202 */ 203 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ 204 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ 205 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ 206 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ 207 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ 208 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ 209 /** 210 * @} 211 */ 212 213 /** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down 214 * @{ 215 */ 216 217 /** @brief OTG HS PHY Power Down config 218 */ 219 220 #define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ 221 #define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ 222 223 /** 224 * @} 225 */ 226 227 /** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable 228 * @{ 229 */ 230 231 #define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ 232 #define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ 233 234 /** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current 235 * @{ 236 */ 237 238 /** @brief High-speed (HS) transmitter preemphasis current control 239 */ 240 #define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ 241 #define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ 242 #define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ 243 #define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ 244 245 /** 246 * @} 247 */ 248 249 /** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold 250 * @{ 251 */ 252 253 /** @brief Squelch threshold adjustment 254 */ 255 #define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ 256 #define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ 257 258 /** 259 * @} 260 */ 261 262 /** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold 263 * @{ 264 */ 265 266 /** @brief Disconnect threshold adjustment 267 */ 268 #define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ 269 #define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ 270 271 /** 272 * @} 273 */ 274 #endif /* SYSCFG_OTGHSPHYCR_EN */ 275 /** 276 * @} 277 */ 278 279 /* Exported macros -----------------------------------------------------------*/ 280 281 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 282 * @{ 283 */ 284 285 /** @brief Freeze/Unfreeze Peripherals in Debug mode 286 */ 287 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 288 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 289 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 290 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 291 292 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 293 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 294 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 295 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 296 297 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 298 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 299 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 300 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 301 302 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 303 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 304 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 305 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ 306 307 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 308 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 309 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 310 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 311 312 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 313 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 314 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 315 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 316 317 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 318 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 319 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 320 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 321 322 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 323 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 324 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 325 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 326 327 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 328 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 329 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 330 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 331 332 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 333 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 334 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 335 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 336 337 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 338 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 339 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 340 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ 341 342 #if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) 343 #define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) 344 #define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) 345 #endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ 346 347 #if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) 348 #define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) 349 #define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) 350 #endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ 351 352 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 353 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 354 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 355 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 356 357 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 358 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 359 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 360 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 361 362 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 363 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 364 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 365 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 366 367 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 368 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 369 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 370 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 371 372 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 373 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 374 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 375 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 376 377 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 378 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 379 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 380 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 381 382 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 383 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 384 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 385 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 386 387 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 388 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 389 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 390 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 391 392 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 393 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 394 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 395 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 396 397 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 398 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 399 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 400 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 401 402 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 403 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 404 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 405 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 406 407 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 408 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 409 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 410 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */ 411 412 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 413 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 414 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 415 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */ 416 417 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 418 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 419 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 420 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */ 421 422 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 423 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 424 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 425 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */ 426 427 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 428 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 429 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 430 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */ 431 432 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 433 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 434 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 435 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */ 436 437 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 438 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 439 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 440 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */ 441 442 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 443 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 444 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 445 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */ 446 447 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 448 #define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 449 #define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 450 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */ 451 452 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 453 #define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 454 #define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 455 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */ 456 457 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 458 #define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 459 #define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 460 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */ 461 462 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 463 #define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 464 #define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 465 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */ 466 467 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 468 #define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 469 #define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 470 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */ 471 472 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 473 #define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 474 #define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 475 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */ 476 477 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 478 #define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 479 #define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 480 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */ 481 482 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 483 #define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 484 #define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 485 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */ 486 487 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 488 #define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 489 #define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 490 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */ 491 492 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 493 #define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 494 #define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 495 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */ 496 497 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 498 #define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 499 #define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 500 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */ 501 502 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 503 #define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 504 #define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 505 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */ 506 507 /** 508 * @} 509 */ 510 511 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 512 * @{ 513 */ 514 515 /** @brief Floating Point Unit interrupt enable/disable macros 516 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 517 */ 518 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 519 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 520 }while(0) 521 522 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 523 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 524 }while(0) 525 526 /** @brief SYSCFG Break ECC lock. 527 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 528 * @note The selected configuration is locked and can be unlocked only by system reset. 529 */ 530 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 531 532 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 533 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 534 * @note The selected configuration is locked and can be unlocked only by system reset. 535 */ 536 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 537 538 /** @brief SYSCFG Break PVD lock. 539 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in 540 * the PWR_CR2 register. 541 * @note The selected configuration is locked and can be unlocked only by system reset. 542 */ 543 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 544 545 /** @brief SYSCFG Break SRAM2 parity lock. 546 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 547 * @note The selected configuration is locked and can be unlocked by system reset. 548 */ 549 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 550 551 /** @brief Check SYSCFG flag is set or not. 552 * @param __FLAG__: specifies the flag to check. 553 * This parameter can be one of the following values: 554 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 555 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 556 * @retval The new state of __FLAG__ (TRUE or FALSE). 557 */ 558 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ 559 & (__FLAG__))!= 0) ? 1 : 0) 560 561 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 562 */ 563 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 564 565 /** @brief Fast-mode Plus driving capability enable/disable macros 566 * @param __FASTMODEPLUS__: This parameter can be a value of : 567 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 568 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 569 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 570 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 571 */ 572 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 573 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 574 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 575 }while(0) 576 577 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 578 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 579 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 580 }while(0) 581 582 /** 583 * @} 584 */ 585 586 /* Private macros ------------------------------------------------------------*/ 587 588 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 589 * @{ 590 */ 591 592 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 593 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 594 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 595 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 596 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 597 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 598 599 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 600 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 601 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 602 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 603 604 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 605 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 606 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ 607 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) 608 609 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 610 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 611 612 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 613 614 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 615 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 616 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 617 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 618 619 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 620 621 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 622 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 623 624 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ 625 (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ 626 (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ 627 (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) 628 629 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 630 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 631 (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ 632 (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ 633 (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ 634 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 635 636 #else 637 638 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 639 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 640 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 641 642 643 #endif /* __ARM_FEATURE_CMSE */ 644 645 #ifdef SYSCFG_OTGHSPHYCR_EN 646 #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ 647 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ 648 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ 649 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ 650 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ 651 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) 652 653 #define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ 654 ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) 655 656 #define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ 657 ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) 658 659 #define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ 660 ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) 661 662 #define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ 663 ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) 664 665 #define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ 666 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ 667 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ 668 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) 669 #endif /* SYSCFG_OTGHSPHYCR_EN */ 670 671 /** 672 * @} 673 */ 674 675 /** @defgroup HAL_Private_Macros HAL Private Macros 676 * @{ 677 */ 678 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 679 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 680 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 681 /** 682 * @} 683 */ 684 /* Exported functions --------------------------------------------------------*/ 685 686 /** @addtogroup HAL_Exported_Functions 687 * @{ 688 */ 689 690 /** @addtogroup HAL_Exported_Functions_Group1 691 * @{ 692 */ 693 694 /* Initialization and de-initialization functions ******************************/ 695 HAL_StatusTypeDef HAL_Init(void); 696 HAL_StatusTypeDef HAL_DeInit(void); 697 void HAL_MspInit(void); 698 void HAL_MspDeInit(void); 699 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 700 701 /** 702 * @} 703 */ 704 705 /** @addtogroup HAL_Exported_Functions_Group2 706 * @{ 707 */ 708 709 /* Peripheral Control functions ************************************************/ 710 void HAL_IncTick(void); 711 void HAL_Delay(uint32_t Delay); 712 uint32_t HAL_GetTick(void); 713 uint32_t HAL_GetTickPrio(void); 714 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 715 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 716 void HAL_SuspendTick(void); 717 void HAL_ResumeTick(void); 718 uint32_t HAL_GetHalVersion(void); 719 uint32_t HAL_GetREVID(void); 720 uint32_t HAL_GetDEVID(void); 721 uint32_t HAL_GetUIDw0(void); 722 uint32_t HAL_GetUIDw1(void); 723 uint32_t HAL_GetUIDw2(void); 724 725 /** 726 * @} 727 */ 728 729 /** @addtogroup HAL_Exported_Functions_Group3 730 * @{ 731 */ 732 733 /* DBGMCU Peripheral Control functions *****************************************/ 734 void HAL_DBGMCU_EnableDBGStopMode(void); 735 void HAL_DBGMCU_DisableDBGStopMode(void); 736 void HAL_DBGMCU_EnableDBGStandbyMode(void); 737 void HAL_DBGMCU_DisableDBGStandbyMode(void); 738 739 /** 740 * @} 741 */ 742 743 /** @addtogroup HAL_Exported_Functions_Group4 744 * @{ 745 */ 746 747 /* SYSCFG Control functions ****************************************************/ 748 void HAL_SYSCFG_SRAM2Erase(void); 749 750 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 751 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 752 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 753 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 754 void HAL_SYSCFG_DisableVREFBUF(void); 755 #ifdef SYSCFG_OTGHSPHYCR_EN 756 void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); 757 void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); 758 void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); 759 void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); 760 void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); 761 void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); 762 #endif /* SYSCFG_OTGHSPHYCR_EN */ 763 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 764 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 765 void HAL_SYSCFG_EnableSRAMCached(void); 766 void HAL_SYSCFG_DisableSRAMCached(void); 767 void HAL_SYSCFG_EnableVddCompensationCell(void); 768 void HAL_SYSCFG_EnableVddIO2CompensationCell(void); 769 #if defined(SYSCFG_CCCSR_EN3) 770 void HAL_SYSCFG_EnableVddHSPICompensationCell(void); 771 #endif /* SYSCFG_CCCSR_EN3 */ 772 void HAL_SYSCFG_DisableVddCompensationCell(void); 773 void HAL_SYSCFG_DisableVddIO2CompensationCell(void); 774 #if defined(SYSCFG_CCCSR_EN3) 775 void HAL_SYSCFG_DisableVddHSPICompensationCell(void); 776 #endif /* SYSCFG_CCCSR_EN3 */ 777 /** 778 * @} 779 */ 780 781 /** @addtogroup HAL_Exported_Functions_Group5 782 * @{ 783 */ 784 785 /* SYSCFG Lock functions ********************************************/ 786 void HAL_SYSCFG_Lock(uint32_t Item); 787 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 788 789 /** 790 * @} 791 */ 792 793 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 794 795 /** @addtogroup HAL_Exported_Functions_Group6 796 * @{ 797 */ 798 799 /* SYSCFG Attributes functions ********************************************/ 800 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 801 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 802 803 /** 804 * @} 805 */ 806 807 #endif /* __ARM_FEATURE_CMSE */ 808 809 /** 810 * @} 811 */ 812 813 /** 814 * @} 815 */ 816 817 /** 818 * @} 819 */ 820 821 /** 822 * @} 823 */ 824 825 #ifdef __cplusplus 826 } 827 #endif 828 829 #endif /* __STM32U5xx_HAL_H */ 830
