1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_RNG_H
21 #define STM32U0xx_LL_RNG_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (RNG)
35
36 /** @defgroup RNG_LL RNG
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /* Exported types ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
49 * @{
50 */
51
52
53 /**
54 * @brief LL RNG Init Structure Definition
55 */
56 typedef struct
57 {
58 uint32_t ClockErrorDetection; /*!< Clock error detection.
59 This parameter can be one value of @ref RNG_LL_CED.
60 This parameter can be modified using unitary
61 functions @ref LL_RNG_EnableClkErrorDetect(). */
62 } LL_RNG_InitTypeDef;
63
64 /**
65 * @}
66 */
67 #endif /* USE_FULL_LL_DRIVER */
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
70 * @{
71 */
72
73 /** @defgroup RNG_LL_CED Clock Error Detection
74 * @{
75 */
76 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
77 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
78 /**
79 * @}
80 */
81 /** @defgroup RNG_LL_ARDIS Auto reset disable
82 * @{
83 */
84 #define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/
85 #define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/
86 /**
87 * @}
88 */
89
90 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
91 * programmable divider acting on the incoming RNG clock
92 * @{
93 */
94 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
95 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
96 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
97 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
98 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
99 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
100 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
101 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
102 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
103 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
104 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
105 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
106 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
107 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
108 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
109 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
110 /**
111 * @}
112 */
113
114 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
115 * @{
116 */
117 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
118 #define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
119
120 /**
121 * @}
122 */
123
124 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
125 * @brief Flags defines which can be used with LL_RNG_ReadReg function
126 * @{
127 */
128 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
129 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
130 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
131 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
132 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
133 /**
134 * @}
135 */
136
137 /** @defgroup RNG_LL_EC_IT IT Defines
138 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
139 * @{
140 */
141 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
142 /**
143 * @}
144 */
145
146 /**
147 * @}
148 */
149
150 /* Exported macro ------------------------------------------------------------*/
151 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
152 * @{
153 */
154
155 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
156 * @{
157 */
158
159 /**
160 * @brief Write a value in RNG register
161 * @param __INSTANCE__ RNG Instance
162 * @param __REG__ Register to be written
163 * @param __VALUE__ Value to be written in the register
164 * @retval None
165 */
166 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
167
168 /**
169 * @brief Read a value in RNG register
170 * @param __INSTANCE__ RNG Instance
171 * @param __REG__ Register to be read
172 * @retval Register value
173 */
174 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
175 /**
176 * @}
177 */
178
179 /**
180 * @}
181 */
182
183
184 /* Exported functions --------------------------------------------------------*/
185 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
186 * @{
187 */
188 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
189 * @{
190 */
191
192 /**
193 * @brief Enable Random Number Generation
194 * @rmtoll CR RNGEN LL_RNG_Enable
195 * @param RNGx RNG Instance
196 * @retval None
197 */
LL_RNG_Enable(RNG_TypeDef * RNGx)198 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
199 {
200 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
201 }
202
203 /**
204 * @brief Disable Random Number Generation
205 * @rmtoll CR RNGEN LL_RNG_Disable
206 * @param RNGx RNG Instance
207 * @retval None
208 */
LL_RNG_Disable(RNG_TypeDef * RNGx)209 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
210 {
211 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
212 }
213
214 /**
215 * @brief Check if Random Number Generator is enabled
216 * @rmtoll CR RNGEN LL_RNG_IsEnabled
217 * @param RNGx RNG Instance
218 * @retval State of bit (1 or 0).
219 */
LL_RNG_IsEnabled(const RNG_TypeDef * RNGx)220 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
221 {
222 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
223 }
224
225 /**
226 * @brief Enable Clock Error Detection
227 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
228 * @param RNGx RNG Instance
229 * @retval None
230 */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)231 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
232 {
233 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
234 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
235 }
236
237 /**
238 * @brief Disable RNG Clock Error Detection
239 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
240 * @param RNGx RNG Instance
241 * @retval None
242 */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)243 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
244 {
245 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
246 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
247 }
248
249 /**
250 * @brief Check if RNG Clock Error Detection is enabled
251 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
252 * @param RNGx RNG Instance
253 * @retval State of bit (1 or 0).
254 */
LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef * RNGx)255 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
256 {
257 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
258 }
259
260 /**
261 * @brief Set RNG Conditioning Soft Reset bit
262 * @rmtoll CR CONDRST LL_RNG_EnableCondReset
263 * @param RNGx RNG Instance
264 * @retval None
265 */
LL_RNG_EnableCondReset(RNG_TypeDef * RNGx)266 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
267 {
268 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
269 }
270
271 /**
272 * @brief Reset RNG Conditioning Soft Reset bit
273 * @rmtoll CR CONDRST LL_RNG_DisableCondReset
274 * @param RNGx RNG Instance
275 * @retval None
276 */
LL_RNG_DisableCondReset(RNG_TypeDef * RNGx)277 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
278 {
279 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
280 }
281
282 /**
283 * @brief Check if RNG Conditioning Soft Reset bit is set
284 * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
285 * @param RNGx RNG Instance
286 * @retval State of bit (1 or 0).
287 */
LL_RNG_IsEnabledCondReset(const RNG_TypeDef * RNGx)288 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
289 {
290 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
291 }
292
293 /**
294 * @brief Enable RNG Config Lock
295 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
296 * @param RNGx RNG Instance
297 * @retval None
298 */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)299 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
300 {
301 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
302 }
303
304 /**
305 * @brief Check if RNG Config Lock is enabled
306 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
307 * @param RNGx RNG Instance
308 * @retval State of bit (1 or 0).
309 */
LL_RNG_IsConfigLocked(const RNG_TypeDef * RNGx)310 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
311 {
312 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
313 }
314
315 /**
316 * @brief Enable NIST Compliance
317 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
318 * @param RNGx RNG Instance
319 * @retval None
320 */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)321 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
322 {
323 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
324 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
325 }
326
327 /**
328 * @brief Disable NIST Compliance
329 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
330 * @param RNGx RNG Instance
331 * @retval None
332 */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)333 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
334 {
335 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
336 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
337 }
338
339 /**
340 * @brief Check if NIST Compliance is enabled
341 * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
342 * @param RNGx RNG Instance
343 * @retval State of bit (1 or 0).
344 */
LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef * RNGx)345 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
346 {
347 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
348 }
349
350 /**
351 * @brief Set RNG Config1 Configuration field value
352 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
353 * @param RNGx RNG Instance
354 * @param Config1 Value between 0 and 0x3F
355 * @retval None
356 */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)357 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
358 {
359 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
360 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
361 }
362
363 /**
364 * @brief Get RNG Config1 Configuration field value
365 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
366 * @param RNGx RNG Instance
367 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
368 */
LL_RNG_GetConfig1(const RNG_TypeDef * RNGx)369 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
370 {
371 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
372 }
373
374 /**
375 * @brief Set RNG Config2 Configuration field value
376 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
377 * @param RNGx RNG Instance
378 * @param Config2 Value between 0 and 0x7
379 * @retval None
380 */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)381 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
382 {
383 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
384 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
385 }
386
387 /**
388 * @brief Get RNG Config2 Configuration field value
389 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
390 * @param RNGx RNG Instance
391 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
392 */
LL_RNG_GetConfig2(const RNG_TypeDef * RNGx)393 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
394 {
395 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
396 }
397
398 /**
399 * @brief Set RNG Config3 Configuration field value
400 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
401 * @param RNGx RNG Instance
402 * @param Config3 Value between 0 and 0xF
403 * @retval None
404 */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)405 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
406 {
407 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
408 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
409 }
410
411 /**
412 * @brief Get RNG Config3 Configuration field value
413 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
414 * @param RNGx RNG Instance
415 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
416 */
LL_RNG_GetConfig3(const RNG_TypeDef * RNGx)417 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
418 {
419 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
420 }
421
422 /**
423 * @brief Set RNG Clock divider factor
424 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
425 * @param RNGx RNG Instance
426 * @param Divider can be one of the following values:
427 * @arg @ref LL_RNG_CLKDIV_BY_1
428 * @arg @ref LL_RNG_CLKDIV_BY_2
429 * @arg @ref LL_RNG_CLKDIV_BY_4
430 * @arg @ref LL_RNG_CLKDIV_BY_8
431 * @arg @ref LL_RNG_CLKDIV_BY_16
432 * @arg @ref LL_RNG_CLKDIV_BY_32
433 * @arg @ref LL_RNG_CLKDIV_BY_64
434 * @arg @ref LL_RNG_CLKDIV_BY_128
435 * @arg @ref LL_RNG_CLKDIV_BY_256
436 * @arg @ref LL_RNG_CLKDIV_BY_512
437 * @arg @ref LL_RNG_CLKDIV_BY_1024
438 * @arg @ref LL_RNG_CLKDIV_BY_2048
439 * @arg @ref LL_RNG_CLKDIV_BY_4096
440 * @arg @ref LL_RNG_CLKDIV_BY_8192
441 * @arg @ref LL_RNG_CLKDIV_BY_16384
442 * @arg @ref LL_RNG_CLKDIV_BY_32768
443 * @retval None
444 */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)445 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
446 {
447 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
448 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
449 }
450
451 /**
452 * @brief Get RNG Clock divider factor
453 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
454 * @param RNGx RNG Instance
455 * @retval Returned value can be one of the following values:
456 * @arg @ref LL_RNG_CLKDIV_BY_1
457 * @arg @ref LL_RNG_CLKDIV_BY_2
458 * @arg @ref LL_RNG_CLKDIV_BY_4
459 * @arg @ref LL_RNG_CLKDIV_BY_8
460 * @arg @ref LL_RNG_CLKDIV_BY_16
461 * @arg @ref LL_RNG_CLKDIV_BY_32
462 * @arg @ref LL_RNG_CLKDIV_BY_64
463 * @arg @ref LL_RNG_CLKDIV_BY_128
464 * @arg @ref LL_RNG_CLKDIV_BY_256
465 * @arg @ref LL_RNG_CLKDIV_BY_512
466 * @arg @ref LL_RNG_CLKDIV_BY_1024
467 * @arg @ref LL_RNG_CLKDIV_BY_2048
468 * @arg @ref LL_RNG_CLKDIV_BY_4096
469 * @arg @ref LL_RNG_CLKDIV_BY_8192
470 * @arg @ref LL_RNG_CLKDIV_BY_16384
471 * @arg @ref LL_RNG_CLKDIV_BY_32768
472 */
LL_RNG_GetClockDivider(const RNG_TypeDef * RNGx)473 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
474 {
475 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
476 }
477 /**
478 * @}
479 */
480
481 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
482 * @{
483 */
484
485 /**
486 * @brief Indicate if the RNG Data ready Flag is set or not
487 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
488 * @param RNGx RNG Instance
489 * @retval State of bit (1 or 0).
490 */
LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef * RNGx)491 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
492 {
493 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
494 }
495
496 /**
497 * @brief Indicate if the Clock Error Current Status Flag is set or not
498 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
499 * @param RNGx RNG Instance
500 * @retval State of bit (1 or 0).
501 */
LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef * RNGx)502 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
503 {
504 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
505 }
506
507 /**
508 * @brief Indicate if the Seed Error Current Status Flag is set or not
509 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
510 * @param RNGx RNG Instance
511 * @retval State of bit (1 or 0).
512 */
LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef * RNGx)513 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
514 {
515 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
516 }
517
518 /**
519 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
520 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
521 * @param RNGx RNG Instance
522 * @retval State of bit (1 or 0).
523 */
LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef * RNGx)524 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
525 {
526 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
527 }
528
529 /**
530 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
531 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
532 * @param RNGx RNG Instance
533 * @retval State of bit (1 or 0).
534 */
LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef * RNGx)535 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
536 {
537 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
538 }
539
540 /**
541 * @brief Clear Clock Error interrupt Status (CEIS) Flag
542 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
543 * @param RNGx RNG Instance
544 * @retval None
545 */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)546 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
547 {
548 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
549 }
550
551 /**
552 * @brief Clear Seed Error interrupt Status (SEIS) Flag
553 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
554 * @param RNGx RNG Instance
555 * @retval None
556 */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)557 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
558 {
559 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
560 }
561
562 /**
563 * @}
564 */
565
566 /** @defgroup RNG_LL_EF_IT_Management IT Management
567 * @{
568 */
569
570 /**
571 * @brief Enable Random Number Generator Interrupt
572 * (applies for either Seed error, Clock Error or Data ready interrupts)
573 * @rmtoll CR IE LL_RNG_EnableIT
574 * @param RNGx RNG Instance
575 * @retval None
576 */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)577 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
578 {
579 SET_BIT(RNGx->CR, RNG_CR_IE);
580 }
581
582 /**
583 * @brief Disable Random Number Generator Interrupt
584 * (applies for either Seed error, Clock Error or Data ready interrupts)
585 * @rmtoll CR IE LL_RNG_DisableIT
586 * @param RNGx RNG Instance
587 * @retval None
588 */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)589 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
590 {
591 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
592 }
593
594 /**
595 * @brief Check if Random Number Generator Interrupt is enabled
596 * (applies for either Seed error, Clock Error or Data ready interrupts)
597 * @rmtoll CR IE LL_RNG_IsEnabledIT
598 * @param RNGx RNG Instance
599 * @retval State of bit (1 or 0).
600 */
LL_RNG_IsEnabledIT(const RNG_TypeDef * RNGx)601 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
602 {
603 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
604 }
605
606 /**
607 * @}
608 */
609
610 /** @defgroup RNG_LL_EF_Data_Management Data Management
611 * @{
612 */
613
614 /**
615 * @brief Return32-bit Random Number value
616 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
617 * @param RNGx RNG Instance
618 * @retval Generated 32-bit random value
619 */
LL_RNG_ReadRandData32(const RNG_TypeDef * RNGx)620 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
621 {
622 return (uint32_t)(READ_REG(RNGx->DR));
623 }
624
625 /**
626 * @}
627 */
628
629 /**
630 * @brief Enable Auto reset
631 * @rmtoll CR ARDIS LL_RNG_EnableArdis
632 * @param RNGx RNG Instance
633 * @retval None
634 */
LL_RNG_EnableArdis(RNG_TypeDef * RNGx)635 __STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx)
636 {
637 MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST);
638 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
639 }
640
641 /**
642 * @brief Disable Auto reset
643 * @rmtoll CR ARDIS LL_RNG_DisableArdis
644 * @param RNGx RNG Instance
645 * @retval None
646 */
LL_RNG_DisableArdis(RNG_TypeDef * RNGx)647 __STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx)
648 {
649 MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST);
650 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
651 }
652
653 /**
654 * @brief Check if RNG Auto reset is enabled
655 * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis
656 * @param RNGx RNG Instance
657 * @retval State of bit (1 or 0).
658 */
LL_RNG_IsEnabledArdis(const RNG_TypeDef * RNGx)659 __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx)
660 {
661 return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL);
662 }
663
664 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
665 * @{
666 */
667
668 /**
669 * @brief Set RNG Health Test Control
670 * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
671 * @param RNGx RNG Instance
672 * @param HTCFG can be values of 32 bits
673 * @retval None
674 */
LL_RNG_SetHealthConfig(RNG_TypeDef * RNGx,uint32_t HTCFG)675 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
676 {
677 WRITE_REG(RNGx->HTCR, HTCFG);
678 }
679
680 /**
681 * @brief Get RNG Health Test Control
682 * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
683 * @param RNGx RNG Instance
684 * @retval Return 32-bit RNG Health Test configuration
685 */
LL_RNG_GetHealthConfig(const RNG_TypeDef * RNGx)686 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx)
687 {
688 return (uint32_t)READ_REG(RNGx->HTCR);
689 }
690
691 /**
692 * @}
693 */
694 #if defined(USE_FULL_LL_DRIVER)
695 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
696 * @{
697 */
698 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct);
699 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
700 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
701
702 /**
703 * @}
704 */
705 #endif /* USE_FULL_LL_DRIVER */
706
707 /**
708 * @}
709 */
710
711 /**
712 * @}
713 */
714
715 #endif /* RNG */
716
717 /**
718 * @}
719 */
720
721 #ifdef __cplusplus
722 }
723 #endif
724
725 #endif /* __STM32U0xx_LL_RNG_H */
726
727
