1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32U0xx_LL_RCC_H
21 #define __STM32U0xx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43
44 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
45 * @{
46 */
47 /* Defines used to perform offsets*/
48 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
49 #define RCC_OFFSET_CCIPR 0U
50
51 /**
52 * @}
53 */
54
55 /* Private macros ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
58 * @{
59 */
60 /**
61 * @}
62 */
63 #endif /*USE_FULL_LL_DRIVER*/
64
65 /* Exported types ------------------------------------------------------------*/
66 #if defined(USE_FULL_LL_DRIVER)
67 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
68 * @{
69 */
70
71 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
72 * @{
73 */
74
75 /**
76 * @brief RCC Clocks Frequency Structure
77 */
78 typedef struct
79 {
80 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
81 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
82 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
83 } LL_RCC_ClocksTypeDef;
84
85 /**
86 * @}
87 */
88
89 /**
90 * @}
91 */
92 #endif /* USE_FULL_LL_DRIVER */
93
94 /* Exported constants --------------------------------------------------------*/
95 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
96 * @{
97 */
98
99 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
100 * @brief Defines used to adapt values of different oscillators
101 * @note These values could be modified in the user environment according to
102 * HW set-up.
103 * @{
104 */
105 #if !defined (HSE_VALUE)
106 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
107 #endif /* HSE_VALUE */
108
109 #if !defined (HSI_VALUE)
110 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
111 #endif /* HSI_VALUE */
112
113 #if !defined (LSE_VALUE)
114 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
115 #endif /* LSE_VALUE */
116
117 #if !defined (LSI_VALUE)
118 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
119 #endif /* LSI_VALUE */
120
121 #if !defined (HSI48_VALUE)
122 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
123 #endif /* HSI48_VALUE */
124 /**
125 * @}
126 */
127
128 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
129 * @brief Flags defines which can be used with LL_RCC_WriteReg function
130 * @{
131 */
132 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
133 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
134 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
135 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
136 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
137 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
138 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
139 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
140 #if defined(RCC_CRRCR_HSI48ON)
141 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Clock Security System Interrupt Clear */
142 #endif /* RCC_CRRCR_HSI48ON */
143 /**
144 * @}
145 */
146
147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_RCC_ReadReg function
149 * @{
150 */
151 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
152 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
153 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
154 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
155 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
156 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
157 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */
158 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
159 #if defined(RCC_CRRCR_HSI48ON)
160 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
161 #endif /* RCC_CRRCR_HSI48ON */
162 #define LL_RCC_CSR_RMVF RCC_CSR_RMVF /*!< Low-Power reset flag */
163 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
164 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
165 #define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< PWR reset flag */
166 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
167 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
168 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
169 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
170 /**
171 * @}
172 */
173
174 /** @defgroup RCC_LL_EC_IT IT Defines
175 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
176 * @{
177 */
178 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
179 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
180 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
181 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
182 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
183 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
184 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
185 #if defined(RCC_CRRCR_HSI48ON)
186 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
187 #endif /* RCC_CRRCR_HSI48ON */
188 /**
189 * @}
190 */
191
192 /** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
193 * @{
194 */
195 #define LL_RCC_LSI_DIV_1 0UL /*!< LSI divided by 1 */
196 #define LL_RCC_LSI_DIV_128 RCC_CSR_LSIPREDIV /*!< LSI divided by 128 */
197 /**
198 * @}
199 */
200
201 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
202 * @{
203 */
204 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
205 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
206 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
207 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
208 /**
209 * @}
210 */
211
212 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
213 * @{
214 */
215 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
216 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
217 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
218 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
219 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
220 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
221 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
222 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
223 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
224 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
225 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
226 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
227 /**
228 * @}
229 */
230
231 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
232 * @{
233 */
234 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISTBYRG_1 /*!< MSI = 1 MHz */
235 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISTBYRG_2 /*!< MSI = 2 MHz */
236 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISTBYRG_4 /*!< MSI = 4 MHz */
237 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISTBYRG_8 /*!< MSI = 8 MHz */
238 /**
239 * @}
240 */
241
242 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
243 * @{
244 */
245 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
246 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
247 /**
248 * @}
249 */
250
251 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
252 * @{
253 */
254 #define LL_RCC_SYS_CLKSOURCE_MSI (0x00000000U) /*!< MSI selection as system clock */
255 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
256 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
257 #define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
258 #define LL_RCC_SYS_CLKSOURCE_LSI RCC_CFGR_SW_2 /*!< LSI selection as system clock */
259 #define LL_RCC_SYS_CLKSOURCE_LSE (RCC_CFGR_SW_2 |RCC_CFGR_SW_0) /*!< LSE selection as system clock */
260 /**
261 * @}
262 */
263
264 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
265 * @{
266 */
267 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI (0x00000000U) /*!< MSI used as system clock */
268 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
269 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
270 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
271 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI RCC_CFGR_SWS_2 /*!< LSI used as system clock */
272 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE (RCC_CFGR_SWS_2 |RCC_CFGR_SWS_0) /*!< LSE used as system clock */
273 /**
274 * @}
275 */
276
277 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
278 * @{
279 */
280 #define LL_RCC_SYSCLK_DIV_1 (0x00000000U) /*!< SYSCLK not divided */
281 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
282 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
283 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
284 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
285 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
286 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
287 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
288 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
289 /**
290 * @}
291 */
292
293 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
294 * @{
295 */
296 #define LL_RCC_APB1_DIV_1 (0x00000000U) /*!< APB not divided */
297 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< APB divided by 2 */
298 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< APB divided by 4 */
299 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< APB divided by 8 */
300 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< APB divided by 16 */
301 /**
302 * @}
303 */
304
305 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
306 * @{
307 */
308 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
309 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
310 /**
311 * @}
312 */
313
314 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
315 * @{
316 */
317 #define LL_RCC_MCO1SOURCE_NOCLOCK (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | 0x00000000U) /*!< MCO output disabled, no clock on MCO */
318 #define LL_RCC_MCO1SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_0) /*!< SYSCLK selection as MCO1 source */
319 #define LL_RCC_MCO1SOURCE_MSI (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_1) /*!< MSI selection as MCO1 source */
320 #define LL_RCC_MCO1SOURCE_HSI16 (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_1 |\
321 RCC_CFGR_MCO1SEL_0) /*!< HSI16 selection as MCO1 source */
322 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_2) /*!< HSE selection as MCO1 source */
323 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_2 |\
324 RCC_CFGR_MCO1SEL_0) /*!< Main PLL selection as MCO1 source */
325 #define LL_RCC_MCO1SOURCE_LSI (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_2 |\
326 RCC_CFGR_MCO1SEL_1) /*!< LSI selection as MCO1 source */
327 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_2 |\
328 RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_0) /*!< LSE selection as MCO1 source */
329 #if defined(RCC_CRRCR_HSI48ON)
330 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_3) /*!< HSI48 selection as MCO1 source */
331 #endif /* RCC_CRRCR_HSI48ON */
332 #define LL_RCC_MCO1SOURCE_RTC (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_3 |\
333 RCC_CFGR_MCO1SEL_0) /*!< RTC alter clk selection as MCO1 source */
334 #define LL_RCC_MCO1SOURCE_RTCWUPI (uint32_t)((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_3 |\
335 RCC_CFGR_MCO1SEL_1) /*!< RTC wakeup interrupt signal selection as MCO1 source */
336 /**
337 * @}
338 */
339
340 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
341 * @{
342 */
343
344 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | 0x00000000U) /*!< MCO not divided */
345
346 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 2 */
347 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 4 */
348 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 |\
349 RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 8 */
350 #define LL_RCC_MCO1_DIV_16 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) /*!< MCO divided by 16 */
351 #define LL_RCC_MCO1_DIV_32 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 |\
352 RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 32 */
353 #define LL_RCC_MCO1_DIV_64 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 |\
354 RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 64 */
355 #define LL_RCC_MCO1_DIV_128 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 |\
356 RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 128 */
357 #define LL_RCC_MCO1_DIV_256 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) /*!< MCO divided by 256 */
358 #define LL_RCC_MCO1_DIV_512 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3 |\
359 RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 512 */
360 #define LL_RCC_MCO1_DIV_1024 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3 |\
361 RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 1024 */
362 /**
363 * @}
364 */
365
366 /** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection
367 * @{
368 */
369 #define LL_RCC_MCO2SOURCE_NOCLOCK (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | 0x00000000U) /*!< MCO output disabled, no clock on MCO2 */
370 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_0) /*!< SYSCLK selection as MCO2 source */
371 #define LL_RCC_MCO2SOURCE_MSI (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_1) /*!< MSI selection as MCO2 source */
372 #define LL_RCC_MCO2SOURCE_HSI16 (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_1 |\
373 RCC_CFGR_MCO2SEL_0) /*!< HSI16 selection as MCO2 source */
374 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2) /*!< HSE selection as MCO2 source */
375 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2 |\
376 RCC_CFGR_MCO2SEL_0) /*!< Main PLL selection as MCO2 source */
377 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2 |\
378 RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */
379 #define LL_RCC_MCO2SOURCE_LSE (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2 |\
380 RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
381 #if defined(RCC_CRRCR_HSI48ON)
382 #define LL_RCC_MCO2SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_3) /*!< HSI48 selection as MCO2 source */
383 #endif /* RCC_CRRCR_HSI48ON */
384 #define LL_RCC_MCO2SOURCE_RTC (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_3 |\
385 RCC_CFGR_MCO2SEL_0) /*!< RTC alter clk selection as MCO2 source */
386 #define LL_RCC_MCO2SOURCE_RTCWUPI (uint32_t)((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_3 |\
387 RCC_CFGR_MCO2SEL_1) /*!< RTC wakeup interrupt signal selection as MCO2 source */
388 /**
389 * @}
390 */
391
392 /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler
393 * @{
394 */
395
396 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | 0x00000000U) /*!< MCO not divided */
397
398 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 2 */
399 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 4 */
400 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 |\
401 RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 8 */
402 #define LL_RCC_MCO2_DIV_16 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) /*!< MCO divided by 16 */
403 #define LL_RCC_MCO2_DIV_32 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 |\
404 RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 32 */
405 #define LL_RCC_MCO2_DIV_64 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 |\
406 RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 64 */
407 #define LL_RCC_MCO2_DIV_128 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 |\
408 RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 128 */
409 #define LL_RCC_MCO2_DIV_256 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) /*!< MCO divided by 256 */
410 #define LL_RCC_MCO2_DIV_512 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3 |\
411 RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 512 */
412 #define LL_RCC_MCO2_DIV_1024 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3 |\
413 RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 1024 */
414 /**
415 * @}
416 */
417
418 #if defined(USE_FULL_LL_DRIVER)
419 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
420 * @{
421 */
422 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
423 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
424 /**
425 * @}
426 */
427 #endif /* USE_FULL_LL_DRIVER */
428
429 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
430 * @{
431 */
432 #define LL_RCC_USART1_CLKSOURCE_PCLK1 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK clock used as USART1 clock source */
433 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
434 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
435 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
436
437 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK clock used as USART2 clock source */
438 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
439 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
440 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
441 /**
442 * @}
443 */
444
445 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
446 * @{
447 */
448 #if defined (LPUART3)
449 #define LL_RCC_LPUART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART3SEL << 16U) | 0x00000000U) /*!< PCLK clock used as LPUART3 clock source */
450 #define LL_RCC_LPUART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART3SEL << 16U) | RCC_CCIPR_LPUART3SEL_0) /*!< SYSCLK clock used as LPUART3 clock source */
451 #define LL_RCC_LPUART3_CLKSOURCE_HSI ((RCC_CCIPR_LPUART3SEL << 16U) | RCC_CCIPR_LPUART3SEL_1) /*!< HSI clock used as LPUART3 clock source */
452 #define LL_RCC_LPUART3_CLKSOURCE_LSE ((RCC_CCIPR_LPUART3SEL << 16U) | RCC_CCIPR_LPUART3SEL) /*!< LSE clock used as LPUART3 clock source */
453 #endif /* LPUART3 */
454 #define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U) /*!< PCLK clock used as LPUART2 clock source */
455 #define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0) /*!< SYSCLK clock used as LPUART2 clock source */
456 #define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1) /*!< HSI clock used as LPUART2 clock source */
457 #define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL) /*!< LSE clock used as LPUART2 clock source */
458 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U) /*!< PCLK clock used as LPUART1 clock source */
459 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0) /*!< SYSCLK clock used as LPUART1 clock source */
460 #define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */
461 #define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL) /*!< LSE clock used as LPUART1 clock source */
462 /**
463 * @}
464 */
465
466 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
467 * @{
468 */
469 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
470 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | \
471 (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
472 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | \
473 (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
474 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
475 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | \
476 (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
477 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | \
478 (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
479 /**
480 * @}
481 */
482
483 /** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection
484 * @{
485 */
486 #define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*!< PCLK clock used as TIM1 clock source */
487 #define LL_RCC_TIM1_CLKSOURCE_PLLQ (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*!< PLL used as TIM1 clock source */
488 /**
489 * @}
490 */
491 /** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE
492 * @{
493 */
494 #define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U)) /*!< PCLK clock used as TIM15 clock source */
495 #define LL_RCC_TIM15_CLKSOURCE_PLLQ (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U)) /*!< PLL used as TIM15 clock source */
496 /**
497 * @}
498 */
499 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
500 * @{
501 */
502 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) /*!< PCLK selected as LPTIM1 clock */
503 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */
504 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */
505 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE selected as LPTIM1 clock */
506 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) /*!< PCLK selected as LPTIM2 clock */
507 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */
508 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */
509 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE selected as LPTIM2 clock */
510 #if defined (LPTIM3)
511 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM3SEL | (0x00000000U >> 16U)) /*!< PCLK selected as LPTIM3 clock */
512 #define LL_RCC_LPTIM3_CLKSOURCE_LSI (RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL_0 >> 16U)) /*!< LSI selected as LPTIM3 clock */
513 #define LL_RCC_LPTIM3_CLKSOURCE_HSI (RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL_1 >> 16U)) /*!< HSI selected as LPTIM3 clock */
514 #define LL_RCC_LPTIM3_CLKSOURCE_LSE (RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL >> 16U)) /*!< LSE selected as LPTIM3 clock */
515 #endif /* LPTIM3 */
516 /**
517 * @}
518 */
519 #if defined(USB_DRD_FS)
520 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
521 * @{
522 */
523 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */
524 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL_0 /*!< MSI clock used as USB clock source */
525 #define LL_RCC_USB_CLKSOURCE_PLLQ RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
526 #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR_CLK48SEL /*!< HSI48 clock used as USB clock source */
527 #endif /* USB_DRD_FS */
528 /**
529 * @}
530 */
531
532 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
533 * @{
534 */
535 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */
536 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL_0 /*!< MSI clock used as RNG clock source */
537 #define LL_RCC_RNG_CLKSOURCE_PLLQ RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
538 #if defined(RCC_CRRCR_HSI48ON)
539 #define LL_RCC_RNG_CLKSOURCE_HSI48 RCC_CCIPR_CLK48SEL /*!< HSI48 clock used as RNG clock source */
540 #endif /* RCC_CRRCR_HSI48ON */
541 /**
542 * @}
543 */
544
545 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
546 * @{
547 */
548 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as ADC clock source */
549 #define LL_RCC_ADC_CLKSOURCE_PLLP RCC_CCIPR_ADCSEL_0 /*!< PLL P clock used as ADC clock source */
550 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI clock used as ADC clock source */
551 #define LL_RCC_ADC_CLKSOURCE_NONE RCC_CCIPR_ADCSEL /*!< No clock used as ADC clock source */
552
553 /**
554 * @}
555 */
556
557 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
558 * @{
559 */
560 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
561 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
562 #define LL_RCC_USART3_CLKSOURCE 0x00000000U /*!< To be used for USART3 Clock frequency retrieval */
563 #define LL_RCC_USART4_CLKSOURCE 0x00000001U /*!< To be used for USART4 Clock frequency retrieval */
564 /**
565 * @}
566 */
567
568 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
569 * @{
570 */
571 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
572 #define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */
573 #if defined (LPUART3)
574 #define LL_RCC_LPUART3_CLKSOURCE RCC_CCIPR_LPUART3SEL /*!< LPUART3 Clock source selection */
575 #endif /* LPUART3 */
576 /**
577 * @}
578 */
579
580 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
581 * @{
582 */
583 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | \
584 (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
585 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | \
586 (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
587 /**
588 * @}
589 */
590
591 /** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source
592 * @{
593 */
594 #define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */
595 #define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL /*!< TIM15 Clock source selection */
596 /**
597 * @}
598 */
599
600 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
601 * @{
602 */
603 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */
604 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
605 #if defined (LPTIM3)
606 #define LL_RCC_LPTIM3_CLKSOURCE RCC_CCIPR_LPTIM3SEL /*!< LPTIM2 Clock source selection */
607 #endif /* LPTIM3 */
608 /**
609 * @}
610 */
611
612 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
613 * @{
614 */
615 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
616 /**
617 * @}
618 */
619 #if defined (USB_DRD_FS)
620 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
621 * @{
622 */
623 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
624 #endif /* USB_DRD_FS */
625 /**
626 * @}
627 */
628
629 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
630 * @{
631 */
632 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
633 /**
634 * @}
635 */
636
637 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
638 * @{
639 */
640 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
641 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
642 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
643 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
644 /**
645 * @}
646 */
647
648 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
649 * @{
650 */
651 #define LL_RCC_PLLSOURCE_NONE 0UL /*!< No clock selected as main PLL entry clock source */
652 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as main PLL entry clock source */
653 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI16 clock selected as main PLL entry clock source */
654 #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as main PLL entry clock source */
655
656 /**
657 * @}
658 */
659
660 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
661 * @{
662 */
663 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */
664 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
665 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
666 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
667 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */
668 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */
669 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */
670 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< Main PLL division factor for PLLM input by 8 */
671 /**
672 * @}
673 */
674
675 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
676 * @{
677 */
678 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
679 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
680 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
681 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
682 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
683 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
684 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
685 /**
686 * @}
687 */
688
689 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
690 * @{
691 */
692 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
693 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
694 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 4 */
695 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
696 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 6 */
697 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 7 */
698 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
699 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
700 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 10 */
701 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 11 */
702 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 12 */
703 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 13 */
704 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 14 */
705 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 15 */
706 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 16 */
707 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
708 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 18 */
709 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 19 */
710 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 20 */
711 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 21 */
712 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 22 */
713 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 23 */
714 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 24 */
715 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 25 */
716 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 26 */
717 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 27 */
718 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 28 */
719 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 29 */
720 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 30 */
721 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 31 */
722 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_4|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_1| \
723 RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 32 */
724 /**
725 * @}
726 */
727
728 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
729 * @{
730 */
731 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
732 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
733 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
734 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
735 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
736 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
737 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 8 */
738 /**
739 * @}
740 */
741
742 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
743 * @{
744 */
745 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
746 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
747 /**
748 * @}
749 */
750
751 /**
752 * @}
753 */
754
755 /* Exported macro ------------------------------------------------------------*/
756 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
757 * @{
758 */
759
760 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
761 * @{
762 */
763
764 /**
765 * @brief Write a value in RCC register
766 * @param __REG__ Register to be written
767 * @param __VALUE__ Value to be written in the register
768 * @retval None
769 */
770 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
771
772 /**
773 * @brief Read a value in RCC register
774 * @param __REG__ Register to be read
775 * @retval Register value
776 */
777 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
778 /**
779 * @}
780 */
781
782 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
783 * @{
784 */
785
786 /**
787 * @brief Helper macro to calculate the PLLCLK frequency on system domain
788 * @note ex: @ref __LL_RCC_CALC_PLLCLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetM (),
789 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
790 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
791 * @param __PLLM__ This parameter can be one of the following values:
792 * @arg @ref LL_RCC_PLLM_DIV_1
793 * @arg @ref LL_RCC_PLLM_DIV_2
794 * @arg @ref LL_RCC_PLLM_DIV_3
795 * @arg @ref LL_RCC_PLLM_DIV_4
796 * @arg @ref LL_RCC_PLLM_DIV_5
797 * @arg @ref LL_RCC_PLLM_DIV_6
798 * @arg @ref LL_RCC_PLLM_DIV_7
799 * @arg @ref LL_RCC_PLLM_DIV_8
800 *
801 * @param __PLLN__ Between 4 and 127
802 * @param __PLLR__ This parameter can be one of the following values:
803 * @arg @ref LL_RCC_PLLR_DIV_2
804 * @arg @ref LL_RCC_PLLR_DIV_3
805 * @arg @ref LL_RCC_PLLR_DIV_4
806 * @arg @ref LL_RCC_PLLR_DIV_5
807 * @arg @ref LL_RCC_PLLR_DIV_6
808 * @arg @ref LL_RCC_PLLR_DIV_7
809 * @arg @ref LL_RCC_PLLR_DIV_8
810 * @retval PLL clock frequency (in Hz)
811 */
812 #define __LL_RCC_CALC_PLLCLK_R_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
813 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
814 (((__PLLR__)>> RCC_PLLCFGR_PLLR_Pos) + 1U))
815
816 /**
817 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
818 * @note ex: @ref __LL_RCC_CALC_PLLCLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetM (),
819 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
820 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
821 * @param __PLLM__ This parameter can be one of the following values:
822 * @arg @ref LL_RCC_PLLM_DIV_1
823 * @arg @ref LL_RCC_PLLM_DIV_2
824 * @arg @ref LL_RCC_PLLM_DIV_3
825 * @arg @ref LL_RCC_PLLM_DIV_4
826 * @arg @ref LL_RCC_PLLM_DIV_5
827 * @arg @ref LL_RCC_PLLM_DIV_6
828 * @arg @ref LL_RCC_PLLM_DIV_7
829 * @arg @ref LL_RCC_PLLM_DIV_8
830 *
831 * @param __PLLN__ Between 4 and 127
832 * @param __PLLQ__ This parameter can be one of the following values:
833 * @arg @ref LL_RCC_PLLQ_DIV_2
834 * @arg @ref LL_RCC_PLLR_DIV_3
835 * @arg @ref LL_RCC_PLLQ_DIV_4
836 * @arg @ref LL_RCC_PLLR_DIV_5
837 * @arg @ref LL_RCC_PLLQ_DIV_6
838 * @arg @ref LL_RCC_PLLR_DIV_7
839 * @arg @ref LL_RCC_PLLQ_DIV_8
840 * @retval PLL clock frequency (in Hz)
841 */
842 #define __LL_RCC_CALC_PLLCLK_Q_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((((__INPUTFREQ__) \
843 /(((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) +1UL))) * (__PLLN__)) / (((__PLLQ__)>> RCC_PLLCFGR_PLLQ_Pos) + 1UL)
844
845 /**
846 * @brief Helper macro to calculate the HCLK frequency
847 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
848 * @param __AHBPRESCALER__ This parameter can be one of the following values:
849 * @arg @ref LL_RCC_SYSCLK_DIV_1
850 * @arg @ref LL_RCC_SYSCLK_DIV_2
851 * @arg @ref LL_RCC_SYSCLK_DIV_4
852 * @arg @ref LL_RCC_SYSCLK_DIV_8
853 * @arg @ref LL_RCC_SYSCLK_DIV_16
854 * @arg @ref LL_RCC_SYSCLK_DIV_64
855 * @arg @ref LL_RCC_SYSCLK_DIV_128
856 * @arg @ref LL_RCC_SYSCLK_DIV_256
857 * @arg @ref LL_RCC_SYSCLK_DIV_512
858 * @retval HCLK clock frequency (in Hz)
859 */
860 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
861 ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & \
862 RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
863
864 /**
865 * @brief Helper macro to calculate the PCLK frequency (APB)
866 * @param __HCLKFREQ__ HCLK frequency
867 * @param __APBPRESCALER__ This parameter can be one of the following values:
868 * @arg @ref LL_RCC_APB1_DIV_1
869 * @arg @ref LL_RCC_APB1_DIV_2
870 * @arg @ref LL_RCC_APB1_DIV_4
871 * @arg @ref LL_RCC_APB1_DIV_8
872 * @arg @ref LL_RCC_APB1_DIV_16
873 * @retval PCLK1 clock frequency (in Hz)
874 */
875 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APBPRESCALER__) \
876 ((__HCLKFREQ__) >> APBPrescTable[(__APBPRESCALER__) >> RCC_CFGR_PPRE_Pos])
877
878 /**
879 * @brief Helper macro to calculate the MSI frequency (in Hz)
880 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
881 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
882 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
883 * else by LL_RCC_MSI_GetRange()
884 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
885 * (LL_RCC_MSI_IsEnabledRangeSelect()?
886 * LL_RCC_MSI_GetRange():
887 * LL_RCC_MSI_GetRangeAfterStandby()))
888 * @param __MSISEL__ This parameter can be one of the following values:
889 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
890 * @arg @ref LL_RCC_MSIRANGESEL_RUN
891 * @param __MSIRANGE__ This parameter can be one of the following values:
892 * @arg @ref LL_RCC_MSIRANGE_0
893 * @arg @ref LL_RCC_MSIRANGE_1
894 * @arg @ref LL_RCC_MSIRANGE_2
895 * @arg @ref LL_RCC_MSIRANGE_3
896 * @arg @ref LL_RCC_MSIRANGE_4
897 * @arg @ref LL_RCC_MSIRANGE_5
898 * @arg @ref LL_RCC_MSIRANGE_6
899 * @arg @ref LL_RCC_MSIRANGE_7
900 * @arg @ref LL_RCC_MSIRANGE_8
901 * @arg @ref LL_RCC_MSIRANGE_9
902 * @arg @ref LL_RCC_MSIRANGE_10
903 * @arg @ref LL_RCC_MSIRANGE_11
904 * @arg @ref LL_RCC_MSISRANGE_4
905 * @arg @ref LL_RCC_MSISRANGE_5
906 * @arg @ref LL_RCC_MSISRANGE_6
907 * @arg @ref LL_RCC_MSISRANGE_7
908 * @retval MSI clock frequency (in Hz)
909 */
910 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
911 (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
912 (MSIRangeTable[(__MSIRANGE__) >> 4U]))
913
914 /**
915 * @brief Helper macro to calculate the PLLPCLK frequency used on P domain
916 * @note ex: @ref __LL_RCC_CALC_PLLCLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetM (),
917 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
918 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
919 * @param __PLLM__ This parameter can be one of the following values:
920 * @arg @ref LL_RCC_PLLM_DIV_1
921 * @arg @ref LL_RCC_PLLM_DIV_2
922 * @arg @ref LL_RCC_PLLM_DIV_3
923 * @arg @ref LL_RCC_PLLM_DIV_4
924 * @arg @ref LL_RCC_PLLM_DIV_5
925 * @arg @ref LL_RCC_PLLM_DIV_6
926 * @arg @ref LL_RCC_PLLM_DIV_7
927 * @arg @ref LL_RCC_PLLM_DIV_8
928 * @param __PLLN__ Between Min_Data = 4 and Max_Data = 127
929 * @param __PLLP__ This parameter can be one of the following values:
930 * @arg @ref LL_RCC_PLLP_DIV_2
931 * @arg @ref LL_RCC_PLLP_DIV_3
932 * @arg @ref LL_RCC_PLLP_DIV_4
933 * @arg @ref LL_RCC_PLLP_DIV_5
934 * @arg @ref LL_RCC_PLLP_DIV_6
935 * @arg @ref LL_RCC_PLLP_DIV_7
936 * @arg @ref LL_RCC_PLLP_DIV_8
937 * @arg @ref LL_RCC_PLLP_DIV_9
938 * @arg @ref LL_RCC_PLLP_DIV_10
939 * @arg @ref LL_RCC_PLLP_DIV_11
940 * @arg @ref LL_RCC_PLLP_DIV_12
941 * @arg @ref LL_RCC_PLLP_DIV_13
942 * @arg @ref LL_RCC_PLLP_DIV_14
943 * @arg @ref LL_RCC_PLLP_DIV_15
944 * @arg @ref LL_RCC_PLLP_DIV_16
945 * @arg @ref LL_RCC_PLLP_DIV_17
946 * @arg @ref LL_RCC_PLLP_DIV_18
947 * @arg @ref LL_RCC_PLLP_DIV_19
948 * @arg @ref LL_RCC_PLLP_DIV_20
949 * @arg @ref LL_RCC_PLLP_DIV_21
950 * @arg @ref LL_RCC_PLLP_DIV_22
951 * @arg @ref LL_RCC_PLLP_DIV_23
952 * @arg @ref LL_RCC_PLLP_DIV_24
953 * @arg @ref LL_RCC_PLLP_DIV_25
954 * @arg @ref LL_RCC_PLLP_DIV_26
955 * @arg @ref LL_RCC_PLLP_DIV_27
956 * @arg @ref LL_RCC_PLLP_DIV_28
957 * @arg @ref LL_RCC_PLLP_DIV_29
958 * @arg @ref LL_RCC_PLLP_DIV_30
959 * @arg @ref LL_RCC_PLLP_DIV_31
960 * @arg @ref LL_RCC_PLLP_DIV_32
961 * @retval PLL clock frequency (in Hz)
962 */
963 #define __LL_RCC_CALC_PLLCLK_P_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
964 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
965 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
966 /**
967 * @}
968 */
969
970 /**
971 * @}
972 */
973
974 /* Exported functions --------------------------------------------------------*/
975 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
976 * @{
977 */
978
979 /** @defgroup RCC_LL_EF_HSE HSE
980 * @{
981 */
982
983 /**
984 * @brief Enable the Clock Security System.
985 * @rmtoll CR CSSON LL_RCC_EnableCSS
986 * @retval None
987 */
LL_RCC_EnableCSS(void)988 __STATIC_INLINE void LL_RCC_EnableCSS(void)
989 {
990 SET_BIT(RCC->CR, RCC_CR_CSSON);
991 }
992
993 /**
994 * @brief Disable the Clock Security System.
995 * @rmtoll CR CSSON LL_RCC_DisableCSS
996 * @retval None
997 */
LL_RCC_DisableCSS(void)998 __STATIC_INLINE void LL_RCC_DisableCSS(void)
999 {
1000 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
1001 }
1002
1003 /**
1004 * @brief Enable HSE external oscillator (HSE Bypass)
1005 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1006 * @retval None
1007 */
LL_RCC_HSE_EnableBypass(void)1008 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1009 {
1010 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1011 }
1012
1013 /**
1014 * @brief Disable HSE external oscillator (HSE Bypass)
1015 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1016 * @retval None
1017 */
LL_RCC_HSE_DisableBypass(void)1018 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1019 {
1020 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1021 }
1022
1023 /**
1024 * @brief Enable HSE crystal oscillator (HSE ON)
1025 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1026 * @retval None
1027 */
LL_RCC_HSE_Enable(void)1028 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1029 {
1030 SET_BIT(RCC->CR, RCC_CR_HSEON);
1031 }
1032
1033 /**
1034 * @brief Disable HSE crystal oscillator (HSE ON)
1035 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1036 * @retval None
1037 */
LL_RCC_HSE_Disable(void)1038 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1039 {
1040 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1041 }
1042
1043 /**
1044 * @brief Check if HSE oscillator Ready
1045 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1046 * @retval State of bit (1 or 0).
1047 */
LL_RCC_HSE_IsReady(void)1048 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1049 {
1050 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
1051 }
1052
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup RCC_LL_EF_HSI HSI
1058 * @{
1059 */
1060
1061 /**
1062 * @brief Enable HSI even in stop mode
1063 * @note HSI oscillator is forced ON even in Stop mode
1064 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1065 * @retval None
1066 */
LL_RCC_HSI_EnableInStopMode(void)1067 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1068 {
1069 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1070 }
1071
1072 /**
1073 * @brief Disable HSI in stop mode
1074 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1075 * @retval None
1076 */
LL_RCC_HSI_DisableInStopMode(void)1077 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1078 {
1079 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1080 }
1081
1082 /**
1083 * @brief IsEnabled HSI in stop mode
1084 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1085 * @retval State of bit (1 or 0).
1086 */
LL_RCC_HSI_IsEnabledInStopMode(void)1087 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1088 {
1089 return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON));
1090 }
1091
1092 /**
1093 * @brief Enable HSI oscillator
1094 * @rmtoll CR HSION LL_RCC_HSI_Enable
1095 * @retval None
1096 */
LL_RCC_HSI_Enable(void)1097 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1098 {
1099 SET_BIT(RCC->CR, RCC_CR_HSION);
1100 }
1101
1102 /**
1103 * @brief Disable HSI oscillator
1104 * @rmtoll CR HSION LL_RCC_HSI_Disable
1105 * @retval None
1106 */
LL_RCC_HSI_Disable(void)1107 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1108 {
1109 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1110 }
1111
1112 /**
1113 * @brief Check if HSI clock is ready
1114 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1115 * @retval State of bit (1 or 0).
1116 */
LL_RCC_HSI_IsReady(void)1117 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1118 {
1119 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
1120 }
1121
1122 /**
1123 * @brief Enable HSI oscillator in auto start from stop mode
1124 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
1125 * @retval None
1126 */
LL_RCC_HSI_EnableAutoFromStop(void)1127 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
1128 {
1129 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
1130 }
1131
1132 /**
1133 * @brief Disable HSI oscillator in auto start from stop mode
1134 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
1135 * @retval None
1136 */
LL_RCC_HSI_DisableAutoFromStop(void)1137 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
1138 {
1139 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
1140 }
1141
1142 /**
1143 * @brief Check if HSI is enabled in auto start from stop mode
1144 * @rmtoll CR HSIASFS LL_RCC_HSI_IsEnabledInAutoFromStop
1145 * @retval State of bit (1 or 0).
1146 */
LL_RCC_HSI_IsEnabledInAutoFromStop(void)1147 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInAutoFromStop(void)
1148 {
1149 return ((READ_BIT(RCC->CR, RCC_CR_HSIASFS) == RCC_CR_HSIASFS) ? 1U : 0U);
1150 }
1151
1152 /**
1153 * @brief Get HSI Calibration value
1154 * @note When HSITRIM is written, HSICAL is updated with the sum of
1155 * HSITRIM and the factory trim value
1156 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1157 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1158 */
LL_RCC_HSI_GetCalibration(void)1159 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1160 {
1161 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1162 }
1163
1164 /**
1165 * @brief Set HSI Calibration trimming
1166 * @note user-programmable trimming value that is added to the HSICAL
1167 * @note Default value is 16, which, when added to the HSICAL value,
1168 * should trim the HSI to 16 MHz +/- 1 %
1169 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1170 * @param Value Between Min_Data = 0 and Max_Data = 31
1171 * @retval None
1172 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1173 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1174 {
1175 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1176 }
1177
1178 /**
1179 * @brief Get HSI Calibration trimming
1180 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1181 * @retval Between Min_Data = 0 and Max_Data = 31
1182 */
LL_RCC_HSI_GetCalibTrimming(void)1183 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1184 {
1185 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1186 }
1187
1188 /**
1189 * @}
1190 */
1191
1192 /** @defgroup RCC_LL_EF_LSE LSE
1193 * @{
1194 */
1195
1196 /**
1197 * @brief Enable Low Speed External (LSE) crystal.
1198 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1199 * @retval None
1200 */
LL_RCC_LSE_Enable(void)1201 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1202 {
1203 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1204 }
1205
1206 /**
1207 * @brief Disable Low Speed External (LSE) crystal.
1208 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1209 * @retval None
1210 */
LL_RCC_LSE_Disable(void)1211 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1212 {
1213 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1214 }
1215
1216 /**
1217 * @brief Enable LSE oscillator propagation for system clock
1218 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation
1219 * @retval None
1220 */
LL_RCC_LSE_EnablePropagation(void)1221 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
1222 {
1223 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1224 }
1225
1226 /**
1227 * @brief Disable LSE oscillator propagation for system clock
1228 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation
1229 * @retval None
1230 */
LL_RCC_LSE_DisablePropagation(void)1231 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
1232 {
1233 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1234 }
1235
1236 /**
1237 * @brief Enable external clock source (LSE bypass).
1238 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1239 * @retval None
1240 */
LL_RCC_LSE_EnableBypass(void)1241 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1242 {
1243 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1244 }
1245
1246 /**
1247 * @brief Disable external clock source (LSE bypass).
1248 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1249 * @retval None
1250 */
LL_RCC_LSE_DisableBypass(void)1251 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1252 {
1253 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1254 }
1255
1256 /**
1257 * @brief Set LSE oscillator drive capability
1258 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1259 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1260 * @param LSEDrive This parameter can be one of the following values:
1261 * @arg @ref LL_RCC_LSEDRIVE_LOW
1262 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1263 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1264 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1265 * @retval None
1266 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1267 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1268 {
1269 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1270 }
1271
1272 /**
1273 * @brief Get LSE oscillator drive capability
1274 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1275 * @retval Returned value can be one of the following values:
1276 * @arg @ref LL_RCC_LSEDRIVE_LOW
1277 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1278 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1279 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1280 */
LL_RCC_LSE_GetDriveCapability(void)1281 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1282 {
1283 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1284 }
1285
1286 /**
1287 * @brief Enable Clock security system on LSE.
1288 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1289 * @retval None
1290 */
LL_RCC_LSE_EnableCSS(void)1291 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1292 {
1293 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1294 }
1295
1296 /**
1297 * @brief Disable Clock security system on LSE.
1298 * @note Clock security system can be disabled only after a LSE
1299 * failure detection. In that case it MUST be disabled by software.
1300 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1301 * @retval None
1302 */
LL_RCC_LSE_DisableCSS(void)1303 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1304 {
1305 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1306 }
1307
1308 /**
1309 * @brief Check if LSE oscillator Ready
1310 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1311 * @retval State of bit (1 or 0).
1312 */
LL_RCC_LSE_IsReady(void)1313 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1314 {
1315 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
1316 }
1317
1318 /**
1319 * @brief Check if LSE oscillator propagation for system clock Ready
1320 * @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady
1321 * @retval State of bit (1 or 0).
1322 */
LL_RCC_LSE_IsPropagationReady(void)1323 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
1324 {
1325 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY));
1326 }
1327
1328 /**
1329 * @brief Check if CSS on LSE failure Detection
1330 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1331 * @retval State of bit (1 or 0).
1332 */
LL_RCC_LSE_IsCSSDetected(void)1333 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1334 {
1335 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
1336 }
1337
1338 /**
1339 * @}
1340 */
1341
1342 /** @defgroup RCC_LL_EF_LSI LSI
1343 * @{
1344 */
1345
1346 /**
1347 * @brief Enable LSI Oscillator
1348 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1349 * @retval None
1350 */
LL_RCC_LSI_Enable(void)1351 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1352 {
1353 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1354 }
1355
1356 /**
1357 * @brief Disable LSI Oscillator
1358 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1359 * @retval None
1360 */
LL_RCC_LSI_Disable(void)1361 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1362 {
1363 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1364 }
1365
1366 /**
1367 * @brief Check if LSI is Ready
1368 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1369 * @retval State of bit (1 or 0).
1370 */
LL_RCC_LSI_IsReady(void)1371 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1372 {
1373 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
1374 }
1375 /**
1376 * @brief Set LSI prescaler
1377 * @rmtoll CSR LSIPRE LL_RCC_LSI_SetPrescaler
1378 * @param LSIPrescaler This parameter can be one of the following values:
1379 * @arg @ref LL_RCC_LSI_DIV_1
1380 * @arg @ref LL_RCC_LSI_DIV_128
1381 * @retval None
1382 */
LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)1383 __STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)
1384 {
1385 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSIPrescaler);
1386 }
1387
1388 /**
1389 * @brief Get LSI prescaler
1390 * @rmtoll CSR LSIPRE LL_RCC_LSI_GetPrescaler
1391 * @retval Returned value can be one of the following values:
1392 * @arg @ref LL_RCC_LSI_DIV_1
1393 * @arg @ref LL_RCC_LSI_DIV_128
1394 */
LL_RCC_LSI_GetPrescaler(void)1395 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void)
1396 {
1397 return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV));
1398 }
1399
1400 /**
1401 * @}
1402 */
1403 /**
1404 * @}
1405 */
1406
1407 /** @defgroup RCC_LL_EF_MSI MSI
1408 * @{
1409 */
1410
1411 /**
1412 * @brief Enable MSI oscillator
1413 * @rmtoll CR MSION LL_RCC_MSI_Enable
1414 * @retval None
1415 */
LL_RCC_MSI_Enable(void)1416 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1417 {
1418 SET_BIT(RCC->CR, RCC_CR_MSION);
1419 }
1420
1421 /**
1422 * @brief Disable MSI oscillator
1423 * @rmtoll CR MSION LL_RCC_MSI_Disable
1424 * @retval None
1425 */
LL_RCC_MSI_Disable(void)1426 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1427 {
1428 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1429 }
1430
1431 /**
1432 * @brief Check if MSI oscillator Ready
1433 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1434 * @retval State of bit (1 or 0).
1435 */
LL_RCC_MSI_IsReady(void)1436 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1437 {
1438 return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
1439 }
1440
1441 /**
1442 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
1443 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
1444 * and ready (LSERDY set by hardware)
1445 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
1446 * ready
1447 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
1448 * @retval None
1449 */
LL_RCC_MSI_EnablePLLMode(void)1450 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
1451 {
1452 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1453 }
1454
1455 /**
1456 * @brief Disable MSI-PLL mode
1457 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
1458 * the Clock Security System on LSE detects a LSE failure
1459 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
1460 * @retval None
1461 */
LL_RCC_MSI_DisablePLLMode(void)1462 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
1463 {
1464 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1465 }
1466
1467 /**
1468 * @brief Enable MSI clock range selection with MSIRANGE register
1469 * @note Write 0 has no effect. After a standby or a reset
1470 * MSIRGSEL is at 0 and the MSI range value is provided by
1471 * MSISRANGE
1472 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
1473 * @retval None
1474 */
LL_RCC_MSI_EnableRangeSelection(void)1475 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
1476 {
1477 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
1478 }
1479
1480 /**
1481 * @brief Check if MSI clock range is selected with MSIRANGE register
1482 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
1483 * @retval State of bit (1 or 0).
1484 */
LL_RCC_MSI_IsEnabledRangeSelect(void)1485 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
1486 {
1487 return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
1488 }
1489
1490 /**
1491 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1492 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
1493 * @param Range This parameter can be one of the following values:
1494 * @arg @ref LL_RCC_MSIRANGE_0
1495 * @arg @ref LL_RCC_MSIRANGE_1
1496 * @arg @ref LL_RCC_MSIRANGE_2
1497 * @arg @ref LL_RCC_MSIRANGE_3
1498 * @arg @ref LL_RCC_MSIRANGE_4
1499 * @arg @ref LL_RCC_MSIRANGE_5
1500 * @arg @ref LL_RCC_MSIRANGE_6
1501 * @arg @ref LL_RCC_MSIRANGE_7
1502 * @arg @ref LL_RCC_MSIRANGE_8
1503 * @arg @ref LL_RCC_MSIRANGE_9
1504 * @arg @ref LL_RCC_MSIRANGE_10
1505 * @arg @ref LL_RCC_MSIRANGE_11
1506 * @retval None
1507 */
LL_RCC_MSI_SetRange(uint32_t Range)1508 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1509 {
1510 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
1511 }
1512
1513 /**
1514 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1515 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
1516 * @retval Returned value can be one of the following values:
1517 * @arg @ref LL_RCC_MSIRANGE_0
1518 * @arg @ref LL_RCC_MSIRANGE_1
1519 * @arg @ref LL_RCC_MSIRANGE_2
1520 * @arg @ref LL_RCC_MSIRANGE_3
1521 * @arg @ref LL_RCC_MSIRANGE_4
1522 * @arg @ref LL_RCC_MSIRANGE_5
1523 * @arg @ref LL_RCC_MSIRANGE_6
1524 * @arg @ref LL_RCC_MSIRANGE_7
1525 * @arg @ref LL_RCC_MSIRANGE_8
1526 * @arg @ref LL_RCC_MSIRANGE_9
1527 * @arg @ref LL_RCC_MSIRANGE_10
1528 * @arg @ref LL_RCC_MSIRANGE_11
1529 */
LL_RCC_MSI_GetRange(void)1530 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
1531 {
1532 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
1533 }
1534
1535 /**
1536 * @brief Configure MSI range used after standby
1537 * @rmtoll CSR MSISTBYRG LL_RCC_MSI_SetRangeAfterStandby
1538 * @param Range This parameter can be one of the following values:
1539 * @arg @ref LL_RCC_MSISRANGE_4
1540 * @arg @ref LL_RCC_MSISRANGE_5
1541 * @arg @ref LL_RCC_MSISRANGE_6
1542 * @arg @ref LL_RCC_MSISRANGE_7
1543 * @retval None
1544 */
LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)1545 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
1546 {
1547 MODIFY_REG(RCC->CSR, RCC_CSR_MSISTBYRG, Range);
1548 }
1549
1550 /**
1551 * @brief Get MSI range used after standby
1552 * @rmtoll CSR MSISTBYRG LL_RCC_MSI_GetRangeAfterStandby
1553 * @retval Returned value can be one of the following values:
1554 * @arg @ref LL_RCC_MSISRANGE_4
1555 * @arg @ref LL_RCC_MSISRANGE_5
1556 * @arg @ref LL_RCC_MSISRANGE_6
1557 * @arg @ref LL_RCC_MSISRANGE_7
1558 */
LL_RCC_MSI_GetRangeAfterStandby(void)1559 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
1560 {
1561 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISTBYRG));
1562 }
1563
1564 /**
1565 * @brief Get MSI Calibration value
1566 * @note When MSITRIM is written, MSICAL is updated with the sum of
1567 * MSITRIM and the factory trim value
1568 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
1569 * @retval Between Min_Data = 0 and Max_Data = 255
1570 */
LL_RCC_MSI_GetCalibration(void)1571 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
1572 {
1573 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
1574 }
1575
1576 /**
1577 * @brief Set MSI Calibration trimming
1578 * @note user-programmable trimming value that is added to the MSICAL
1579 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
1580 * @param Value Between Min_Data = 0 and Max_Data = 255
1581 * @retval None
1582 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)1583 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
1584 {
1585 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
1586 }
1587
1588 /**
1589 * @brief Get MSI Calibration trimming
1590 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
1591 * @retval Between 0 and 255
1592 */
LL_RCC_MSI_GetCalibTrimming(void)1593 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
1594 {
1595 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
1596 }
1597
1598 /**
1599 * @}
1600 */
1601
1602 /** @defgroup RCC_LL_EF_LSCO LSCO
1603 * @{
1604 */
1605
1606 /**
1607 * @brief Enable Low speed clock
1608 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1609 * @retval None
1610 */
LL_RCC_LSCO_Enable(void)1611 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1612 {
1613 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1614 }
1615
1616 /**
1617 * @brief Disable Low speed clock
1618 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1619 * @retval None
1620 */
LL_RCC_LSCO_Disable(void)1621 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1622 {
1623 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1624 }
1625
1626 /**
1627 * @brief Configure Low speed clock selection
1628 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1629 * @param Source This parameter can be one of the following values:
1630 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1631 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1632 * @retval None
1633 */
LL_RCC_LSCO_SetSource(uint32_t Source)1634 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1635 {
1636 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1637 }
1638
1639 /**
1640 * @brief Get Low speed clock selection
1641 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1642 * @retval Returned value can be one of the following values:
1643 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1644 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1645 */
LL_RCC_LSCO_GetSource(void)1646 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1647 {
1648 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1649 }
1650
1651 /**
1652 * @}
1653 */
1654
1655 /** @defgroup RCC_LL_EF_System System
1656 * @{
1657 */
1658
1659 /**
1660 * @brief Configure the system clock source
1661 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1662 * @param Source This parameter can be one of the following values:
1663 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
1664 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1665 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1666 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1667 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
1668 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
1669 * @retval None
1670 */
LL_RCC_SetSysClkSource(uint32_t Source)1671 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1672 {
1673 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1674 }
1675
1676 /**
1677 * @brief Get the system clock source
1678 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1679 * @retval Returned value can be one of the following values:
1680 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
1681 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1682 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1683 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1684 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
1685 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
1686 */
LL_RCC_GetSysClkSource(void)1687 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1688 {
1689 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1690 }
1691
1692 /**
1693 * @brief Set AHB prescaler
1694 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1695 * @param Prescaler This parameter can be one of the following values:
1696 * @arg @ref LL_RCC_SYSCLK_DIV_1
1697 * @arg @ref LL_RCC_SYSCLK_DIV_2
1698 * @arg @ref LL_RCC_SYSCLK_DIV_4
1699 * @arg @ref LL_RCC_SYSCLK_DIV_8
1700 * @arg @ref LL_RCC_SYSCLK_DIV_16
1701 * @arg @ref LL_RCC_SYSCLK_DIV_64
1702 * @arg @ref LL_RCC_SYSCLK_DIV_128
1703 * @arg @ref LL_RCC_SYSCLK_DIV_256
1704 * @arg @ref LL_RCC_SYSCLK_DIV_512
1705 * @retval None
1706 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1707 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1708 {
1709 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1710 }
1711
1712 /**
1713 * @brief Set APB prescaler
1714 * @rmtoll CFGR PPRE LL_RCC_SetAPBPrescaler
1715 * @param Prescaler This parameter can be one of the following values:
1716 * @arg @ref LL_RCC_APB1_DIV_1
1717 * @arg @ref LL_RCC_APB1_DIV_2
1718 * @arg @ref LL_RCC_APB1_DIV_4
1719 * @arg @ref LL_RCC_APB1_DIV_8
1720 * @arg @ref LL_RCC_APB1_DIV_16
1721 * @retval None
1722 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1723 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1724 {
1725 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
1726 }
1727
1728 /**
1729 * @brief Get AHB prescaler
1730 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1731 * @retval Returned value can be one of the following values:
1732 * @arg @ref LL_RCC_SYSCLK_DIV_1
1733 * @arg @ref LL_RCC_SYSCLK_DIV_2
1734 * @arg @ref LL_RCC_SYSCLK_DIV_4
1735 * @arg @ref LL_RCC_SYSCLK_DIV_8
1736 * @arg @ref LL_RCC_SYSCLK_DIV_16
1737 * @arg @ref LL_RCC_SYSCLK_DIV_64
1738 * @arg @ref LL_RCC_SYSCLK_DIV_128
1739 * @arg @ref LL_RCC_SYSCLK_DIV_256
1740 * @arg @ref LL_RCC_SYSCLK_DIV_512
1741 */
LL_RCC_GetAHBPrescaler(void)1742 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1743 {
1744 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1745 }
1746
1747 /**
1748 * @brief Get APB prescaler
1749 * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
1750 * @retval Returned value can be one of the following values:
1751 * @arg @ref LL_RCC_APB1_DIV_1
1752 * @arg @ref LL_RCC_APB1_DIV_2
1753 * @arg @ref LL_RCC_APB1_DIV_4
1754 * @arg @ref LL_RCC_APB1_DIV_8
1755 * @arg @ref LL_RCC_APB1_DIV_16
1756 */
LL_RCC_GetAPB1Prescaler(void)1757 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1758 {
1759 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
1760 }
1761
1762 /**
1763 * @brief Set Clock After Wake-Up From Stop mode
1764 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
1765 * @param Clock This parameter can be one of the following values:
1766 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
1767 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
1768 * @retval None
1769 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)1770 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
1771 {
1772 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
1773 }
1774
1775 /**
1776 * @brief Get Clock After Wake-Up From Stop mode
1777 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
1778 * @retval Returned value can be one of the following values:
1779 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
1780 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
1781 */
LL_RCC_GetClkAfterWakeFromStop(void)1782 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
1783 {
1784 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
1785 }
1786
1787 /**
1788 * @}
1789 */
1790
1791 /** @defgroup RCC_LL_EF_MCO MCO
1792 * @{
1793 */
1794
1795 /**
1796 * @brief Configure MCOx
1797 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
1798 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
1799 * CFGR MCO2 LL_RCC_ConfigMCO\n
1800 * CFGR MCO2PRE LL_RCC_ConfigMCO
1801 * @param MCOxSource This parameter can be one of the following values:
1802 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1803 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1804 * @arg @ref LL_RCC_MCO1SOURCE_MSI
1805 * @arg @ref LL_RCC_MCO1SOURCE_HSI16
1806 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1807 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1808 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1809 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1810 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
1811 * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
1812 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
1813 * @arg @ref LL_RCC_MCO2SOURCE_MSI
1814 * @arg @ref LL_RCC_MCO2SOURCE_HSI16
1815 * @arg @ref LL_RCC_MCO2SOURCE_HSE
1816 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
1817 * @arg @ref LL_RCC_MCO2SOURCE_LSI
1818 * @arg @ref LL_RCC_MCO2SOURCE_LSE
1819 * @arg @ref LL_RCC_MCO2SOURCE_HSI48
1820 * @param MCOxPrescaler This parameter can be one of the following values:
1821 * @arg @ref LL_RCC_MCO1_DIV_1
1822 * @arg @ref LL_RCC_MCO1_DIV_2
1823 * @arg @ref LL_RCC_MCO1_DIV_4
1824 * @arg @ref LL_RCC_MCO1_DIV_8
1825 * @arg @ref LL_RCC_MCO1_DIV_16
1826 * @arg @ref LL_RCC_MCO1_DIV_32
1827 * @arg @ref LL_RCC_MCO1_DIV_64
1828 * @arg @ref LL_RCC_MCO1_DIV_128
1829 * @arg @ref LL_RCC_MCO1_DIV_256
1830 * @arg @ref LL_RCC_MCO1_DIV_512
1831 * @arg @ref LL_RCC_MCO2_DIV_1
1832 * @arg @ref LL_RCC_MCO2_DIV_2
1833 * @arg @ref LL_RCC_MCO2_DIV_4
1834 * @arg @ref LL_RCC_MCO2_DIV_8
1835 * @arg @ref LL_RCC_MCO2_DIV_16
1836 * @arg @ref LL_RCC_MCO2_DIV_32
1837 * @arg @ref LL_RCC_MCO2_DIV_64
1838 * @arg @ref LL_RCC_MCO2_DIV_128
1839 * @arg @ref LL_RCC_MCO2_DIV_256
1840 * @arg @ref LL_RCC_MCO2_DIV_512
1841 * @arg @ref LL_RCC_MCO2_DIV_1024
1842 * @retval None
1843 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1844 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1845 {
1846 MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), \
1847 (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
1848 }
1849
1850 /**
1851 * @}
1852 */
1853
1854 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1855 * @{
1856 */
1857
1858 /**
1859 * @brief Configure USARTx clock source
1860 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1861 * @param USARTxSource This parameter can be one of the following values:
1862 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1863 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1864 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1865 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1866 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1867 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1868 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1869 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1870 * @retval None
1871 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1872 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1873 {
1874 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
1875 }
1876
1877 /**
1878 * @brief Configure LPUART1x clock source
1879 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1880 * @param LPUARTxSource This parameter can be one of the following values:
1881 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1882 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1883 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1884 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1885 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1
1886 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK
1887 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI
1888 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE
1889 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_PCLK1 (*)
1890 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_SYSCLK (*)
1891 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_HSI (*)
1892 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_LSE (*)
1893 *
1894 * (*) value not defined in all devices.
1895 * @retval None
1896 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1897 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1898 {
1899 MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16), (LPUARTxSource & 0x0000FFFFU));
1900 }
1901
1902 /**
1903 * @brief Configure I2Cx clock source
1904 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
1905 * @param I2CxSource This parameter can be one of the following values:
1906 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1907 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1908 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1909 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1910 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1911 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1912 * @retval None
1913 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1914 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1915 {
1916 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
1917 MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), \
1918 ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
1919 }
1920
1921 /**
1922 * @brief Configure TIMx clock source
1923 * @rmtoll CCIPR TIMxSEL LL_RCC_SetTIMClockSource
1924 * @param TIMxSource This parameter can be one of the following values:
1925 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLLQ
1926 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
1927 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLLQ
1928 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
1929 * @retval None
1930 */
LL_RCC_SetTIMClockSource(uint32_t TIMxSource)1931 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
1932 {
1933 MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16));
1934 }
1935
1936 /**
1937 * @brief Configure LPTIMx clock source
1938 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
1939 * @param LPTIMxSource This parameter can be one of the following values:
1940 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1941 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1942 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1943 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1944 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
1945 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
1946 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
1947 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
1948 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1 (*)
1949 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
1950 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI (*)
1951 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
1952 *
1953 * (*) value not defined in all devices.
1954 * @retval None
1955 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1956 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1957 {
1958 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
1959 }
1960
1961 /**
1962 * @brief Configure RNG clock source
1963 * @rmtoll CCIPR CLK48MSEL LL_RCC_SetRNGClockSource
1964 * @param RNGxSource This parameter can be one of the following values:
1965 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
1966 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
1967 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLQ
1968 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
1969 *
1970 * (*) value not defined in all devices.
1971 * @retval None
1972 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1973 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1974 {
1975 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
1976 }
1977
1978 #if defined(USB_DRD_FS)
1979 /**
1980 * @brief Configure USB clock source
1981 * @rmtoll CCIPR USBSEL LL_RCC_SetUSBClockSource
1982 * @param USBxSource This parameter can be one of the following values:
1983 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
1984 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1985 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLQ
1986 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
1987 *
1988 * (*) value not defined in all devices.
1989 * @retval None
1990 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1991 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1992 {
1993 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
1994 }
1995 #endif /* USB_DRD_FS */
1996
1997 /**
1998 * @brief Configure ADC clock source
1999 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2000 * @param ADCxSource This parameter can be one of the following values:
2001 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2002 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLP
2003 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2004 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2005 * @retval None
2006 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2007 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2008 {
2009 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2010 }
2011
2012 /**
2013 * @brief Get USARTx clock source
2014 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
2015 * @param USARTx This parameter can be one of the following values:
2016 * @arg @ref LL_RCC_USART1_CLKSOURCE
2017 * @arg @ref LL_RCC_USART2_CLKSOURCE
2018 *
2019 * (*) value not defined in all devices.
2020 * @retval Returned value can be one of the following values:
2021 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
2022 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2023 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2024 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2025 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2026 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2027 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2028 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2029 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2030 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2031 {
2032 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
2033 }
2034
2035 /**
2036 * @brief Get LPUARTx clock source
2037 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
2038 * @param LPUARTx This parameter can be one of the following values:
2039 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2040 * @retval Returned value can be one of the following values:
2041 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2042 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2043 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2044 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2045 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1
2046 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK
2047 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI
2048 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE
2049 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_PCLK1 (*)
2050 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_SYSCLK (*)
2051 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_HSI (*)
2052 * @arg @ref LL_RCC_LPUART3_CLKSOURCE_LSE (*)
2053 *
2054 * (*) value not defined in all devices.
2055 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2056 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2057 {
2058 return (uint32_t)((READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U)));
2059 }
2060
2061 /**
2062 * @brief Get I2Cx clock source
2063 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
2064 * @param I2Cx This parameter can be one of the following values:
2065 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2066 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2067 *
2068 * (*) value not defined in all devices.
2069 * @retval Returned value can be one of the following values:
2070 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2071 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2072 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2073 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2074 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2075 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2076 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2077 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2078 {
2079 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
2080 return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x0000FF0000U) >> 16U)) >> ((I2Cx & 0x0000FF0000U) >> 16U)) | \
2081 (I2Cx & 0xFFFF0000U));
2082 }
2083
2084 /**
2085 * @brief Get TIMx clock source
2086 * @rmtoll CCIPR TIMxSEL LL_RCC_GetTIMClockSource
2087 * @param TIMx This parameter can be one of the following values:
2088 * @arg @ref LL_RCC_TIM1_CLKSOURCE
2089 * @arg @ref LL_RCC_TIM15_CLKSOURCE
2090 * @retval Returned value can be one of the following values:
2091 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLLQ
2092 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
2093 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLLQ
2094 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
2095 */
LL_RCC_GetTIMClockSource(uint32_t TIMx)2096 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
2097 {
2098 return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx);
2099 }
2100
2101 /**
2102 * @brief Get LPTIMx clock source
2103 * @rmtoll CCIPR LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2104 * CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource
2105 * CCIPR LPTIM3SEL LL_RCC_GetLPTIMClockSource
2106 * @param LPTIMx This parameter can be one of the following values:
2107 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2108 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2109 * @retval Returned value can be one of the following values:
2110 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2111 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2112 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2113 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2114 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2115 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2116 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2117 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2118 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1 (*)
2119 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
2120 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI (*)
2121 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
2122 *
2123 * (*) value not defined in all devices.
2124 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2125 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2126 {
2127 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
2128 }
2129
2130 /**
2131 * @brief Get RNGx clock source
2132 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
2133 * @param RNGx This parameter can be one of the following values:
2134 * @arg @ref LL_RCC_RNG_CLKSOURCE
2135 * @retval Returned value can be one of the following values:
2136 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
2137 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
2138 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLQ
2139 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
2140 *
2141 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2142 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2143 {
2144 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2145 }
2146
2147 #if defined (USB_DRD_FS)
2148 /**
2149 * @brief Get USBx clock source
2150 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
2151 * @param USBx This parameter can be one of the following values:
2152 * @arg @ref LL_RCC_USB_CLKSOURCE
2153 * @retval Returned value can be one of the following values:
2154 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
2155 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2156 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLQ
2157 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2158 *
2159 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2160 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2161 {
2162 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
2163 }
2164 #endif /* USB_DRD_FS */
2165
2166 /**
2167 * @brief Get ADCx clock source
2168 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2169 * @param ADCx This parameter can be one of the following values:
2170 * @arg @ref LL_RCC_ADC_CLKSOURCE
2171 * @retval Returned value can be one of the following values:
2172 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2173 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLP
2174 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2175 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2176 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2177 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2178 {
2179 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2180 }
2181
2182 /**
2183 * @}
2184 */
2185
2186 /** @defgroup RCC_LL_EF_RTC RTC
2187 * @{
2188 */
2189
2190 /**
2191 * @brief Set RTC Clock Source
2192 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2193 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2194 * set). The BDRST bit can be used to reset them.
2195 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2196 * @param Source This parameter can be one of the following values:
2197 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2198 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2199 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2200 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2201 * @retval None
2202 */
LL_RCC_SetRTCClockSource(uint32_t Source)2203 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2204 {
2205 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2206 }
2207
2208 /**
2209 * @brief Get RTC Clock Source
2210 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2211 * @retval Returned value can be one of the following values:
2212 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2213 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2214 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2215 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2216 */
LL_RCC_GetRTCClockSource(void)2217 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2218 {
2219 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2220 }
2221
2222 /**
2223 * @brief Enable RTC
2224 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2225 * @retval None
2226 */
LL_RCC_EnableRTC(void)2227 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2228 {
2229 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2230 }
2231
2232 /**
2233 * @brief Disable RTC
2234 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2235 * @retval None
2236 */
LL_RCC_DisableRTC(void)2237 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2238 {
2239 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2240 }
2241
2242 /**
2243 * @brief Check if RTC has been enabled or not
2244 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2245 * @retval State of bit (1 or 0).
2246 */
LL_RCC_IsEnabledRTC(void)2247 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2248 {
2249 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2250 }
2251
2252 /**
2253 * @brief Force the Backup domain reset
2254 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2255 * @retval None
2256 */
LL_RCC_ForceBackupDomainReset(void)2257 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2258 {
2259 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2260 }
2261
2262 /**
2263 * @brief Release the Backup domain reset
2264 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2265 * @retval None
2266 */
LL_RCC_ReleaseBackupDomainReset(void)2267 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2268 {
2269 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2270 }
2271
2272 /**
2273 * @}
2274 */
2275
2276 /** @defgroup RCC_LL_EF_PLL PLL
2277 * @{
2278 */
2279
2280 /**
2281 * @brief Enable PLL
2282 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2283 * @retval None
2284 */
LL_RCC_PLL_Enable(void)2285 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2286 {
2287 SET_BIT(RCC->CR, RCC_CR_PLLON);
2288 }
2289
2290 /**
2291 * @brief Disable PLL
2292 * @note Cannot be disabled if the PLL clock is used as the system clock
2293 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2294 * @retval None
2295 */
LL_RCC_PLL_Disable(void)2296 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2297 {
2298 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2299 }
2300
2301 /**
2302 * @brief Check if PLL Ready
2303 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2304 * @retval State of bit (1 or 0).
2305 */
LL_RCC_PLL_IsReady(void)2306 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2307 {
2308 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
2309 }
2310
2311 /** @defgroup RCC_LL_EF_HSI48 HSI48
2312 * @{
2313 */
2314 #if defined(RCC_CRRCR_HSI48ON)
2315 /**
2316 * @brief Enable HSI48
2317 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
2318 * @retval None
2319 */
LL_RCC_HSI48_Enable(void)2320 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
2321 {
2322 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2323 }
2324
2325 /**
2326 * @brief Disable HSI48
2327 * @note Cannot be disabled if the HSI48 clock is used as the system clock
2328 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
2329 * @retval None
2330 */
LL_RCC_HSI48_Disable(void)2331 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2332 {
2333 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2334 }
2335 #endif /* RCC_CRRCR_HSI48ON */
2336 #if defined(RCC_CRRCR_HSI48ON)
2337 /**
2338 * @brief Check if HSI48 Ready
2339 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
2340 * @retval State of bit (1 or 0).
2341 */
LL_RCC_HSI48_IsReady(void)2342 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2343 {
2344 return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
2345 }
2346 #endif /* RCC_CRRCR_HSI48ON */
2347 #if defined(RCC_CRRCR_HSI48ON)
2348 /**
2349 * @brief Get HSI Calibration value
2350 * @note When HSITRIM is written, HSICAL is updated with the sum of
2351 * HSITRIM and the factory trim value
2352 * @rmtoll CRRCR HSICAL LL_RCC_HSI_GetCalibration
2353 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
2354 */
LL_RCC_HSI48_GetCalibration(void)2355 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2356 {
2357 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2358 }
2359
2360 /**
2361 * @brief Set HSI Calibration trimming
2362 * @note user-programmable trimming value that is added to the HSICAL
2363 * @note Default value is 16, which, when added to the HSICAL value,
2364 * should trim the HSI to 16 MHz +/- 1 %
2365 * @rmtoll CRRCR HSITRIM LL_RCC_HSI_SetCalibTrimming
2366 * @param Value Between Min_Data = 0 and Max_Data = 31
2367 * @retval None
2368 */
LL_RCC_HSI48_SetCalibration(uint32_t Value)2369 __STATIC_INLINE void LL_RCC_HSI48_SetCalibration(uint32_t Value)
2370 {
2371 MODIFY_REG(RCC->CRRCR, RCC_CRRCR_HSI48CAL, Value << RCC_CRRCR_HSI48CAL_Pos);
2372 }
2373 #endif /* RCC_CRRCR_HSI48ON */
2374 /**
2375 * @brief Configure PLLR used for SYSCLK Domain
2376 * @note PLL Source and PLLM Divider can be written only when PLL
2377 * is disabled.
2378 * @note PLLN/PLLR can be written only when PLL is disabled.
2379 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2380 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2381 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2382 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2383 * @param Source This parameter can be one of the following values:
2384 * @arg @ref LL_RCC_PLLSOURCE_NONE
2385 * @arg @ref LL_RCC_PLLSOURCE_MSI
2386 * @arg @ref LL_RCC_PLLSOURCE_HSI
2387 * @arg @ref LL_RCC_PLLSOURCE_HSE
2388 * @param PLLM This parameter can be one of the following values:
2389 * @arg @ref LL_RCC_PLLM_DIV_1
2390 * @arg @ref LL_RCC_PLLM_DIV_2
2391 * @arg @ref LL_RCC_PLLM_DIV_3
2392 * @arg @ref LL_RCC_PLLM_DIV_4
2393 * @arg @ref LL_RCC_PLLM_DIV_5
2394 * @arg @ref LL_RCC_PLLM_DIV_6
2395 * @arg @ref LL_RCC_PLLM_DIV_7
2396 * @arg @ref LL_RCC_PLLM_DIV_8
2397 *
2398 * @param PLLN Between 4 and 127
2399 * @param PLLR This parameter can be one of the following values:
2400 * @arg @ref LL_RCC_PLLR_DIV_2
2401 * @arg @ref LL_RCC_PLLR_DIV_4
2402 * @arg @ref LL_RCC_PLLR_DIV_6
2403 * @arg @ref LL_RCC_PLLR_DIV_8
2404 * @retval None
2405 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2406 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2407 {
2408 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2409 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
2410 }
2411
2412 /**
2413 * @brief Configure PLL used for Q domain clock
2414 * @note PLL Source and PLLM Divider can be written only when PLL.
2415 * @note PLLN/PLLQ can be written only when PLL is disabled.
2416 * @note This can be selected for USB, RNG
2417 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_PLLQ\n
2418 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_PLLQ\n
2419 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_PLLQ\n
2420 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_PLLQ
2421 * @param Source This parameter can be one of the following values:
2422 * @arg @ref LL_RCC_PLLSOURCE_NONE
2423 * @arg @ref LL_RCC_PLLSOURCE_MSI
2424 * @arg @ref LL_RCC_PLLSOURCE_HSI
2425 * @arg @ref LL_RCC_PLLSOURCE_HSE
2426 * @param PLLM This parameter can be one of the following values:
2427 * @arg @ref LL_RCC_PLLM_DIV_1
2428 * @arg @ref LL_RCC_PLLM_DIV_2
2429 * @arg @ref LL_RCC_PLLM_DIV_3
2430 * @arg @ref LL_RCC_PLLM_DIV_4
2431 * @arg @ref LL_RCC_PLLM_DIV_5
2432 * @arg @ref LL_RCC_PLLM_DIV_6
2433 * @arg @ref LL_RCC_PLLM_DIV_7
2434 * @arg @ref LL_RCC_PLLM_DIV_8
2435 *
2436 * @param PLLN Between 4 and 127
2437 * @param PLLQ This parameter can be one of the following values:
2438 * @arg @ref LL_RCC_PLLQ_DIV_2
2439 * @arg @ref LL_RCC_PLLQ_DIV_4
2440 * @arg @ref LL_RCC_PLLQ_DIV_6
2441 * @arg @ref LL_RCC_PLLQ_DIV_8
2442 * @retval None
2443 */
LL_RCC_PLL_ConfigDomain_PLLQ(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2444 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLQ(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2445 {
2446 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2447 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2448 }
2449
2450 /**
2451 * @brief Configure PLL used for P domain clock
2452 * @note PLL Source and PLLM Divider can be written only when PLL.
2453 * @note PLLN/PLLQ can be written only when PLL is disabled.
2454 * @note This can be selected for ADC, TIM1 , TIM15
2455 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_PLLP\n
2456 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_PLLP\n
2457 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_PLLP\n
2458 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_PLLP
2459 * @param Source This parameter can be one of the following values:
2460 * @arg @ref LL_RCC_PLLSOURCE_NONE
2461 * @arg @ref LL_RCC_PLLSOURCE_MSI
2462 * @arg @ref LL_RCC_PLLSOURCE_HSI
2463 * @arg @ref LL_RCC_PLLSOURCE_HSE
2464 * @param PLLM This parameter can be one of the following values:
2465 * @arg @ref LL_RCC_PLLM_DIV_1
2466 * @arg @ref LL_RCC_PLLM_DIV_2
2467 * @arg @ref LL_RCC_PLLM_DIV_3
2468 * @arg @ref LL_RCC_PLLM_DIV_4
2469 * @arg @ref LL_RCC_PLLM_DIV_5
2470 * @arg @ref LL_RCC_PLLM_DIV_6
2471 * @arg @ref LL_RCC_PLLM_DIV_7
2472 * @arg @ref LL_RCC_PLLM_DIV_8
2473 *
2474 * @param PLLN Between 4 and 127
2475 * @param PLLP This parameter can be one of the following values:
2476 * @arg @ref LL_RCC_PLLP_DIV_2
2477 * @arg @ref LL_RCC_PLLP_DIV_3
2478 * @arg @ref LL_RCC_PLLP_DIV_4
2479 * @arg @ref LL_RCC_PLLP_DIV_5
2480 * @arg @ref LL_RCC_PLLP_DIV_6
2481 * @arg @ref LL_RCC_PLLP_DIV_7
2482 * @arg @ref LL_RCC_PLLP_DIV_8
2483 * @arg @ref LL_RCC_PLLP_DIV_9
2484 * @arg @ref LL_RCC_PLLP_DIV_10
2485 * @arg @ref LL_RCC_PLLP_DIV_11
2486 * @arg @ref LL_RCC_PLLP_DIV_12
2487 * @arg @ref LL_RCC_PLLP_DIV_13
2488 * @arg @ref LL_RCC_PLLP_DIV_14
2489 * @arg @ref LL_RCC_PLLP_DIV_15
2490 * @arg @ref LL_RCC_PLLP_DIV_16
2491 * @arg @ref LL_RCC_PLLP_DIV_17
2492 * @arg @ref LL_RCC_PLLP_DIV_18
2493 * @arg @ref LL_RCC_PLLP_DIV_19
2494 * @arg @ref LL_RCC_PLLP_DIV_20
2495 * @arg @ref LL_RCC_PLLP_DIV_21
2496 * @arg @ref LL_RCC_PLLP_DIV_22
2497 * @arg @ref LL_RCC_PLLP_DIV_23
2498 * @arg @ref LL_RCC_PLLP_DIV_24
2499 * @arg @ref LL_RCC_PLLP_DIV_25
2500 * @arg @ref LL_RCC_PLLP_DIV_26
2501 * @arg @ref LL_RCC_PLLP_DIV_27
2502 * @arg @ref LL_RCC_PLLP_DIV_28
2503 * @arg @ref LL_RCC_PLLP_DIV_29
2504 * @arg @ref LL_RCC_PLLP_DIV_30
2505 * @arg @ref LL_RCC_PLLP_DIV_31
2506 * @arg @ref LL_RCC_PLLP_DIV_32
2507 * @retval None
2508 */
LL_RCC_PLL_ConfigDomain_PLLP(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2509 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLP(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2510 {
2511 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2512 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2513 }
2514
2515 /**
2516 * @brief Get Main PLL multiplication factor for VCO
2517 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2518 * @retval Between 4 and 127
2519 */
LL_RCC_PLL_GetN(void)2520 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2521 {
2522 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2523 }
2524
2525 /**
2526 * @brief Get Main PLL division factor for PLLP
2527 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
2528 * @retval Returned value can be one of the following values:
2529 * @arg @ref LL_RCC_PLLP_DIV_2
2530 * @arg @ref LL_RCC_PLLP_DIV_3
2531 * @arg @ref LL_RCC_PLLP_DIV_4
2532 * @arg @ref LL_RCC_PLLP_DIV_5
2533 * @arg @ref LL_RCC_PLLP_DIV_6
2534 * @arg @ref LL_RCC_PLLP_DIV_7
2535 * @arg @ref LL_RCC_PLLP_DIV_8
2536 * @arg @ref LL_RCC_PLLP_DIV_9
2537 * @arg @ref LL_RCC_PLLP_DIV_10
2538 * @arg @ref LL_RCC_PLLP_DIV_11
2539 * @arg @ref LL_RCC_PLLP_DIV_12
2540 * @arg @ref LL_RCC_PLLP_DIV_13
2541 * @arg @ref LL_RCC_PLLP_DIV_14
2542 * @arg @ref LL_RCC_PLLP_DIV_15
2543 * @arg @ref LL_RCC_PLLP_DIV_16
2544 * @arg @ref LL_RCC_PLLP_DIV_17
2545 * @arg @ref LL_RCC_PLLP_DIV_18
2546 * @arg @ref LL_RCC_PLLP_DIV_19
2547 * @arg @ref LL_RCC_PLLP_DIV_20
2548 * @arg @ref LL_RCC_PLLP_DIV_21
2549 * @arg @ref LL_RCC_PLLP_DIV_22
2550 * @arg @ref LL_RCC_PLLP_DIV_23
2551 * @arg @ref LL_RCC_PLLP_DIV_24
2552 * @arg @ref LL_RCC_PLLP_DIV_25
2553 * @arg @ref LL_RCC_PLLP_DIV_26
2554 * @arg @ref LL_RCC_PLLP_DIV_27
2555 * @arg @ref LL_RCC_PLLP_DIV_28
2556 * @arg @ref LL_RCC_PLLP_DIV_29
2557 * @arg @ref LL_RCC_PLLP_DIV_30
2558 * @arg @ref LL_RCC_PLLP_DIV_31
2559 */
LL_RCC_PLL_GetP(void)2560 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
2561 {
2562 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
2563 }
2564
2565 /**
2566 * @brief Get Main PLL division factor for PLLQ
2567 * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
2568 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
2569 * @retval Returned value can be one of the following values:
2570 * @arg @ref LL_RCC_PLLQ_DIV_2
2571 * @arg @ref LL_RCC_PLLQ_DIV_4
2572 * @arg @ref LL_RCC_PLLQ_DIV_6
2573 * @arg @ref LL_RCC_PLLQ_DIV_8
2574 */
LL_RCC_PLL_GetQ(void)2575 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
2576 {
2577 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
2578 }
2579
2580 /**
2581 * @brief Get Main PLL division factor for PLLR
2582 * @note Used for PLLCLK (system clock)
2583 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
2584 * @retval Returned value can be one of the following values:
2585 * @arg @ref LL_RCC_PLLR_DIV_2
2586 * @arg @ref LL_RCC_PLLR_DIV_4
2587 * @arg @ref LL_RCC_PLLR_DIV_6
2588 * @arg @ref LL_RCC_PLLR_DIV_8
2589 */
LL_RCC_PLL_GetR(void)2590 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
2591 {
2592 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
2593 }
2594
2595 /**
2596 * @brief Get the oscillator used as PLL clock source.
2597 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
2598 * @retval Returned value can be one of the following values:
2599 * @arg @ref LL_RCC_PLLSOURCE_NONE
2600 * @arg @ref LL_RCC_PLLSOURCE_MSI
2601 * @arg @ref LL_RCC_PLLSOURCE_HSI
2602 * @arg @ref LL_RCC_PLLSOURCE_HSE
2603 */
LL_RCC_PLL_GetMainSource(void)2604 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2605 {
2606 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
2607 }
2608
2609 /**
2610 * @brief Get Division factor for the main PLL and other PLL
2611 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetM
2612 * @retval Returned value can be one of the following values:
2613 * @arg @ref LL_RCC_PLLM_DIV_1
2614 * @arg @ref LL_RCC_PLLM_DIV_2
2615 * @arg @ref LL_RCC_PLLM_DIV_3
2616 * @arg @ref LL_RCC_PLLM_DIV_4
2617 * @arg @ref LL_RCC_PLLM_DIV_5
2618 * @arg @ref LL_RCC_PLLM_DIV_6
2619 * @arg @ref LL_RCC_PLLM_DIV_7
2620 * @arg @ref LL_RCC_PLLM_DIV_8
2621 *
2622 */
LL_RCC_PLL_GetM(void)2623 __STATIC_INLINE uint32_t LL_RCC_PLL_GetM(void)
2624 {
2625 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
2626 }
2627
2628 /**
2629 * @brief Enable PLL output mapped on P domain clock
2630 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_PLLP
2631 * @note User shall check that PLL enable is not done through
2632 * other functions (ex: I2S1)
2633 * @retval None
2634 */
LL_RCC_PLL_EnableDomain_PLLP(void)2635 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_PLLP(void)
2636 {
2637 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2638 }
2639
2640 /**
2641 * @brief Disable PLL output mapped on P domain clock
2642 * @note Cannot be disabled if the PLL clock is used as the system clock
2643 * @note User shall check that PLL is not used by any other peripheral
2644 * (ex: I2S1)
2645 * @note In order to save power, when the PLLCLK of the PLL is
2646 * not used, should be 0
2647 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_PLLP
2648 * @retval None
2649 */
LL_RCC_PLL_DisableDomain_PLLP(void)2650 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_PLLP(void)
2651 {
2652 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2653 }
2654
2655 /**
2656 * @brief Check if PLL output mapped on P domain clock is enabled
2657 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_PLLP
2658 * @retval State of bit (1 or 0).
2659 */
LL_RCC_PLL_IsEnabledDomain_PLLP(void)2660 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_PLLP(void)
2661 {
2662 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
2663 }
2664 /**
2665 * @brief Enable PLL output mapped on 48MHz domain clock
2666 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_PLLQ
2667 * @retval None
2668 */
LL_RCC_PLL_EnableDomain_PLLQ(void)2669 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_PLLQ(void)
2670 {
2671 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2672 }
2673
2674 /**
2675 * @brief Disable PLL output mapped on 48MHz domain clock
2676 * @note Cannot be disabled if the PLL clock is used as the system
2677 * clock
2678 * @note In order to save power, when the PLLCLK of the PLL is
2679 * not used, should be 0
2680 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_PLLQ
2681 * @retval None
2682 */
LL_RCC_PLL_DisableDomain_PLLQ(void)2683 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_PLLQ(void)
2684 {
2685 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2686 }
2687
2688 /**
2689 * @brief Check if PLL output mapped on Q domain clock is enabled
2690 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_PLLQ
2691 * @retval State of bit (1 or 0).
2692 */
LL_RCC_PLL_IsEnabledDomain_PLLQ(void)2693 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_PLLQ(void)
2694 {
2695 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
2696 }
2697
2698 /**
2699 * @brief Enable PLL output mapped on SYSCLK domain
2700 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
2701 * @retval None
2702 */
LL_RCC_PLL_EnableDomain_SYS(void)2703 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
2704 {
2705 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2706 }
2707
2708 /**
2709 * @brief Disable PLL output mapped on SYSCLK domain
2710 * @note Cannot be disabled if the PLL clock is used as the system
2711 * clock
2712 * @note In order to save power, when the PLLCLK of the PLL is
2713 * not used, Main PLL should be 0
2714 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
2715 * @retval None
2716 */
LL_RCC_PLL_DisableDomain_SYS(void)2717 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
2718 {
2719 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2720 }
2721
2722 /**
2723 * @brief Check if PLL output mapped on tR(SYS) domain clock is enabled
2724 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
2725 * @retval State of bit (1 or 0).
2726 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)2727 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
2728 {
2729 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
2730 }
2731
2732 /**
2733 * @}
2734 */
2735
2736 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2737 * @{
2738 */
2739
2740 /**
2741 * @brief Clear LSI ready interrupt flag
2742 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2743 * @retval None
2744 */
LL_RCC_ClearFlag_LSIRDY(void)2745 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2746 {
2747 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
2748 }
2749
2750 /**
2751 * @brief Clear LSE ready interrupt flag
2752 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2753 * @retval None
2754 */
LL_RCC_ClearFlag_LSERDY(void)2755 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2756 {
2757 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2758 }
2759
2760 /**
2761 * @brief Clear MSI ready interrupt flag
2762 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
2763 * @retval None
2764 */
LL_RCC_ClearFlag_MSIRDY(void)2765 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
2766 {
2767 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
2768 }
2769
2770 /**
2771 * @brief Clear HSI ready interrupt flag
2772 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2773 * @retval None
2774 */
LL_RCC_ClearFlag_HSIRDY(void)2775 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2776 {
2777 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2778 }
2779
2780 /**
2781 * @brief Clear HSE ready interrupt flag
2782 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2783 * @retval None
2784 */
LL_RCC_ClearFlag_HSERDY(void)2785 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2786 {
2787 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2788 }
2789
2790 /**
2791 * @brief Clear PLL ready interrupt flag
2792 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2793 * @retval None
2794 */
LL_RCC_ClearFlag_PLLRDY(void)2795 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2796 {
2797 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
2798 }
2799
2800 /**
2801 * @brief Clear Clock security system interrupt flag
2802 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2803 * @retval None
2804 */
LL_RCC_ClearFlag_CSS(void)2805 __STATIC_INLINE void LL_RCC_ClearFlag_CSS(void)
2806 {
2807 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
2808 }
2809
2810 /**
2811 * @brief Clear LSE Clock security system interrupt flag
2812 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
2813 * @retval None
2814 */
LL_RCC_ClearFlag_LSECSS(void)2815 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
2816 {
2817 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
2818 }
2819 #if defined(RCC_CRRCR_HSI48ON)
2820 /**
2821 * @brief Clear LSE Clock security system interrupt flag
2822 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
2823 * @retval None
2824 */
LL_RCC_ClearFlag_HSI48RDY(void)2825 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
2826 {
2827 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
2828 }
2829 #endif /* RCC_CRRCR_HSI48ON */
2830 /**
2831 * @brief Check if LSI ready interrupt occurred or not
2832 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2833 * @retval State of bit (1 or 0).
2834 */
LL_RCC_IsActiveFlag_LSIRDY(void)2835 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2836 {
2837 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
2838 }
2839
2840 /**
2841 * @brief Check if LSE ready interrupt occurred or not
2842 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2843 * @retval State of bit (1 or 0).
2844 */
LL_RCC_IsActiveFlag_LSERDY(void)2845 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2846 {
2847 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
2848 }
2849
2850 /**
2851 * @brief Check if MSI ready interrupt occurred or not
2852 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
2853 * @retval State of bit (1 or 0).
2854 */
LL_RCC_IsActiveFlag_MSIRDY(void)2855 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
2856 {
2857 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL);
2858 }
2859
2860 /**
2861 * @brief Check if HSI ready interrupt occurred or not
2862 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2863 * @retval State of bit (1 or 0).
2864 */
LL_RCC_IsActiveFlag_HSIRDY(void)2865 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2866 {
2867 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
2868 }
2869
2870 /**
2871 * @brief Check if HSE ready interrupt occurred or not
2872 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2873 * @retval State of bit (1 or 0).
2874 */
LL_RCC_IsActiveFlag_HSERDY(void)2875 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2876 {
2877 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
2878 }
2879
2880 /**
2881 * @brief Check if PLL ready interrupt occurred or not
2882 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2883 * @retval State of bit (1 or 0).
2884 */
LL_RCC_IsActiveFlag_PLLRDY(void)2885 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2886 {
2887 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
2888 }
2889 #if defined(RCC_CRRCR_HSI48ON)
2890 /**
2891 * @brief Check if HSI48 ready interrupt occurred or not
2892 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
2893 * @retval State of bit (1 or 0).
2894 */
LL_RCC_IsActiveFlag_HSI48RDY(void)2895 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
2896 {
2897 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
2898 }
2899 #endif /* RCC_CRRCR_HSI48ON */
2900 /**
2901 * @brief Check if Clock security system interrupt occurred or not
2902 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2903 * @retval State of bit (1 or 0).
2904 */
LL_RCC_IsActiveFlag_LSECSS(void)2905 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
2906 {
2907 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
2908 }
2909
2910 /**
2911 * @brief Check if LSE Clock security system interrupt occurred or not
2912 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
2913 * @retval State of bit (1 or 0).
2914 */
LL_RCC_IsActiveFlag_CSS(void)2915 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSS(void)
2916 {
2917 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
2918 }
2919
2920 /**
2921 * @brief Check if RCC flag Watchdog reset is set or not.
2922 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2923 * @retval State of bit (1 or 0).
2924 */
LL_RCC_IsActiveFlag_IWDGRST(void)2925 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2926 {
2927 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
2928 }
2929
2930 /**
2931 * @brief Check if RCC flag Low Power reset is set or not.
2932 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2933 * @retval State of bit (1 or 0).
2934 */
LL_RCC_IsActiveFlag_LPWRRST(void)2935 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2936 {
2937 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
2938 }
2939
2940 /**
2941 * @brief Check if RCC flag is set or not.
2942 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2943 * @retval State of bit (1 or 0).
2944 */
LL_RCC_IsActiveFlag_OBLRST(void)2945 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2946 {
2947 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
2948 }
2949
2950 /**
2951 * @brief Check if RCC flag Pin reset is set or not.
2952 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2953 * @retval State of bit (1 or 0).
2954 */
LL_RCC_IsActiveFlag_PINRST(void)2955 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2956 {
2957 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
2958 }
2959
2960 /**
2961 * @brief Check if RCC flag Software reset is set or not.
2962 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2963 * @retval State of bit (1 or 0).
2964 */
LL_RCC_IsActiveFlag_SFTRST(void)2965 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2966 {
2967 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
2968 }
2969
2970 /**
2971 * @brief Check if RCC flag Window Watchdog reset is set or not.
2972 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2973 * @retval State of bit (1 or 0).
2974 */
LL_RCC_IsActiveFlag_WWDGRST(void)2975 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2976 {
2977 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
2978 }
2979
2980 /**
2981 * @brief Check if RCC flag PWR reset is set or not.
2982 * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST
2983 * @retval State of bit (1 or 0).
2984 */
LL_RCC_IsActiveFlag_PWRRST(void)2985 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
2986 {
2987 return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL);
2988 }
2989
2990 /**
2991 * @brief Set RMVF bit to clear the reset flags.
2992 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2993 * @retval None
2994 */
LL_RCC_ClearResetFlags(void)2995 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2996 {
2997 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2998 }
2999
3000 /**
3001 * @}
3002 */
3003
3004 /** @defgroup RCC_LL_EF_IT_Management IT Management
3005 * @{
3006 */
3007
3008 /**
3009 * @brief Enable LSI ready interrupt
3010 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
3011 * @retval None
3012 */
LL_RCC_EnableIT_LSIRDY(void)3013 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
3014 {
3015 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3016 }
3017
3018 /**
3019 * @brief Enable LSE ready interrupt
3020 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
3021 * @retval None
3022 */
LL_RCC_EnableIT_LSERDY(void)3023 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
3024 {
3025 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3026 }
3027
3028 /**
3029 * @brief Enable MSI ready interrupt
3030 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
3031 * @retval None
3032 */
LL_RCC_EnableIT_MSIRDY(void)3033 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
3034 {
3035 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
3036 }
3037
3038 /**
3039 * @brief Enable HSI ready interrupt
3040 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
3041 * @retval None
3042 */
LL_RCC_EnableIT_HSIRDY(void)3043 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3044 {
3045 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3046 }
3047
3048 /**
3049 * @brief Enable HSE ready interrupt
3050 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3051 * @retval None
3052 */
LL_RCC_EnableIT_HSERDY(void)3053 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3054 {
3055 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3056 }
3057
3058 /**
3059 * @brief Enable PLL ready interrupt
3060 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
3061 * @retval None
3062 */
LL_RCC_EnableIT_PLLRDY(void)3063 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
3064 {
3065 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3066 }
3067 #if defined(RCC_CRRCR_HSI48ON)
3068 /**
3069 * @brief Enable HSI48 ready interrupt
3070 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
3071 * @retval None
3072 */
LL_RCC_EnableIT_HSI48RDY(void)3073 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
3074 {
3075 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
3076 }
3077 #endif /* RCC_CRRCR_HSI48ON */
3078 /**
3079 * @brief Enable LSE clock security system interrupt
3080 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
3081 * @retval None
3082 */
LL_RCC_EnableIT_LSECSS(void)3083 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
3084 {
3085 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
3086 }
3087
3088 /**
3089 * @brief Disable LSI ready interrupt
3090 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
3091 * @retval None
3092 */
LL_RCC_DisableIT_LSIRDY(void)3093 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
3094 {
3095 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3096 }
3097
3098 /**
3099 * @brief Disable LSE ready interrupt
3100 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3101 * @retval None
3102 */
LL_RCC_DisableIT_LSERDY(void)3103 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3104 {
3105 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3106 }
3107
3108 /**
3109 * @brief Disable MSI ready interrupt
3110 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
3111 * @retval None
3112 */
LL_RCC_DisableIT_MSIRDY(void)3113 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
3114 {
3115 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
3116 }
3117
3118 /**
3119 * @brief Disable HSI ready interrupt
3120 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3121 * @retval None
3122 */
LL_RCC_DisableIT_HSIRDY(void)3123 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3124 {
3125 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3126 }
3127
3128 /**
3129 * @brief Disable HSE ready interrupt
3130 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3131 * @retval None
3132 */
LL_RCC_DisableIT_HSERDY(void)3133 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3134 {
3135 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3136 }
3137
3138 /**
3139 * @brief Disable PLL ready interrupt
3140 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
3141 * @retval None
3142 */
LL_RCC_DisableIT_PLLRDY(void)3143 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
3144 {
3145 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3146 }
3147 #if defined(RCC_CRRCR_HSI48ON)
3148 /**
3149 * @brief Disable HSI48 ready interrupt
3150 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
3151 * @retval None
3152 */
LL_RCC_DisableIT_HSI48RDY(void)3153 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
3154 {
3155 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
3156 }
3157 #endif /* RCC_CRRCR_HSI48ON */
3158 /**
3159 * @brief Disable LSE clock security system interrupt
3160 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
3161 * @retval None
3162 */
LL_RCC_DisableIT_LSECSS(void)3163 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
3164 {
3165 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
3166 }
3167
3168 /**
3169 * @brief Checks if LSI ready interrupt source is enabled or disabled.
3170 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
3171 * @retval State of bit (1 or 0).
3172 */
LL_RCC_IsEnabledIT_LSIRDY(void)3173 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
3174 {
3175 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
3176 }
3177
3178 /**
3179 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3180 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3181 * @retval State of bit (1 or 0).
3182 */
LL_RCC_IsEnabledIT_LSERDY(void)3183 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3184 {
3185 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
3186 }
3187
3188 /**
3189 * @brief Checks if MSI ready interrupt source is enabled or disabled.
3190 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
3191 * @retval State of bit (1 or 0).
3192 */
LL_RCC_IsEnabledIT_MSIRDY(void)3193 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
3194 {
3195 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL);
3196 }
3197
3198 /**
3199 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3200 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3201 * @retval State of bit (1 or 0).
3202 */
LL_RCC_IsEnabledIT_HSIRDY(void)3203 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3204 {
3205 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
3206 }
3207
3208 /**
3209 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3210 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3211 * @retval State of bit (1 or 0).
3212 */
LL_RCC_IsEnabledIT_HSERDY(void)3213 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3214 {
3215 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
3216 }
3217
3218 /**
3219 * @brief Checks if PLL ready interrupt source is enabled or disabled.
3220 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
3221 * @retval State of bit (1 or 0).
3222 */
LL_RCC_IsEnabledIT_PLLRDY(void)3223 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
3224 {
3225 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
3226 }
3227 #if defined(RCC_CRRCR_HSI48ON)
3228 /**
3229 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
3230 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
3231 * @retval State of bit (1 or 0).
3232 */
LL_RCC_IsEnabledIT_HSI48RDY(void)3233 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
3234 {
3235 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
3236 }
3237 #endif /* RCC_CRRCR_HSI48ON */
3238 /**
3239 * @brief Checks if LSECSS interrupt source is enabled or disabled.
3240 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
3241 * @retval State of bit (1 or 0).
3242 */
LL_RCC_IsEnabledIT_LSECSS(void)3243 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
3244 {
3245 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
3246 }
3247
3248 /**
3249 * @}
3250 */
3251
3252 #if defined(USE_FULL_LL_DRIVER)
3253 /** @defgroup RCC_LL_EF_Init De-initialization function
3254 * @{
3255 */
3256 ErrorStatus LL_RCC_DeInit(void);
3257 /**
3258 * @}
3259 */
3260
3261 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3262 * @{
3263 */
3264 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3265 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3266 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3267 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3268 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
3269 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3270 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3271 #if defined (USB_DRD_FS)
3272 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
3273 #endif /* USB_DRD_FS */
3274 uint32_t LL_RCC_GetRTCClockFreq(void);
3275 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3276 /**
3277 * @}
3278 */
3279 #endif /* USE_FULL_LL_DRIVER */
3280
3281 /**
3282 * @}
3283 */
3284
3285 /**
3286 * @}
3287 */
3288
3289 #endif /* RCC */
3290
3291 /**
3292 * @}
3293 */
3294
3295 #ifdef __cplusplus
3296 }
3297 #endif
3298
3299 #endif /* __STM32U0xx_LL_RCC_H */
3300
