1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_I2C_H
21 #define STM32U0xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
64 * @{
65 */
66 typedef struct
67 {
68 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
69 This parameter must be set by referring to the STM32CubeMX Tool and
70 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_I2C_SetTiming(). */
74
75 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
76 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
77
78 This feature can be modified afterwards using unitary functions
79 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
80
81 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
82 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
83
84 This feature can be modified afterwards using unitary function
85 @ref LL_I2C_SetDigitalFilter(). */
86
87 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
88 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_I2C_SetOwnAddress1(). */
92
93 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
94 match code or next received byte.
95 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
96
97 This feature can be modified afterwards using unitary function
98 @ref LL_I2C_AcknowledgeNextData(). */
99
100 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
101 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
102
103 This feature can be modified afterwards using unitary function
104 @ref LL_I2C_SetOwnAddress1(). */
105 } LL_I2C_InitTypeDef;
106 /**
107 * @}
108 */
109 #endif /*USE_FULL_LL_DRIVER*/
110
111 /* Exported constants --------------------------------------------------------*/
112 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
113 * @{
114 */
115
116 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
117 * @brief Flags defines which can be used with LL_I2C_WriteReg function
118 * @{
119 */
120 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
121 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
122 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
123 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
124 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
125 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
126 /**
127 * @}
128 */
129
130 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
131 * @brief Flags defines which can be used with LL_I2C_ReadReg function
132 * @{
133 */
134 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
135 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
136 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
137 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
138 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
139 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
140 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
141 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
142 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
143 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
144 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
145 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
146 /**
147 * @}
148 */
149
150 /** @defgroup I2C_LL_EC_IT IT Defines
151 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
152 * @{
153 */
154 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
155 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
156 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
157 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
158 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
159 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
160 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
161 /**
162 * @}
163 */
164
165 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
166 * @{
167 */
168 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
169 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
170 /**
171 * @}
172 */
173
174 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
175 * @{
176 */
177 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
178 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
179 /**
180 * @}
181 */
182
183 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
184 * @{
185 */
186 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
187 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
188 /**
189 * @}
190 */
191
192 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
193 * @{
194 */
195 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
196 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
197 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
198 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
199 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
200 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
201 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
202 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
203 All Address2 are acknowledged. */
204 /**
205 * @}
206 */
207
208 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
209 * @{
210 */
211 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
212 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
213 /**
214 * @}
215 */
216
217 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
218 * @{
219 */
220 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
221 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
222 /**
223 * @}
224 */
225
226 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
227 * @{
228 */
229 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
230 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
231 /**
232 * @}
233 */
234
235 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
236 * @{
237 */
238 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
239 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
240 with no HW PEC comparison. */
241 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
242 with no HW PEC comparison. */
243 /**
244 * @}
245 */
246
247 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
248 * @{
249 */
250 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
251 /*!< Don't Generate Stop and Start condition. */
252 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
253 /*!< Generate Stop condition (Size should be set to 0). */
254 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
255 /*!< Generate Start for read request. */
256 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
257 /*!< Generate Start for write request. */
258 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
259 /*!< Generate Restart for read request, slave 7Bit address. */
260 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
261 /*!< Generate Restart for write request, slave 7Bit address. */
262 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
263 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
264 /*!< Generate Restart for read request, slave 10Bit address. */
265 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
266 /*!< Generate Restart for write request, slave 10Bit address.*/
267 /**
268 * @}
269 */
270
271 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
272 * @{
273 */
274 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
275 slave enters receiver mode. */
276 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
277 slave enters transmitter mode.*/
278 /**
279 * @}
280 */
281
282 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
283 * @{
284 */
285 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
286 transmission */
287 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
288 reception */
289 /**
290 * @}
291 */
292
293 /**
294 * @}
295 */
296
297 /* Exported macro ------------------------------------------------------------*/
298 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
299 * @{
300 */
301
302 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
303 * @{
304 */
305
306 /**
307 * @brief Write a value in I2C register
308 * @param __INSTANCE__ I2C Instance
309 * @param __REG__ Register to be written
310 * @param __VALUE__ Value to be written in the register
311 * @retval None
312 */
313 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
314
315 /**
316 * @brief Read a value in I2C register
317 * @param __INSTANCE__ I2C Instance
318 * @param __REG__ Register to be read
319 * @retval Register value
320 */
321 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
322 /**
323 * @}
324 */
325
326 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
327 * @{
328 */
329 /**
330 * @brief Configure the SDA setup, hold time and the SCL high, low period.
331 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
332 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
333 (tscldel = (SCLDEL+1)xtpresc)
334 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
335 (tsdadel = SDADELxtpresc)
336 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
337 (tsclh = (SCLH+1)xtpresc)
338 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
339 (tscll = (SCLL+1)xtpresc)
340 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
341 */
342 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
343 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
344 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
345 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
346 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
347 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
348 /**
349 * @}
350 */
351
352 /**
353 * @}
354 */
355
356 /* Exported functions --------------------------------------------------------*/
357 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
358 * @{
359 */
360
361 /** @defgroup I2C_LL_EF_Configuration Configuration
362 * @{
363 */
364
365 /**
366 * @brief Enable I2C peripheral (PE = 1).
367 * @rmtoll CR1 PE LL_I2C_Enable
368 * @param I2Cx I2C Instance.
369 * @retval None
370 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)371 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
372 {
373 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
374 }
375
376 /**
377 * @brief Disable I2C peripheral (PE = 0).
378 * @note When PE = 0, the I2C SCL and SDA lines are released.
379 * Internal state machines and status bits are put back to their reset value.
380 * When cleared, PE must be kept low for at least 3 APB clock cycles.
381 * @rmtoll CR1 PE LL_I2C_Disable
382 * @param I2Cx I2C Instance.
383 * @retval None
384 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)385 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
386 {
387 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
388 }
389
390 /**
391 * @brief Check if the I2C peripheral is enabled or disabled.
392 * @rmtoll CR1 PE LL_I2C_IsEnabled
393 * @param I2Cx I2C Instance.
394 * @retval State of bit (1 or 0).
395 */
LL_I2C_IsEnabled(const I2C_TypeDef * I2Cx)396 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
397 {
398 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
399 }
400
401 /**
402 * @brief Configure Noise Filters (Analog and Digital).
403 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
404 * The filters can only be programmed when the I2C is disabled (PE = 0).
405 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
406 * CR1 DNF LL_I2C_ConfigFilters
407 * @param I2Cx I2C Instance.
408 * @param AnalogFilter This parameter can be one of the following values:
409 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
410 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
411 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
412 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
413 * This parameter is used to configure the digital noise filter on SDA and SCL input.
414 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
415 * @retval None
416 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)417 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
418 {
419 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
420 }
421
422 /**
423 * @brief Configure Digital Noise Filter.
424 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
425 * This filter can only be programmed when the I2C is disabled (PE = 0).
426 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
427 * @param I2Cx I2C Instance.
428 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
429 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
430 * This parameter is used to configure the digital noise filter on SDA and SCL input.
431 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
432 * @retval None
433 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)434 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
435 {
436 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
437 }
438
439 /**
440 * @brief Get the current Digital Noise Filter configuration.
441 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
442 * @param I2Cx I2C Instance.
443 * @retval Value between Min_Data=0x0 and Max_Data=0xF
444 */
LL_I2C_GetDigitalFilter(const I2C_TypeDef * I2Cx)445 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
446 {
447 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
448 }
449
450 /**
451 * @brief Enable Analog Noise Filter.
452 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
453 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
454 * @param I2Cx I2C Instance.
455 * @retval None
456 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)457 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
458 {
459 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
460 }
461
462 /**
463 * @brief Disable Analog Noise Filter.
464 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
465 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
466 * @param I2Cx I2C Instance.
467 * @retval None
468 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)469 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
470 {
471 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
472 }
473
474 /**
475 * @brief Check if Analog Noise Filter is enabled or disabled.
476 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
477 * @param I2Cx I2C Instance.
478 * @retval State of bit (1 or 0).
479 */
LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef * I2Cx)480 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
481 {
482 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
483 }
484
485 /**
486 * @brief Enable DMA transmission requests.
487 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
488 * @param I2Cx I2C Instance.
489 * @retval None
490 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)491 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
492 {
493 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
494 }
495
496 /**
497 * @brief Disable DMA transmission requests.
498 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
499 * @param I2Cx I2C Instance.
500 * @retval None
501 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)502 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
503 {
504 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
505 }
506
507 /**
508 * @brief Check if DMA transmission requests are enabled or disabled.
509 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
510 * @param I2Cx I2C Instance.
511 * @retval State of bit (1 or 0).
512 */
LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef * I2Cx)513 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
514 {
515 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
516 }
517
518 /**
519 * @brief Enable DMA reception requests.
520 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
521 * @param I2Cx I2C Instance.
522 * @retval None
523 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)524 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
525 {
526 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
527 }
528
529 /**
530 * @brief Disable DMA reception requests.
531 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
532 * @param I2Cx I2C Instance.
533 * @retval None
534 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)535 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
536 {
537 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
538 }
539
540 /**
541 * @brief Check if DMA reception requests are enabled or disabled.
542 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
543 * @param I2Cx I2C Instance.
544 * @retval State of bit (1 or 0).
545 */
LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef * I2Cx)546 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
547 {
548 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
549 }
550
551 /**
552 * @brief Get the data register address used for DMA transfer
553 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
554 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
555 * @param I2Cx I2C Instance
556 * @param Direction This parameter can be one of the following values:
557 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
558 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
559 * @retval Address of data register
560 */
LL_I2C_DMA_GetRegAddr(const I2C_TypeDef * I2Cx,uint32_t Direction)561 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
562 {
563 uint32_t data_reg_addr;
564
565 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
566 {
567 /* return address of TXDR register */
568 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
569 }
570 else
571 {
572 /* return address of RXDR register */
573 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
574 }
575
576 return data_reg_addr;
577 }
578
579 /**
580 * @brief Enable Clock stretching.
581 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
582 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
583 * @param I2Cx I2C Instance.
584 * @retval None
585 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)586 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
587 {
588 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
589 }
590
591 /**
592 * @brief Disable Clock stretching.
593 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
594 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
595 * @param I2Cx I2C Instance.
596 * @retval None
597 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)598 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
599 {
600 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
601 }
602
603 /**
604 * @brief Check if Clock stretching is enabled or disabled.
605 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
606 * @param I2Cx I2C Instance.
607 * @retval State of bit (1 or 0).
608 */
LL_I2C_IsEnabledClockStretching(const I2C_TypeDef * I2Cx)609 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
610 {
611 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
612 }
613
614 #if defined(I2C_CR1_WUPEN)
615 /**
616 * @brief Enable Wakeup from STOP.
617 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
618 * WakeUpFromStop feature is supported by the I2Cx Instance.
619 * @note This bit can only be programmed when Digital Filter is disabled.
620 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
621 * @param I2Cx I2C Instance.
622 * @retval None
623 */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)624 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
625 {
626 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
627 }
628
629 /**
630 * @brief Disable Wakeup from STOP.
631 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
632 * WakeUpFromStop feature is supported by the I2Cx Instance.
633 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
634 * @param I2Cx I2C Instance.
635 * @retval None
636 */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)637 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
638 {
639 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
640 }
641
642 /**
643 * @brief Check if Wakeup from STOP is enabled or disabled.
644 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
645 * WakeUpFromStop feature is supported by the I2Cx Instance.
646 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
647 * @param I2Cx I2C Instance.
648 * @retval State of bit (1 or 0).
649 */
LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef * I2Cx)650 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
651 {
652 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
653 }
654
655 #endif /* I2C_CR1_WUPEN */
656 /**
657 * @brief Enable General Call.
658 * @note When enabled the Address 0x00 is ACKed.
659 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
660 * @param I2Cx I2C Instance.
661 * @retval None
662 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)663 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
664 {
665 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
666 }
667
668 /**
669 * @brief Disable General Call.
670 * @note When disabled the Address 0x00 is NACKed.
671 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
672 * @param I2Cx I2C Instance.
673 * @retval None
674 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)675 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
676 {
677 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
678 }
679
680 /**
681 * @brief Check if General Call is enabled or disabled.
682 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
683 * @param I2Cx I2C Instance.
684 * @retval State of bit (1 or 0).
685 */
LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef * I2Cx)686 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
687 {
688 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
689 }
690
691 /**
692 * @brief Enable I2C Fast Mode Plus (FMP = 1).
693 * @note 20mA I/O drive enable
694 * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
695 * @param I2Cx I2C Instance.
696 * @retval None
697 */
LL_I2C_EnableFastModePlus(I2C_TypeDef * I2Cx)698 __STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
699 {
700 SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
701 }
702
703 /**
704 * @brief Disable I2C Fast Mode Plus (FMP = 0).
705 * @note 20mA I/O drive disable
706 * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
707 * @param I2Cx I2C Instance.
708 * @retval None
709 */
LL_I2C_DisableFastModePlus(I2C_TypeDef * I2Cx)710 __STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
711 {
712 CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
713 }
714
715 /**
716 * @brief Check if the I2C Fast Mode Plus is enabled or disabled.
717 * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
718 * @param I2Cx I2C Instance.
719 * @retval State of bit (1 or 0).
720 */
LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef * I2Cx)721 __STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx)
722 {
723 return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
724 }
725
726 /**
727 * @brief Enable automatic clear of ADDR flag.
728 * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR
729 * @param I2Cx I2C Instance.
730 * @retval None
731 */
LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)732 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
733 {
734 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
735 }
736
737 /**
738 * @brief Disable automatic clear of ADDR flag.
739 * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR
740 * @param I2Cx I2C Instance.
741 * @retval None
742 */
LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)743 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
744 {
745 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
746 }
747
748 /**
749 * @brief Check if the automatic clear of ADDR flag is enabled or disabled.
750 * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR
751 * @param I2Cx I2C Instance.
752 * @retval State of bit (1 or 0).
753 */
LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef * I2Cx)754 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx)
755 {
756 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL);
757 }
758
759 /**
760 * @brief Enable automatic clear of STOP flag.
761 * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP
762 * @param I2Cx I2C Instance.
763 * @retval None
764 */
LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)765 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
766 {
767 SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
768 }
769
770 /**
771 * @brief Disable automatic clear of STOP flag.
772 * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP
773 * @param I2Cx I2C Instance.
774 * @retval None
775 */
LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)776 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
777 {
778 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
779 }
780
781 /**
782 * @brief Check if the automatic clear of STOP flag is enabled or disabled.
783 * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP
784 * @param I2Cx I2C Instance.
785 * @retval State of bit (1 or 0).
786 */
LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef * I2Cx)787 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx)
788 {
789 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL);
790 }
791
792 /**
793 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
794 * @note Changing this bit is not allowed, when the START bit is set.
795 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
796 * @param I2Cx I2C Instance.
797 * @param AddressingMode This parameter can be one of the following values:
798 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
799 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
800 * @retval None
801 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)802 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
803 {
804 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
805 }
806
807 /**
808 * @brief Get the Master addressing mode.
809 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
810 * @param I2Cx I2C Instance.
811 * @retval Returned value can be one of the following values:
812 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
813 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
814 */
LL_I2C_GetMasterAddressingMode(const I2C_TypeDef * I2Cx)815 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
816 {
817 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
818 }
819
820 /**
821 * @brief Set the Own Address1.
822 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
823 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
824 * @param I2Cx I2C Instance.
825 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
826 * @param OwnAddrSize This parameter can be one of the following values:
827 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
828 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
829 * @retval None
830 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)831 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
832 {
833 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
834 }
835
836 /**
837 * @brief Enable acknowledge on Own Address1 match address.
838 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
839 * @param I2Cx I2C Instance.
840 * @retval None
841 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)842 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
843 {
844 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
845 }
846
847 /**
848 * @brief Disable acknowledge on Own Address1 match address.
849 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
850 * @param I2Cx I2C Instance.
851 * @retval None
852 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)853 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
854 {
855 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
856 }
857
858 /**
859 * @brief Check if Own Address1 acknowledge is enabled or disabled.
860 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
861 * @param I2Cx I2C Instance.
862 * @retval State of bit (1 or 0).
863 */
LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef * I2Cx)864 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
865 {
866 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
867 }
868
869 /**
870 * @brief Set the 7bits Own Address2.
871 * @note This action has no effect if own address2 is enabled.
872 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
873 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
874 * @param I2Cx I2C Instance.
875 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
876 * @param OwnAddrMask This parameter can be one of the following values:
877 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
878 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
879 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
880 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
881 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
882 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
883 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
884 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
885 * @retval None
886 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)887 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
888 {
889 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
890 }
891
892 /**
893 * @brief Enable acknowledge on Own Address2 match address.
894 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
895 * @param I2Cx I2C Instance.
896 * @retval None
897 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)898 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
899 {
900 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
901 }
902
903 /**
904 * @brief Disable acknowledge on Own Address2 match address.
905 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
906 * @param I2Cx I2C Instance.
907 * @retval None
908 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)909 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
910 {
911 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
912 }
913
914 /**
915 * @brief Check if Own Address1 acknowledge is enabled or disabled.
916 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
917 * @param I2Cx I2C Instance.
918 * @retval State of bit (1 or 0).
919 */
LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef * I2Cx)920 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
921 {
922 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
923 }
924
925 /**
926 * @brief Configure the SDA setup, hold time and the SCL high, low period.
927 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
928 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
929 * @param I2Cx I2C Instance.
930 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
931 * @note This parameter is computed with the STM32CubeMX Tool.
932 * @retval None
933 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)934 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
935 {
936 WRITE_REG(I2Cx->TIMINGR, Timing);
937 }
938
939 /**
940 * @brief Get the Timing Prescaler setting.
941 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
942 * @param I2Cx I2C Instance.
943 * @retval Value between Min_Data=0x0 and Max_Data=0xF
944 */
LL_I2C_GetTimingPrescaler(const I2C_TypeDef * I2Cx)945 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
946 {
947 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
948 }
949
950 /**
951 * @brief Get the SCL low period setting.
952 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
953 * @param I2Cx I2C Instance.
954 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
955 */
LL_I2C_GetClockLowPeriod(const I2C_TypeDef * I2Cx)956 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
957 {
958 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
959 }
960
961 /**
962 * @brief Get the SCL high period setting.
963 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
964 * @param I2Cx I2C Instance.
965 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
966 */
LL_I2C_GetClockHighPeriod(const I2C_TypeDef * I2Cx)967 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
968 {
969 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
970 }
971
972 /**
973 * @brief Get the SDA hold time.
974 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
975 * @param I2Cx I2C Instance.
976 * @retval Value between Min_Data=0x0 and Max_Data=0xF
977 */
LL_I2C_GetDataHoldTime(const I2C_TypeDef * I2Cx)978 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
979 {
980 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
981 }
982
983 /**
984 * @brief Get the SDA setup time.
985 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
986 * @param I2Cx I2C Instance.
987 * @retval Value between Min_Data=0x0 and Max_Data=0xF
988 */
LL_I2C_GetDataSetupTime(const I2C_TypeDef * I2Cx)989 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
990 {
991 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
992 }
993
994 /**
995 * @}
996 */
997
998 /** @defgroup I2C_LL_EF_IT_Management IT_Management
999 * @{
1000 */
1001
1002 /**
1003 * @brief Enable TXIS interrupt.
1004 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1005 * @param I2Cx I2C Instance.
1006 * @retval None
1007 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1008 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1009 {
1010 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1011 }
1012
1013 /**
1014 * @brief Disable TXIS interrupt.
1015 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1016 * @param I2Cx I2C Instance.
1017 * @retval None
1018 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1019 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1020 {
1021 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1022 }
1023
1024 /**
1025 * @brief Check if the TXIS Interrupt is enabled or disabled.
1026 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1027 * @param I2Cx I2C Instance.
1028 * @retval State of bit (1 or 0).
1029 */
LL_I2C_IsEnabledIT_TX(const I2C_TypeDef * I2Cx)1030 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
1031 {
1032 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1033 }
1034
1035 /**
1036 * @brief Enable RXNE interrupt.
1037 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1038 * @param I2Cx I2C Instance.
1039 * @retval None
1040 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1041 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1042 {
1043 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1044 }
1045
1046 /**
1047 * @brief Disable RXNE interrupt.
1048 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1049 * @param I2Cx I2C Instance.
1050 * @retval None
1051 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1052 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1053 {
1054 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1055 }
1056
1057 /**
1058 * @brief Check if the RXNE Interrupt is enabled or disabled.
1059 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1060 * @param I2Cx I2C Instance.
1061 * @retval State of bit (1 or 0).
1062 */
LL_I2C_IsEnabledIT_RX(const I2C_TypeDef * I2Cx)1063 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
1064 {
1065 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1066 }
1067
1068 /**
1069 * @brief Enable Address match interrupt (slave mode only).
1070 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1071 * @param I2Cx I2C Instance.
1072 * @retval None
1073 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1074 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1075 {
1076 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1077 }
1078
1079 /**
1080 * @brief Disable Address match interrupt (slave mode only).
1081 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1082 * @param I2Cx I2C Instance.
1083 * @retval None
1084 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1085 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1086 {
1087 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1088 }
1089
1090 /**
1091 * @brief Check if Address match interrupt is enabled or disabled.
1092 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1093 * @param I2Cx I2C Instance.
1094 * @retval State of bit (1 or 0).
1095 */
LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef * I2Cx)1096 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
1097 {
1098 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1099 }
1100
1101 /**
1102 * @brief Enable Not acknowledge received interrupt.
1103 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1104 * @param I2Cx I2C Instance.
1105 * @retval None
1106 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1107 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1108 {
1109 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1110 }
1111
1112 /**
1113 * @brief Disable Not acknowledge received interrupt.
1114 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1115 * @param I2Cx I2C Instance.
1116 * @retval None
1117 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1118 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1119 {
1120 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1121 }
1122
1123 /**
1124 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1125 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1126 * @param I2Cx I2C Instance.
1127 * @retval State of bit (1 or 0).
1128 */
LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef * I2Cx)1129 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
1130 {
1131 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1132 }
1133
1134 /**
1135 * @brief Enable STOP detection interrupt.
1136 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1137 * @param I2Cx I2C Instance.
1138 * @retval None
1139 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1140 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1141 {
1142 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1143 }
1144
1145 /**
1146 * @brief Disable STOP detection interrupt.
1147 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1148 * @param I2Cx I2C Instance.
1149 * @retval None
1150 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1151 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1152 {
1153 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1154 }
1155
1156 /**
1157 * @brief Check if STOP detection interrupt is enabled or disabled.
1158 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1159 * @param I2Cx I2C Instance.
1160 * @retval State of bit (1 or 0).
1161 */
LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef * I2Cx)1162 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
1163 {
1164 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1165 }
1166
1167 /**
1168 * @brief Enable Transfer Complete interrupt.
1169 * @note Any of these events will generate interrupt :
1170 * Transfer Complete (TC)
1171 * Transfer Complete Reload (TCR)
1172 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1173 * @param I2Cx I2C Instance.
1174 * @retval None
1175 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1176 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1177 {
1178 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1179 }
1180
1181 /**
1182 * @brief Disable Transfer Complete interrupt.
1183 * @note Any of these events will generate interrupt :
1184 * Transfer Complete (TC)
1185 * Transfer Complete Reload (TCR)
1186 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1187 * @param I2Cx I2C Instance.
1188 * @retval None
1189 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1190 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1191 {
1192 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1193 }
1194
1195 /**
1196 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1197 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1198 * @param I2Cx I2C Instance.
1199 * @retval State of bit (1 or 0).
1200 */
LL_I2C_IsEnabledIT_TC(const I2C_TypeDef * I2Cx)1201 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
1202 {
1203 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1204 }
1205
1206 /**
1207 * @brief Enable Error interrupts.
1208 * @note Any of these errors will generate interrupt :
1209 * Arbitration Loss (ARLO)
1210 * Bus Error detection (BERR)
1211 * Overrun/Underrun (OVR)
1212 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1213 * @param I2Cx I2C Instance.
1214 * @retval None
1215 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1216 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1217 {
1218 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1219 }
1220
1221 /**
1222 * @brief Disable Error interrupts.
1223 * @note Any of these errors will generate interrupt :
1224 * Arbitration Loss (ARLO)
1225 * Bus Error detection (BERR)
1226 * Overrun/Underrun (OVR)
1227 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1228 * @param I2Cx I2C Instance.
1229 * @retval None
1230 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1231 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1232 {
1233 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1234 }
1235
1236 /**
1237 * @brief Check if Error interrupts are enabled or disabled.
1238 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1239 * @param I2Cx I2C Instance.
1240 * @retval State of bit (1 or 0).
1241 */
LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef * I2Cx)1242 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
1243 {
1244 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1245 }
1246
1247 /**
1248 * @}
1249 */
1250
1251 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1252 * @{
1253 */
1254
1255 /**
1256 * @brief Indicate the status of Transmit data register empty flag.
1257 * @note RESET: When next data is written in Transmit data register.
1258 * SET: When Transmit data register is empty.
1259 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1260 * @param I2Cx I2C Instance.
1261 * @retval State of bit (1 or 0).
1262 */
LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef * I2Cx)1263 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
1264 {
1265 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1266 }
1267
1268 /**
1269 * @brief Indicate the status of Transmit interrupt flag.
1270 * @note RESET: When next data is written in Transmit data register.
1271 * SET: When Transmit data register is empty.
1272 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1273 * @param I2Cx I2C Instance.
1274 * @retval State of bit (1 or 0).
1275 */
LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef * I2Cx)1276 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
1277 {
1278 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1279 }
1280
1281 /**
1282 * @brief Indicate the status of Receive data register not empty flag.
1283 * @note RESET: When Receive data register is read.
1284 * SET: When the received data is copied in Receive data register.
1285 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1286 * @param I2Cx I2C Instance.
1287 * @retval State of bit (1 or 0).
1288 */
LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef * I2Cx)1289 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
1290 {
1291 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1292 }
1293
1294 /**
1295 * @brief Indicate the status of Address matched flag (slave mode).
1296 * @note RESET: Clear default value.
1297 * SET: When the received slave address matched with one of the enabled slave address.
1298 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1299 * @param I2Cx I2C Instance.
1300 * @retval State of bit (1 or 0).
1301 */
LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef * I2Cx)1302 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
1303 {
1304 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Indicate the status of Not Acknowledge received flag.
1309 * @note RESET: Clear default value.
1310 * SET: When a NACK is received after a byte transmission.
1311 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1312 * @param I2Cx I2C Instance.
1313 * @retval State of bit (1 or 0).
1314 */
LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef * I2Cx)1315 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
1316 {
1317 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1318 }
1319
1320 /**
1321 * @brief Indicate the status of Stop detection flag.
1322 * @note RESET: Clear default value.
1323 * SET: When a Stop condition is detected.
1324 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1325 * @param I2Cx I2C Instance.
1326 * @retval State of bit (1 or 0).
1327 */
LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef * I2Cx)1328 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
1329 {
1330 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1331 }
1332
1333 /**
1334 * @brief Indicate the status of Transfer complete flag (master mode).
1335 * @note RESET: Clear default value.
1336 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1337 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1338 * @param I2Cx I2C Instance.
1339 * @retval State of bit (1 or 0).
1340 */
LL_I2C_IsActiveFlag_TC(const I2C_TypeDef * I2Cx)1341 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
1342 {
1343 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1344 }
1345
1346 /**
1347 * @brief Indicate the status of Transfer complete flag (master mode).
1348 * @note RESET: Clear default value.
1349 * SET: When RELOAD=1 and NBYTES date have been transferred.
1350 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1351 * @param I2Cx I2C Instance.
1352 * @retval State of bit (1 or 0).
1353 */
LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef * I2Cx)1354 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
1355 {
1356 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1357 }
1358
1359 /**
1360 * @brief Indicate the status of Bus error flag.
1361 * @note RESET: Clear default value.
1362 * SET: When a misplaced Start or Stop condition is detected.
1363 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1364 * @param I2Cx I2C Instance.
1365 * @retval State of bit (1 or 0).
1366 */
LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef * I2Cx)1367 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
1368 {
1369 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1370 }
1371
1372 /**
1373 * @brief Indicate the status of Arbitration lost flag.
1374 * @note RESET: Clear default value.
1375 * SET: When arbitration lost.
1376 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1377 * @param I2Cx I2C Instance.
1378 * @retval State of bit (1 or 0).
1379 */
LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef * I2Cx)1380 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
1381 {
1382 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1383 }
1384
1385 /**
1386 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1387 * @note RESET: Clear default value.
1388 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1389 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1390 * @param I2Cx I2C Instance.
1391 * @retval State of bit (1 or 0).
1392 */
LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef * I2Cx)1393 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
1394 {
1395 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1396 }
1397
1398 /**
1399 * @brief Indicate the status of Bus Busy flag.
1400 * @note RESET: Clear default value.
1401 * SET: When a Start condition is detected.
1402 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1403 * @param I2Cx I2C Instance.
1404 * @retval State of bit (1 or 0).
1405 */
LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef * I2Cx)1406 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
1407 {
1408 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1409 }
1410
1411 /**
1412 * @brief Clear Address Matched flag.
1413 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1414 * @param I2Cx I2C Instance.
1415 * @retval None
1416 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1417 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1418 {
1419 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1420 }
1421
1422 /**
1423 * @brief Clear Not Acknowledge flag.
1424 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1425 * @param I2Cx I2C Instance.
1426 * @retval None
1427 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1428 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1429 {
1430 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1431 }
1432
1433 /**
1434 * @brief Clear Stop detection flag.
1435 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1436 * @param I2Cx I2C Instance.
1437 * @retval None
1438 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1439 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1440 {
1441 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1442 }
1443
1444 /**
1445 * @brief Clear Transmit data register empty flag (TXE).
1446 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1447 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1448 * @param I2Cx I2C Instance.
1449 * @retval None
1450 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1451 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1452 {
1453 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1454 }
1455
1456 /**
1457 * @brief Clear Bus error flag.
1458 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1459 * @param I2Cx I2C Instance.
1460 * @retval None
1461 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1462 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1463 {
1464 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1465 }
1466
1467 /**
1468 * @brief Clear Arbitration lost flag.
1469 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1470 * @param I2Cx I2C Instance.
1471 * @retval None
1472 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1473 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1474 {
1475 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1476 }
1477
1478 /**
1479 * @brief Clear Overrun/Underrun flag.
1480 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1481 * @param I2Cx I2C Instance.
1482 * @retval None
1483 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1484 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1485 {
1486 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1487 }
1488
1489 /**
1490 * @}
1491 */
1492
1493 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1494 * @{
1495 */
1496
1497 /**
1498 * @brief Enable automatic STOP condition generation (master mode).
1499 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1500 * This bit has no effect in slave mode or when RELOAD bit is set.
1501 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1502 * @param I2Cx I2C Instance.
1503 * @retval None
1504 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)1505 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1506 {
1507 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1508 }
1509
1510 /**
1511 * @brief Disable automatic STOP condition generation (master mode).
1512 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1513 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1514 * @param I2Cx I2C Instance.
1515 * @retval None
1516 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)1517 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1518 {
1519 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1520 }
1521
1522 /**
1523 * @brief Check if automatic STOP condition is enabled or disabled.
1524 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1525 * @param I2Cx I2C Instance.
1526 * @retval State of bit (1 or 0).
1527 */
LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef * I2Cx)1528 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
1529 {
1530 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1531 }
1532
1533 /**
1534 * @brief Enable reload mode (master mode).
1535 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1536 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1537 * @param I2Cx I2C Instance.
1538 * @retval None
1539 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)1540 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1541 {
1542 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1543 }
1544
1545 /**
1546 * @brief Disable reload mode (master mode).
1547 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1548 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1549 * @param I2Cx I2C Instance.
1550 * @retval None
1551 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)1552 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1553 {
1554 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1555 }
1556
1557 /**
1558 * @brief Check if reload mode is enabled or disabled.
1559 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1560 * @param I2Cx I2C Instance.
1561 * @retval State of bit (1 or 0).
1562 */
LL_I2C_IsEnabledReloadMode(const I2C_TypeDef * I2Cx)1563 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
1564 {
1565 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1566 }
1567
1568 /**
1569 * @brief Configure the number of bytes for transfer.
1570 * @note Changing these bits when START bit is set is not allowed.
1571 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1572 * @param I2Cx I2C Instance.
1573 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1574 * @retval None
1575 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)1576 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1577 {
1578 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1579 }
1580
1581 /**
1582 * @brief Get the number of bytes configured for transfer.
1583 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1584 * @param I2Cx I2C Instance.
1585 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1586 */
LL_I2C_GetTransferSize(const I2C_TypeDef * I2Cx)1587 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
1588 {
1589 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1590 }
1591
1592 /**
1593 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
1594 or next received byte.
1595 * @note Usage in Slave mode only.
1596 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1597 * @param I2Cx I2C Instance.
1598 * @param TypeAcknowledge This parameter can be one of the following values:
1599 * @arg @ref LL_I2C_ACK
1600 * @arg @ref LL_I2C_NACK
1601 * @retval None
1602 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1603 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1604 {
1605 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1606 }
1607
1608 /**
1609 * @brief Generate a START or RESTART condition
1610 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1611 * This action has no effect when RELOAD is set.
1612 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1613 * @param I2Cx I2C Instance.
1614 * @retval None
1615 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1616 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1617 {
1618 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1619 }
1620
1621 /**
1622 * @brief Generate a STOP condition after the current byte transfer (master mode).
1623 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1624 * @param I2Cx I2C Instance.
1625 * @retval None
1626 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)1627 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1628 {
1629 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
1630 }
1631
1632 /**
1633 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1634 * @note The master sends the complete 10bit slave address read sequence :
1635 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
1636 in Read direction.
1637 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
1638 * @param I2Cx I2C Instance.
1639 * @retval None
1640 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)1641 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
1642 {
1643 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1644 }
1645
1646 /**
1647 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1648 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1649 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
1650 * @param I2Cx I2C Instance.
1651 * @retval None
1652 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)1653 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
1654 {
1655 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1656 }
1657
1658 /**
1659 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1660 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
1661 * @param I2Cx I2C Instance.
1662 * @retval State of bit (1 or 0).
1663 */
LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef * I2Cx)1664 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
1665 {
1666 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
1667 }
1668
1669 /**
1670 * @brief Configure the transfer direction (master mode).
1671 * @note Changing these bits when START bit is set is not allowed.
1672 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
1673 * @param I2Cx I2C Instance.
1674 * @param TransferRequest This parameter can be one of the following values:
1675 * @arg @ref LL_I2C_REQUEST_WRITE
1676 * @arg @ref LL_I2C_REQUEST_READ
1677 * @retval None
1678 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)1679 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
1680 {
1681 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
1682 }
1683
1684 /**
1685 * @brief Get the transfer direction requested (master mode).
1686 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
1687 * @param I2Cx I2C Instance.
1688 * @retval Returned value can be one of the following values:
1689 * @arg @ref LL_I2C_REQUEST_WRITE
1690 * @arg @ref LL_I2C_REQUEST_READ
1691 */
LL_I2C_GetTransferRequest(const I2C_TypeDef * I2Cx)1692 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
1693 {
1694 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
1695 }
1696
1697 /**
1698 * @brief Configure the slave address for transfer (master mode).
1699 * @note Changing these bits when START bit is set is not allowed.
1700 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
1701 * @param I2Cx I2C Instance.
1702 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
1703 * @retval None
1704 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)1705 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
1706 {
1707 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
1708 }
1709
1710 /**
1711 * @brief Get the slave address programmed for transfer.
1712 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
1713 * @param I2Cx I2C Instance.
1714 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
1715 */
LL_I2C_GetSlaveAddr(const I2C_TypeDef * I2Cx)1716 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
1717 {
1718 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
1719 }
1720
1721 /**
1722 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
1723 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
1724 * CR2 ADD10 LL_I2C_HandleTransfer\n
1725 * CR2 RD_WRN LL_I2C_HandleTransfer\n
1726 * CR2 START LL_I2C_HandleTransfer\n
1727 * CR2 STOP LL_I2C_HandleTransfer\n
1728 * CR2 RELOAD LL_I2C_HandleTransfer\n
1729 * CR2 NBYTES LL_I2C_HandleTransfer\n
1730 * CR2 AUTOEND LL_I2C_HandleTransfer\n
1731 * CR2 HEAD10R LL_I2C_HandleTransfer
1732 * @param I2Cx I2C Instance.
1733 * @param SlaveAddr Specifies the slave address to be programmed.
1734 * @param SlaveAddrSize This parameter can be one of the following values:
1735 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
1736 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
1737 * @param TransferSize Specifies the number of bytes to be programmed.
1738 * This parameter must be a value between Min_Data=0 and Max_Data=255.
1739 * @param EndMode This parameter can be one of the following values:
1740 * @arg @ref LL_I2C_MODE_RELOAD
1741 * @arg @ref LL_I2C_MODE_AUTOEND
1742 * @arg @ref LL_I2C_MODE_SOFTEND
1743 * @param Request This parameter can be one of the following values:
1744 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
1745 * @arg @ref LL_I2C_GENERATE_STOP
1746 * @arg @ref LL_I2C_GENERATE_START_READ
1747 * @arg @ref LL_I2C_GENERATE_START_WRITE
1748 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
1749 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
1750 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
1751 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
1752 * @retval None
1753 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)1754 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
1755 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
1756 {
1757 /* Declaration of tmp to prevent undefined behavior of volatile usage */
1758 uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
1759 ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
1760 (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
1761 (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
1762
1763 /* update CR2 register */
1764 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
1765 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
1766 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
1767 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
1768 tmp);
1769 }
1770
1771 /**
1772 * @brief Indicate the value of transfer direction (slave mode).
1773 * @note RESET: Write transfer, Slave enters in receiver mode.
1774 * SET: Read transfer, Slave enters in transmitter mode.
1775 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
1776 * @param I2Cx I2C Instance.
1777 * @retval Returned value can be one of the following values:
1778 * @arg @ref LL_I2C_DIRECTION_WRITE
1779 * @arg @ref LL_I2C_DIRECTION_READ
1780 */
LL_I2C_GetTransferDirection(const I2C_TypeDef * I2Cx)1781 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
1782 {
1783 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
1784 }
1785
1786 /**
1787 * @brief Return the slave matched address.
1788 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
1789 * @param I2Cx I2C Instance.
1790 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
1791 */
LL_I2C_GetAddressMatchCode(const I2C_TypeDef * I2Cx)1792 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
1793 {
1794 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
1795 }
1796
1797 /**
1798 * @brief Read Receive Data register.
1799 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
1800 * @param I2Cx I2C Instance.
1801 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1802 */
LL_I2C_ReceiveData8(const I2C_TypeDef * I2Cx)1803 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
1804 {
1805 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
1806 }
1807
1808 /**
1809 * @brief Write in Transmit Data Register .
1810 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
1811 * @param I2Cx I2C Instance.
1812 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1813 * @retval None
1814 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)1815 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
1816 {
1817 WRITE_REG(I2Cx->TXDR, Data);
1818 }
1819
1820 /**
1821 * @}
1822 */
1823
1824 #if defined(USE_FULL_LL_DRIVER)
1825 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
1826 * @{
1827 */
1828
1829 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
1830 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
1831 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
1832
1833
1834 /**
1835 * @}
1836 */
1837 #endif /* USE_FULL_LL_DRIVER */
1838
1839 /**
1840 * @}
1841 */
1842
1843 /**
1844 * @}
1845 */
1846
1847 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
1848
1849 /**
1850 * @}
1851 */
1852
1853 #ifdef __cplusplus
1854 }
1855 #endif
1856
1857 #endif /* STM32U0xx_LL_I2C_H */
1858
