1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_dmamux.h
4 * @author GPM Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_DMAMUX_H
21 #define STM32U0xx_LL_DMAMUX_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMAMUX1)
35
36 /** @defgroup DMAMUX_LL DMAMUX
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
44 * @{
45 */
46 /* Define used to get DMAMUX CCR register size */
47 #define DMAMUX_CCR_SIZE 0x00000004UL
48
49 /* Define used to get DMAMUX RGCR register size */
50 #define DMAMUX_RGCR_SIZE 0x00000004UL
51 /**
52 * @}
53 */
54
55 /* Private macros ------------------------------------------------------------*/
56 /* Exported types ------------------------------------------------------------*/
57 /* Exported constants --------------------------------------------------------*/
58 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
59 * @{
60 */
61 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
62 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
63 * @{
64 */
65 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
66 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
67 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
68 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
69 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
70 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
71 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
72 #if defined(DMA2)
73 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
74 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
75 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
76 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
77 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
78 #endif /* DMA2 */
79 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
80 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
81 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
82 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
83 /**
84 * @}
85 */
86
87 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
88 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
89 * @{
90 */
91 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
92 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
93 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
94 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
95 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
96 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
97 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
98 #if defined(DMA2)
99 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
100 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
101 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
102 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
103 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
104 #endif /* DMA2 */
105 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
106 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
107 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
108 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
109 /**
110 * @}
111 */
112
113 /** @defgroup DMAMUX_LL_EC_IT IT Defines
114 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
115 * @{
116 */
117 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
118 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
119 /**
120 * @}
121 */
122
123 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
124 * @{
125 */
126 #define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */
127 #define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */
128 #define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */
129 #define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */
130 #define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */
131 #define LL_DMAMUX_REQ_ADC 0x00000005U /*!< DMAMUX ADC request */
132 #if defined(AES)
133 #define LL_DMAMUX_REQ_AES_IN 0x00000006U /*!< DMAMUX AES_IN request */
134 #define LL_DMAMUX_REQ_AES_OUT 0x00000007U /*!< DMAMUX AES_OUT request */
135 #endif /* AES */
136 #define LL_DMAMUX_REQ_DAC_CH1 0x00000008U /*!< DMAMUX DAC_CH1 request */
137 #define LL_DMAMUX_REQ_I2C1_RX 0x00000009U /*!< DMAMUX I2C1 RX request */
138 #define LL_DMAMUX_REQ_I2C1_TX 0x0000000AU /*!< DMAMUX I2C1 TX request */
139 #define LL_DMAMUX_REQ_I2C2_RX 0x0000000BU /*!< DMAMUX I2C2 RX request */
140 #define LL_DMAMUX_REQ_I2C2_TX 0x0000000CU /*!< DMAMUX I2C2 TX request */
141 #define LL_DMAMUX_REQ_I2C3_RX 0x0000000DU /*!< DMAMUX I2C3 RX request */
142 #define LL_DMAMUX_REQ_I2C3_TX 0x0000000EU /*!< DMAMUX I2C3 TX request */
143 #if defined(I2C4)
144 #define LL_DMAMUX_REQ_I2C4_RX 0x0000000FU /*!< DMAMUX I2C4 RX request */
145 #define LL_DMAMUX_REQ_I2C4_TX 0x00000010U /*!< DMAMUX I2C4 TX request */
146 #endif /* I2C4 */
147 #define LL_DMAMUX_REQ_LPTIM1_IC1 0x00000011U /*!< DMAMUX LPTIM1 IC1 request */
148 #define LL_DMAMUX_REQ_LPTIM1_IC2 0x00000012U /*!< DMAMUX LPTIM1 IC2 request */
149 #define LL_DMAMUX_REQ_LPTIM1_IC3 0x00000013U /*!< DMAMUX LPTIM1 IC3 request */
150 #define LL_DMAMUX_REQ_LPTIM1_IC4 0x00000014U /*!< DMAMUX LPTIM1 IC4 request */
151 #define LL_DMAMUX_REQ_LPTIM1_UE 0x00000015U /*!< DMAMUX LPTIM1 UE request */
152 #define LL_DMAMUX_REQ_LPTIM2_IC1 0x00000016U /*!< DMAMUX LPTIM2 IC1 request */
153 #define LL_DMAMUX_REQ_LPTIM2_IC2 0x00000017U /*!< DMAMUX LPTIM2 IC2 request */
154 #define LL_DMAMUX_REQ_LPTIM2_UE 0x00000018U /*!< DMAMUX LPTIM2 UE request */
155 #if defined(LPTIM3)
156 #define LL_DMAMUX_REQ_LPTIM3_IC1 0x00000019U /*!< DMAMUX LPTIM3 IC1 request */
157 #define LL_DMAMUX_REQ_LPTIM3_IC2 0x0000001AU /*!< DMAMUX LPTIM3 IC2 request */
158 #define LL_DMAMUX_REQ_LPTIM3_IC3 0x0000001BU /*!< DMAMUX LPTIM3 IC3 request */
159 #define LL_DMAMUX_REQ_LPTIM3_IC4 0x0000001CU /*!< DMAMUX LPTIM3 IC4 request */
160 #define LL_DMAMUX_REQ_LPTIM3_UE 0x0000001DU /*!< DMAMUX LPTIM3 UE request */
161 #endif /* LPTIM3 */
162 #define LL_DMAMUX_REQ_LPUART1_RX 0x0000001EU /*!< DMAMUX LPUART1 RX request */
163 #define LL_DMAMUX_REQ_LPUART1_TX 0x0000001FU /*!< DMAMUX LPUART1 TX request */
164 #define LL_DMAMUX_REQ_LPUART2_RX 0x00000020U /*!< DMAMUX LPUART2 RX request */
165 #define LL_DMAMUX_REQ_LPUART2_TX 0x00000021U /*!< DMAMUX LPUART2 TX request */
166 #if defined(LPUART3)
167 #define LL_DMAMUX_REQ_LPUART3_RX 0x00000022U /*!< DMAMUX LPUART3 RX request */
168 #define LL_DMAMUX_REQ_LPUART3_TX 0x00000023U /*!< DMAMUX LPUART3 TX request */
169 #endif /* LPUART */
170 #define LL_DMAMUX_REQ_SPI1_RX 0x00000024U /*!< DMAMUX SPI1 RX request */
171 #define LL_DMAMUX_REQ_SPI1_TX 0x00000025U /*!< DMAMUX SPI1 TX request */
172 #define LL_DMAMUX_REQ_SPI2_RX 0x00000026U /*!< DMAMUX SPI2 RX request */
173 #define LL_DMAMUX_REQ_SPI2_TX 0x00000027U /*!< DMAMUX SPI2 TX request */
174 #if defined(SPI3)
175 #define LL_DMAMUX_REQ_SPI3_RX 0x00000028U /*!< DMAMUX SPI3 RX request */
176 #define LL_DMAMUX_REQ_SPI3_TX 0x00000029U /*!< DMAMUX SPI3 TX request */
177 #endif /* SPI3 */
178 #define LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU /*!< DMAMUX TIM1 CH1 request */
179 #define LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU /*!< DMAMUX TIM1 CH2 request */
180 #define LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU /*!< DMAMUX TIM1 CH3 request */
181 #define LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU /*!< DMAMUX TIM1 CH4 request */
182 #define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x0000002EU /*!< DMAMUX TIM1 TRIG COM request */
183 #define LL_DMAMUX_REQ_TIM1_UP 0x0000002FU /*!< DMAMUX TIM1 UP request */
184 #define LL_DMAMUX_REQ_TIM2_CH1 0x00000030U /*!< DMAMUX TIM2 CH1 request */
185 #define LL_DMAMUX_REQ_TIM2_CH2 0x00000031U /*!< DMAMUX TIM2 CH2 request */
186 #define LL_DMAMUX_REQ_TIM2_CH3 0x00000032U /*!< DMAMUX TIM2 CH3 request */
187 #define LL_DMAMUX_REQ_TIM2_CH4 0x00000033U /*!< DMAMUX TIM2 CH4 request */
188 #define LL_DMAMUX_REQ_TIM2_TRIG 0x00000034U /*!< DMAMUX TIM2 TRIG request */
189 #define LL_DMAMUX_REQ_TIM2_UP 0x00000035U /*!< DMAMUX TIM2 UP request */
190 #define LL_DMAMUX_REQ_TIM3_CH1 0x00000036U /*!< DMAMUX TIM3 CH1 request */
191 #define LL_DMAMUX_REQ_TIM3_CH2 0x00000037U /*!< DMAMUX TIM3 CH2 request */
192 #define LL_DMAMUX_REQ_TIM3_CH3 0x00000038U /*!< DMAMUX TIM3 CH3 request */
193 #define LL_DMAMUX_REQ_TIM3_CH4 0x00000039U /*!< DMAMUX TIM3 CH4 request */
194 #define LL_DMAMUX_REQ_TIM3_TRIG 0x0000003AU /*!< DMAMUX TIM3 TRIG request */
195 #define LL_DMAMUX_REQ_TIM3_UP 0x0000003BU /*!< DMAMUX TIM3 UP request */
196 #define LL_DMAMUX_REQ_TIM6_UP 0x0000003CU /*!< DMAMUX TIM6 UP request */
197 #define LL_DMAMUX_REQ_TIM7_UP 0x0000003DU /*!< DMAMUX TIM7 UP request */
198 #define LL_DMAMUX_REQ_TIM15_CH1 0x0000003EU /*!< DMAMUX TIM15 CH1 request */
199 #define LL_DMAMUX_REQ_TIM15_CH2 0x0000003FU /*!< DMAMUX TIM15 CH2 request */
200 #define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x00000040U /*!< DMAMUX TIM15 TRIG COMrequest */
201 #define LL_DMAMUX_REQ_TIM15_UP 0x00000041U /*!< DMAMUX TIM15 UP request */
202 #define LL_DMAMUX_REQ_TIM16_CH1 0x00000042U /*!< DMAMUX TIM16 CH1 request */
203 #define LL_DMAMUX_REQ_TIM16_COM 0x00000043U /*!< DMAMUX TIM16 COM request */
204 #define LL_DMAMUX_REQ_TIM16_UP 0x00000044U /*!< DMAMUX TIM16 UP request */
205 #define LL_DMAMUX_REQ_USART1_RX 0x00000045U /*!< DMAMUX USART1 RX request */
206 #define LL_DMAMUX_REQ_USART1_TX 0x00000046U /*!< DMAMUX USART1 TX request */
207 #define LL_DMAMUX_REQ_USART2_RX 0x00000047U /*!< DMAMUX USART2 RX request */
208 #define LL_DMAMUX_REQ_USART2_TX 0x00000048U /*!< DMAMUX USART2 TX request */
209 #define LL_DMAMUX_REQ_USART3_RX 0x00000049U /*!< DMAMUX USART3 RX request */
210 #define LL_DMAMUX_REQ_USART3_TX 0x0000004AU /*!< DMAMUX USART3 TX request */
211 #define LL_DMAMUX_REQ_USART4_RX 0x0000004BU /*!< DMAMUX USART4 RX request */
212 #define LL_DMAMUX_REQ_USART4_TX 0x0000004CU /*!< DMAMUX USART4 TX request */
213
214 #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX
215 /**
216 * @}
217 */
218
219 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
220 * @{
221 */
222 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
223 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
224 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
225 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
226 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
227 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
228 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
229 #if defined(DMA2)
230 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */
231 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */
232 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */
233 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
234 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
235 #endif /* DMA2 */
236 /**
237 * @}
238 */
239
240 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
241 * @{
242 */
243 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
244 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
245 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
246 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
247 /**
248 * @}
249 */
250
251 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
252 * @{
253 */
254 #define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */
255 #define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
256 #define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
257 #define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
258 #define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
259 #define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
260 #define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
261 #define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
262 #define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
263 #define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
264 #define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
265 #define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
266 #define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
267 #define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 3 */
268 #define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line1 4 */
269 #define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | \
270 DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */
271 #define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */
272 #define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
273 #define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
274 #define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
275 #if defined(LPTIM1)
276 #define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
277 #endif /* LPTIM1 */
278 #if defined(LPTIM2)
279 #define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
280 #endif /* LPTIM2 */
281 #if defined(LPTIM3)
282 #define LL_DMAMUX_SYNC_LPTIM3_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from LPTIM3 Output */
283 #endif /* LPTIM3 */
284 /**
285 * @}
286 */
287
288 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
289 * @{
290 */
291 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
292 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
293 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
294 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
295 /**
296 * @}
297 */
298
299 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
300 * @{
301 */
302 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
303 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
304 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
305 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
306 /**
307 * @}
308 */
309
310 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
311 * @{
312 */
313 #define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */
314 #define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
315 #define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
316 #define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
317 #define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
318 #define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
319 #define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
320 #define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
321 #define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
322 #define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
323 #define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
324 #define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
325 #define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
326 #define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
327 #define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
328 #define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | \
329 DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
330 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */
331 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
332 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
333 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
334 #if defined(LPTIM1)
335 #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
336 #endif /* LPTIM1 */
337 #if defined(LPTIM2)
338 #define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
339 #endif /* LPTIM2 */
340 #if defined(LPTIM3)
341 #define LL_DMAMUX_REQ_GEN_LPTIM3_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from LPTIM3 Output */
342 #endif /* LPTIM3 */
343 /**
344 * @}
345 */
346
347 /**
348 * @}
349 */
350
351 /* Exported macro ------------------------------------------------------------*/
352 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
353 * @{
354 */
355
356 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
357 * @{
358 */
359 /**
360 * @brief Write a value in DMAMUX register
361 * @param __INSTANCE__ DMAMUX Instance
362 * @param __REG__ Register to be written
363 * @param __VALUE__ Value to be written in the register
364 * @retval None
365 */
366 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
367
368 /**
369 * @brief Read a value in DMAMUX register
370 * @param __INSTANCE__ DMAMUX Instance
371 * @param __REG__ Register to be read
372 * @retval Register value
373 */
374 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
375 /**
376 * @}
377 */
378
379 /**
380 * @}
381 */
382
383 /* Exported functions --------------------------------------------------------*/
384 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
385 * @{
386 */
387
388 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
389 * @{
390 */
391 /**
392 * @brief Set DMAMUX request ID for DMAMUX Channel x.
393 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
394 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
395 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
396 * @param DMAMUXx DMAMUXx Instance
397 * @param Channel This parameter can be one of the following values:
398 * @arg @ref LL_DMAMUX_CHANNEL_0
399 * @arg @ref LL_DMAMUX_CHANNEL_1
400 * @arg @ref LL_DMAMUX_CHANNEL_2
401 * @arg @ref LL_DMAMUX_CHANNEL_3
402 * @arg @ref LL_DMAMUX_CHANNEL_4
403 * @arg @ref LL_DMAMUX_CHANNEL_5
404 * @arg @ref LL_DMAMUX_CHANNEL_6
405 *
406 * @arg All the next values are only available on chip which support DMA2:
407 * @arg @ref LL_DMAMUX_CHANNEL_7
408 * @arg @ref LL_DMAMUX_CHANNEL_8
409 * @arg @ref LL_DMAMUX_CHANNEL_9
410 * @arg @ref LL_DMAMUX_CHANNEL_10
411 * @arg @ref LL_DMAMUX_CHANNEL_11
412 * @param Request This parameter can be one of the following values:
413 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
414 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
415 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
416 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
417 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
418 * @arg @ref LL_DMAMUX_REQ_ADC
419 * @arg @ref LL_DMAMUX_REQ_AES_IN
420 * @arg @ref LL_DMAMUX_REQ_AES_OUT
421 * @arg @ref LL_DMAMUX_REQ_DAC_CH1
422 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
423 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
424 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
425 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
426 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
427 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
428 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
429 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
430 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC1
431 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC2
432 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC3
433 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC4
434 * @arg @ref LL_DMAMUX_REQ_LPTIM1_UE
435 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC1
436 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC2
437 * @arg @ref LL_DMAMUX_REQ_LPTIM2_UE
438 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC1
439 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC2
440 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC3
441 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC4
442 * @arg @ref LL_DMAMUX_REQ_LPTIM3_UE
443 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
444 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
445 * @arg @ref LL_DMAMUX_REQ_LPUART2_RX
446 * @arg @ref LL_DMAMUX_REQ_LPUART2_TX
447 * @arg @ref LL_DMAMUX_REQ_LPUART3_RX
448 * @arg @ref LL_DMAMUX_REQ_LPUART3_TX
449 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
450 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
451 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
452 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
453 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
454 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
455 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
456 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
457 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
458 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
459 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
460 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
461 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
462 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
463 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
464 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
465 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
466 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
467 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
468 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
469 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
470 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
471 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
472 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
473 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
474 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
475 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
476 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
477 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
478 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
479 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
480 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
481 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
482 * @arg @ref LL_DMAMUX_REQ_USART1_RX
483 * @arg @ref LL_DMAMUX_REQ_USART1_TX
484 * @arg @ref LL_DMAMUX_REQ_USART2_RX
485 * @arg @ref LL_DMAMUX_REQ_USART2_TX
486 * @arg @ref LL_DMAMUX_REQ_USART3_RX
487 * @arg @ref LL_DMAMUX_REQ_USART3_TX
488 * @arg @ref LL_DMAMUX_REQ_USART4_RX
489 * @arg @ref LL_DMAMUX_REQ_USART4_TX
490 * @retval None
491 */
LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Request)492 __STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
493 {
494 (void)(DMAMUXx);
495 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
496 }
497
498 /**
499 * @brief Get DMAMUX request ID for DMAMUX Channel x.
500 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
501 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
502 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
503 * @param DMAMUXx DMAMUXx Instance
504 * @param Channel This parameter can be one of the following values:
505 * @arg @ref LL_DMAMUX_CHANNEL_0
506 * @arg @ref LL_DMAMUX_CHANNEL_1
507 * @arg @ref LL_DMAMUX_CHANNEL_2
508 * @arg @ref LL_DMAMUX_CHANNEL_3
509 * @arg @ref LL_DMAMUX_CHANNEL_4
510 * @arg @ref LL_DMAMUX_CHANNEL_5
511 * @arg @ref LL_DMAMUX_CHANNEL_6
512 *
513 * @arg All the next values are only available on chip which support DMA2:
514 * @arg @ref LL_DMAMUX_CHANNEL_7
515 * @arg @ref LL_DMAMUX_CHANNEL_8
516 * @arg @ref LL_DMAMUX_CHANNEL_9
517 * @arg @ref LL_DMAMUX_CHANNEL_10
518 * @arg @ref LL_DMAMUX_CHANNEL_11
519 * @retval Returned value can be one of the following values:
520 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
521 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
522 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
523 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
524 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
525 * @arg @ref LL_DMAMUX_REQ_ADC
526 * @arg @ref LL_DMAMUX_REQ_AES_IN
527 * @arg @ref LL_DMAMUX_REQ_AES_OUT
528 * @arg @ref LL_DMAMUX_REQ_DAC_CH1
529 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
530 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
531 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
532 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
533 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
534 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
535 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
536 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
537 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC1
538 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC2
539 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC3
540 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC4
541 * @arg @ref LL_DMAMUX_REQ_LPTIM1_UE
542 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC1
543 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC2
544 * @arg @ref LL_DMAMUX_REQ_LPTIM2_UE
545 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC1
546 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC2
547 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC3
548 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC4
549 * @arg @ref LL_DMAMUX_REQ_LPTIM3_UE
550 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
551 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
552 * @arg @ref LL_DMAMUX_REQ_LPUART2_RX
553 * @arg @ref LL_DMAMUX_REQ_LPUART2_TX
554 * @arg @ref LL_DMAMUX_REQ_LPUART3_RX
555 * @arg @ref LL_DMAMUX_REQ_LPUART3_TX
556 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
557 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
558 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
559 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
560 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
561 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
562 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
563 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
564 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
565 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
566 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
567 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
568 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
569 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
570 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
571 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
572 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
573 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
574 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
575 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
576 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
577 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
578 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
579 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
580 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
581 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
582 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
583 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
584 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
585 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
586 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
587 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
588 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
589 * @arg @ref LL_DMAMUX_REQ_USART1_RX
590 * @arg @ref LL_DMAMUX_REQ_USART1_TX
591 * @arg @ref LL_DMAMUX_REQ_USART2_RX
592 * @arg @ref LL_DMAMUX_REQ_USART2_TX
593 * @arg @ref LL_DMAMUX_REQ_USART3_RX
594 * @arg @ref LL_DMAMUX_REQ_USART3_TX
595 * @arg @ref LL_DMAMUX_REQ_USART4_RX
596 * @arg @ref LL_DMAMUX_REQ_USART4_TX
597 */
LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)598 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
599 {
600 (void)(DMAMUXx);
601 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
602 }
603
604 /**
605 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of
606 * DMA request needed to generate an event.
607 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
608 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
609 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
610 * @param DMAMUXx DMAMUXx Instance
611 * @param Channel This parameter can be one of the following values:
612 * @arg @ref LL_DMAMUX_CHANNEL_0
613 * @arg @ref LL_DMAMUX_CHANNEL_1
614 * @arg @ref LL_DMAMUX_CHANNEL_2
615 * @arg @ref LL_DMAMUX_CHANNEL_3
616 * @arg @ref LL_DMAMUX_CHANNEL_4
617 * @arg @ref LL_DMAMUX_CHANNEL_5
618 * @arg @ref LL_DMAMUX_CHANNEL_6
619 *
620 * @arg All the next values are only available on chip which support DMA2:
621 * @arg @ref LL_DMAMUX_CHANNEL_7
622 * @arg @ref LL_DMAMUX_CHANNEL_8
623 * @arg @ref LL_DMAMUX_CHANNEL_9
624 * @arg @ref LL_DMAMUX_CHANNEL_10
625 * @arg @ref LL_DMAMUX_CHANNEL_11
626 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
627 * @retval None
628 */
LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t RequestNb)629 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel,
630 uint32_t RequestNb)
631 {
632 (void)(DMAMUXx);
633 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
634 }
635
636 /**
637 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of
638 * DMA request needed to generate an event.
639 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
640 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
641 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
642 * @param DMAMUXx DMAMUXx Instance
643 * @param Channel This parameter can be one of the following values:
644 * @arg @ref LL_DMAMUX_CHANNEL_0
645 * @arg @ref LL_DMAMUX_CHANNEL_1
646 * @arg @ref LL_DMAMUX_CHANNEL_2
647 * @arg @ref LL_DMAMUX_CHANNEL_3
648 * @arg @ref LL_DMAMUX_CHANNEL_4
649 * @arg @ref LL_DMAMUX_CHANNEL_5
650 * @arg @ref LL_DMAMUX_CHANNEL_6
651 *
652 * @arg All the next values are only available on chip which support DMA2:
653 * @arg @ref LL_DMAMUX_CHANNEL_7
654 * @arg @ref LL_DMAMUX_CHANNEL_8
655 * @arg @ref LL_DMAMUX_CHANNEL_9
656 * @arg @ref LL_DMAMUX_CHANNEL_10
657 * @arg @ref LL_DMAMUX_CHANNEL_11
658 * @retval Between Min_Data = 1 and Max_Data = 32
659 */
LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)660 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
661 {
662 (void)(DMAMUXx);
663 return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
664 }
665
666 /**
667 * @brief Set the polarity of the signal on which the DMA request is synchronized.
668 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
669 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
670 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
671 * @param DMAMUXx DMAMUXx Instance
672 * @param Channel This parameter can be one of the following values:
673 * @arg @ref LL_DMAMUX_CHANNEL_0
674 * @arg @ref LL_DMAMUX_CHANNEL_1
675 * @arg @ref LL_DMAMUX_CHANNEL_2
676 * @arg @ref LL_DMAMUX_CHANNEL_3
677 * @arg @ref LL_DMAMUX_CHANNEL_4
678 * @arg @ref LL_DMAMUX_CHANNEL_5
679 * @arg @ref LL_DMAMUX_CHANNEL_6
680 *
681 * @arg All the next values are only available on chip which support DMA2:
682 * @arg @ref LL_DMAMUX_CHANNEL_7
683 * @arg @ref LL_DMAMUX_CHANNEL_8
684 * @arg @ref LL_DMAMUX_CHANNEL_9
685 * @arg @ref LL_DMAMUX_CHANNEL_10
686 * @arg @ref LL_DMAMUX_CHANNEL_11
687 * @param Polarity This parameter can be one of the following values:
688 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
689 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
690 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
691 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
692 * @retval None
693 */
LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Polarity)694 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel,
695 uint32_t Polarity)
696 {
697 (void)(DMAMUXx);
698 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
699 }
700
701 /**
702 * @brief Get the polarity of the signal on which the DMA request is synchronized.
703 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
704 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
705 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
706 * @param DMAMUXx DMAMUXx Instance
707 * @param Channel This parameter can be one of the following values:
708 * @arg @ref LL_DMAMUX_CHANNEL_0
709 * @arg @ref LL_DMAMUX_CHANNEL_1
710 * @arg @ref LL_DMAMUX_CHANNEL_2
711 * @arg @ref LL_DMAMUX_CHANNEL_3
712 * @arg @ref LL_DMAMUX_CHANNEL_4
713 * @arg @ref LL_DMAMUX_CHANNEL_5
714 * @arg @ref LL_DMAMUX_CHANNEL_6
715 *
716 * @arg All the next values are only available on chip which support DMA2:
717 * @arg @ref LL_DMAMUX_CHANNEL_7
718 * @arg @ref LL_DMAMUX_CHANNEL_8
719 * @arg @ref LL_DMAMUX_CHANNEL_9
720 * @arg @ref LL_DMAMUX_CHANNEL_10
721 * @arg @ref LL_DMAMUX_CHANNEL_11
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
724 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
725 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
726 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
727 */
LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)728 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
729 {
730 (void)(DMAMUXx);
731 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
732 }
733
734 /**
735 * @brief Enable the Event Generation on DMAMUX channel x.
736 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
737 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
738 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
739 * @param DMAMUXx DMAMUXx Instance
740 * @param Channel This parameter can be one of the following values:
741 * @arg @ref LL_DMAMUX_CHANNEL_0
742 * @arg @ref LL_DMAMUX_CHANNEL_1
743 * @arg @ref LL_DMAMUX_CHANNEL_2
744 * @arg @ref LL_DMAMUX_CHANNEL_3
745 * @arg @ref LL_DMAMUX_CHANNEL_4
746 * @arg @ref LL_DMAMUX_CHANNEL_5
747 * @arg @ref LL_DMAMUX_CHANNEL_6
748 *
749 * @arg All the next values are only available on chip which support DMA2:
750 * @arg @ref LL_DMAMUX_CHANNEL_7
751 * @arg @ref LL_DMAMUX_CHANNEL_8
752 * @arg @ref LL_DMAMUX_CHANNEL_9
753 * @arg @ref LL_DMAMUX_CHANNEL_10
754 * @arg @ref LL_DMAMUX_CHANNEL_11
755 * @retval None
756 */
LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)757 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
758 {
759 (void)(DMAMUXx);
760 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
761 }
762
763 /**
764 * @brief Disable the Event Generation on DMAMUX channel x.
765 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
766 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
767 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
768 * @param DMAMUXx DMAMUXx Instance
769 * @param Channel This parameter can be one of the following values:
770 * @arg @ref LL_DMAMUX_CHANNEL_0
771 * @arg @ref LL_DMAMUX_CHANNEL_1
772 * @arg @ref LL_DMAMUX_CHANNEL_2
773 * @arg @ref LL_DMAMUX_CHANNEL_3
774 * @arg @ref LL_DMAMUX_CHANNEL_4
775 * @arg @ref LL_DMAMUX_CHANNEL_5
776 * @arg @ref LL_DMAMUX_CHANNEL_6
777 *
778 * @arg All the next values are only available on chip which support DMA2:
779 * @arg @ref LL_DMAMUX_CHANNEL_7
780 * @arg @ref LL_DMAMUX_CHANNEL_8
781 * @arg @ref LL_DMAMUX_CHANNEL_9
782 * @arg @ref LL_DMAMUX_CHANNEL_10
783 * @arg @ref LL_DMAMUX_CHANNEL_11
784 * @retval None
785 */
LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)786 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
787 {
788 (void)(DMAMUXx);
789 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
790 }
791
792 /**
793 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
794 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
795 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
796 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
797 * @param DMAMUXx DMAMUXx Instance
798 * @param Channel This parameter can be one of the following values:
799 * @arg @ref LL_DMAMUX_CHANNEL_0
800 * @arg @ref LL_DMAMUX_CHANNEL_1
801 * @arg @ref LL_DMAMUX_CHANNEL_2
802 * @arg @ref LL_DMAMUX_CHANNEL_3
803 * @arg @ref LL_DMAMUX_CHANNEL_4
804 * @arg @ref LL_DMAMUX_CHANNEL_5
805 * @arg @ref LL_DMAMUX_CHANNEL_6
806 *
807 * @arg All the next values are only available on chip which support DMA2:
808 * @arg @ref LL_DMAMUX_CHANNEL_7
809 * @arg @ref LL_DMAMUX_CHANNEL_8
810 * @arg @ref LL_DMAMUX_CHANNEL_9
811 * @arg @ref LL_DMAMUX_CHANNEL_10
812 * @arg @ref LL_DMAMUX_CHANNEL_11
813 * @retval State of bit (1 or 0).
814 */
LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)815 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
816 {
817 (void)(DMAMUXx);
818 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
819 }
820
821 /**
822 * @brief Enable the synchronization mode.
823 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
824 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
825 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
826 * @param DMAMUXx DMAMUXx Instance
827 * @param Channel This parameter can be one of the following values:
828 * @arg @ref LL_DMAMUX_CHANNEL_0
829 * @arg @ref LL_DMAMUX_CHANNEL_1
830 * @arg @ref LL_DMAMUX_CHANNEL_2
831 * @arg @ref LL_DMAMUX_CHANNEL_3
832 * @arg @ref LL_DMAMUX_CHANNEL_4
833 * @arg @ref LL_DMAMUX_CHANNEL_5
834 * @arg @ref LL_DMAMUX_CHANNEL_6
835 *
836 * @arg All the next values are only available on chip which support DMA2:
837 * @arg @ref LL_DMAMUX_CHANNEL_7
838 * @arg @ref LL_DMAMUX_CHANNEL_8
839 * @arg @ref LL_DMAMUX_CHANNEL_9
840 * @arg @ref LL_DMAMUX_CHANNEL_10
841 * @arg @ref LL_DMAMUX_CHANNEL_11
842 * @retval None
843 */
LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)844 __STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
845 {
846 (void)(DMAMUXx);
847 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
848 }
849
850 /**
851 * @brief Disable the synchronization mode.
852 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
853 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
854 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
855 * @param DMAMUXx DMAMUXx Instance
856 * @param Channel This parameter can be one of the following values:
857 * @arg @ref LL_DMAMUX_CHANNEL_0
858 * @arg @ref LL_DMAMUX_CHANNEL_1
859 * @arg @ref LL_DMAMUX_CHANNEL_2
860 * @arg @ref LL_DMAMUX_CHANNEL_3
861 * @arg @ref LL_DMAMUX_CHANNEL_4
862 * @arg @ref LL_DMAMUX_CHANNEL_5
863 * @arg @ref LL_DMAMUX_CHANNEL_6
864 *
865 * @arg All the next values are only available on chip which support DMA2:
866 * @arg @ref LL_DMAMUX_CHANNEL_7
867 * @arg @ref LL_DMAMUX_CHANNEL_8
868 * @arg @ref LL_DMAMUX_CHANNEL_9
869 * @arg @ref LL_DMAMUX_CHANNEL_10
870 * @arg @ref LL_DMAMUX_CHANNEL_11
871 * @retval None
872 */
LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)873 __STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
874 {
875 (void)(DMAMUXx);
876 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
877 }
878
879 /**
880 * @brief Check if the synchronization mode is enabled or disabled.
881 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
882 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
883 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
884 * @param DMAMUXx DMAMUXx Instance
885 * @param Channel This parameter can be one of the following values:
886 * @arg @ref LL_DMAMUX_CHANNEL_0
887 * @arg @ref LL_DMAMUX_CHANNEL_1
888 * @arg @ref LL_DMAMUX_CHANNEL_2
889 * @arg @ref LL_DMAMUX_CHANNEL_3
890 * @arg @ref LL_DMAMUX_CHANNEL_4
891 * @arg @ref LL_DMAMUX_CHANNEL_5
892 * @arg @ref LL_DMAMUX_CHANNEL_6
893 *
894 * @arg All the next values are only available on chip which support DMA2:
895 * @arg @ref LL_DMAMUX_CHANNEL_7
896 * @arg @ref LL_DMAMUX_CHANNEL_8
897 * @arg @ref LL_DMAMUX_CHANNEL_9
898 * @arg @ref LL_DMAMUX_CHANNEL_10
899 * @arg @ref LL_DMAMUX_CHANNEL_11
900 * @retval State of bit (1 or 0).
901 */
LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)902 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
903 {
904 (void)(DMAMUXx);
905 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
906 }
907
908 /**
909 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
910 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
911 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
912 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
913 * @param DMAMUXx DMAMUXx Instance
914 * @param Channel This parameter can be one of the following values:
915 * @arg @ref LL_DMAMUX_CHANNEL_0
916 * @arg @ref LL_DMAMUX_CHANNEL_1
917 * @arg @ref LL_DMAMUX_CHANNEL_2
918 * @arg @ref LL_DMAMUX_CHANNEL_3
919 * @arg @ref LL_DMAMUX_CHANNEL_4
920 * @arg @ref LL_DMAMUX_CHANNEL_5
921 * @arg @ref LL_DMAMUX_CHANNEL_6
922 *
923 * @arg All the next values are only available on chip which support DMA2:
924 * @arg @ref LL_DMAMUX_CHANNEL_7
925 * @arg @ref LL_DMAMUX_CHANNEL_8
926 * @arg @ref LL_DMAMUX_CHANNEL_9
927 * @arg @ref LL_DMAMUX_CHANNEL_10
928 * @arg @ref LL_DMAMUX_CHANNEL_11
929 * @param SyncID This parameter can be one of the following values:
930 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
931 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
932 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
933 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
934 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
935 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
936 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
937 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
938 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
939 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
940 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
941 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
942 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
943 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
944 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
945 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
946 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
947 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
948 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
949 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
950 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
951 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
952 * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT
953 * @retval None
954 */
LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t SyncID)955 __STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
956 {
957 (void)(DMAMUXx);
958 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
959 }
960
961 /**
962 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
963 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
964 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
965 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
966 * @param DMAMUXx DMAMUXx Instance
967 * @param Channel This parameter can be one of the following values:
968 * @arg @ref LL_DMAMUX_CHANNEL_0
969 * @arg @ref LL_DMAMUX_CHANNEL_1
970 * @arg @ref LL_DMAMUX_CHANNEL_2
971 * @arg @ref LL_DMAMUX_CHANNEL_3
972 * @arg @ref LL_DMAMUX_CHANNEL_4
973 * @arg @ref LL_DMAMUX_CHANNEL_5
974 * @arg @ref LL_DMAMUX_CHANNEL_6
975 *
976 * @arg All the next values are only available on chip which support DMA2:
977 * @arg @ref LL_DMAMUX_CHANNEL_7
978 * @arg @ref LL_DMAMUX_CHANNEL_8
979 * @arg @ref LL_DMAMUX_CHANNEL_9
980 * @arg @ref LL_DMAMUX_CHANNEL_10
981 * @arg @ref LL_DMAMUX_CHANNEL_11
982 * @retval Returned value can be one of the following values:
983 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
984 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
985 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
986 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
987 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
988 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
989 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
990 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
991 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
992 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
993 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
994 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
995 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
996 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
997 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
998 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
999 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
1000 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
1001 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
1002 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
1003 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
1004 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
1005 * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT
1006 */
LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1007 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1008 {
1009 (void)(DMAMUXx);
1010 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
1011 }
1012
1013 /**
1014 * @brief Enable the Request Generator.
1015 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1016 * @param DMAMUXx DMAMUXx Instance
1017 * @param RequestGenChannel This parameter can be one of the following values:
1018 * @arg @ref LL_DMAMUX_REQ_GEN_0
1019 * @arg @ref LL_DMAMUX_REQ_GEN_1
1020 * @arg @ref LL_DMAMUX_REQ_GEN_2
1021 * @arg @ref LL_DMAMUX_REQ_GEN_3
1022 * @retval None
1023 */
LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1024 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1025 {
1026 (void)(DMAMUXx);
1027 SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1028 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
1029 }
1030
1031 /**
1032 * @brief Disable the Request Generator.
1033 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1034 * @param DMAMUXx DMAMUXx Instance
1035 * @param RequestGenChannel This parameter can be one of the following values:
1036 * @arg @ref LL_DMAMUX_REQ_GEN_0
1037 * @arg @ref LL_DMAMUX_REQ_GEN_1
1038 * @arg @ref LL_DMAMUX_REQ_GEN_2
1039 * @arg @ref LL_DMAMUX_REQ_GEN_3
1040 * @retval None
1041 */
LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1042 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1043 {
1044 (void)(DMAMUXx);
1045 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *) \
1046 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1047 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
1048 }
1049
1050 /**
1051 * @brief Check if the Request Generator is enabled or disabled.
1052 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1053 * @param DMAMUXx DMAMUXx Instance
1054 * @param RequestGenChannel This parameter can be one of the following values:
1055 * @arg @ref LL_DMAMUX_REQ_GEN_0
1056 * @arg @ref LL_DMAMUX_REQ_GEN_1
1057 * @arg @ref LL_DMAMUX_REQ_GEN_2
1058 * @arg @ref LL_DMAMUX_REQ_GEN_3
1059 * @retval State of bit (1 or 0).
1060 */
LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1061 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx,
1062 uint32_t RequestGenChannel)
1063 {
1064 (void)(DMAMUXx);
1065 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1066 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR,
1067 DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1068 }
1069
1070 /**
1071 * @brief Set the polarity of the signal on which the DMA request is generated.
1072 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1073 * @param DMAMUXx DMAMUXx Instance
1074 * @param RequestGenChannel This parameter can be one of the following values:
1075 * @arg @ref LL_DMAMUX_REQ_GEN_0
1076 * @arg @ref LL_DMAMUX_REQ_GEN_1
1077 * @arg @ref LL_DMAMUX_REQ_GEN_2
1078 * @arg @ref LL_DMAMUX_REQ_GEN_3
1079 * @param Polarity This parameter can be one of the following values:
1080 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1081 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1082 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1083 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1084 * @retval None
1085 */
LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t Polarity)1086 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1087 uint32_t Polarity)
1088 {
1089 (void)(DMAMUXx);
1090 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *) \
1091 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1092 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1093 }
1094
1095 /**
1096 * @brief Get the polarity of the signal on which the DMA request is generated.
1097 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1098 * @param DMAMUXx DMAMUXx Instance
1099 * @param RequestGenChannel This parameter can be one of the following values:
1100 * @arg @ref LL_DMAMUX_REQ_GEN_0
1101 * @arg @ref LL_DMAMUX_REQ_GEN_1
1102 * @arg @ref LL_DMAMUX_REQ_GEN_2
1103 * @arg @ref LL_DMAMUX_REQ_GEN_3
1104 * @retval Returned value can be one of the following values:
1105 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1106 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1107 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1108 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1109 */
LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1110 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx,
1111 uint32_t RequestGenChannel)
1112 {
1113 (void)(DMAMUXx);
1114 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *) \
1115 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1116 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
1117 }
1118
1119 /**
1120 * @brief Set the number of DMA request that will be autorized after a generation event.
1121 * @note This field can only be written when Generator is disabled.
1122 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1123 * @param DMAMUXx DMAMUXx Instance
1124 * @param RequestGenChannel This parameter can be one of the following values:
1125 * @arg @ref LL_DMAMUX_REQ_GEN_0
1126 * @arg @ref LL_DMAMUX_REQ_GEN_1
1127 * @arg @ref LL_DMAMUX_REQ_GEN_2
1128 * @arg @ref LL_DMAMUX_REQ_GEN_3
1129 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1130 * @retval None
1131 */
LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestNb)1132 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1133 uint32_t RequestNb)
1134 {
1135 (void)(DMAMUXx);
1136 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *) \
1137 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1138 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR,
1139 DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1140 }
1141
1142 /**
1143 * @brief Get the number of DMA request that will be autorized after a generation event.
1144 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1145 * @param DMAMUXx DMAMUXx Instance
1146 * @param RequestGenChannel This parameter can be one of the following values:
1147 * @arg @ref LL_DMAMUX_REQ_GEN_0
1148 * @arg @ref LL_DMAMUX_REQ_GEN_1
1149 * @arg @ref LL_DMAMUX_REQ_GEN_2
1150 * @arg @ref LL_DMAMUX_REQ_GEN_3
1151 * @retval Between Min_Data = 1 and Max_Data = 32
1152 */
LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1153 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1154 {
1155 (void)(DMAMUXx);
1156 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *) \
1157 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1158 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> \
1159 DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1160 }
1161
1162 /**
1163 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1164 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1165 * @param DMAMUXx DMAMUXx Instance
1166 * @param RequestGenChannel This parameter can be one of the following values:
1167 * @arg @ref LL_DMAMUX_REQ_GEN_0
1168 * @arg @ref LL_DMAMUX_REQ_GEN_1
1169 * @arg @ref LL_DMAMUX_REQ_GEN_2
1170 * @arg @ref LL_DMAMUX_REQ_GEN_3
1171 * @param RequestSignalID This parameter can be one of the following values:
1172 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1173 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1174 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1175 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1176 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1177 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1178 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1179 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1180 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1181 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1182 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1183 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1184 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1185 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1186 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1187 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1188 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1189 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1190 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
1191 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
1192 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1193 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1194 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT
1195 * @retval None
1196 */
LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestSignalID)1197 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1198 uint32_t RequestSignalID)
1199 {
1200 (void)(DMAMUXx);
1201 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *) \
1202 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1203 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1204 }
1205
1206 /**
1207 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1208 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1209 * @param DMAMUXx DMAMUXx Instance
1210 * @param RequestGenChannel This parameter can be one of the following values:
1211 * @arg @ref LL_DMAMUX_REQ_GEN_0
1212 * @arg @ref LL_DMAMUX_REQ_GEN_1
1213 * @arg @ref LL_DMAMUX_REQ_GEN_2
1214 * @arg @ref LL_DMAMUX_REQ_GEN_3
1215 * @retval Returned value can be one of the following values:
1216 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1217 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1218 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1219 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1220 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1221 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1222 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1223 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1224 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1225 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1226 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1227 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1228 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1229 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1230 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1231 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1232 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1233 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1234 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
1235 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
1236 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1237 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1238 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT
1239 */
LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1240 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1241 {
1242 (void)(DMAMUXx);
1243 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *) \
1244 ((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + \
1245 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
1246 }
1247
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1253 * @{
1254 */
1255
1256 /**
1257 * @brief Get Synchronization Event Overrun Flag Channel 0.
1258 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1259 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1260 * @retval State of bit (1 or 0).
1261 */
LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef * DMAMUXx)1262 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1263 {
1264 (void)(DMAMUXx);
1265 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1266 }
1267
1268 /**
1269 * @brief Get Synchronization Event Overrun Flag Channel 1.
1270 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1271 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1272 * @retval State of bit (1 or 0).
1273 */
LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef * DMAMUXx)1274 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1275 {
1276 (void)(DMAMUXx);
1277 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1278 }
1279
1280 /**
1281 * @brief Get Synchronization Event Overrun Flag Channel 2.
1282 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1283 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1284 * @retval State of bit (1 or 0).
1285 */
LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef * DMAMUXx)1286 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1287 {
1288 (void)(DMAMUXx);
1289 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1290 }
1291
1292 /**
1293 * @brief Get Synchronization Event Overrun Flag Channel 3.
1294 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1295 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1296 * @retval State of bit (1 or 0).
1297 */
LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef * DMAMUXx)1298 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1299 {
1300 (void)(DMAMUXx);
1301 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1302 }
1303
1304 /**
1305 * @brief Get Synchronization Event Overrun Flag Channel 4.
1306 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1307 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1308 * @retval State of bit (1 or 0).
1309 */
LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef * DMAMUXx)1310 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1311 {
1312 (void)(DMAMUXx);
1313 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1314 }
1315
1316 /**
1317 * @brief Get Synchronization Event Overrun Flag Channel 5.
1318 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1319 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1320 * @retval State of bit (1 or 0).
1321 */
LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef * DMAMUXx)1322 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
1323 {
1324 (void)(DMAMUXx);
1325 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1326 }
1327
1328 /**
1329 * @brief Get Synchronization Event Overrun Flag Channel 6.
1330 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1331 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1332 * @retval State of bit (1 or 0).
1333 */
LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef * DMAMUXx)1334 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
1335 {
1336 (void)(DMAMUXx);
1337 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1338 }
1339
1340 #if defined(DMAMUX1_Channel7)
1341 /**
1342 * @brief Get Synchronization Event Overrun Flag Channel 7.
1343 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1344 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1345 * @retval State of bit (1 or 0).
1346 */
LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef * DMAMUXx)1347 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
1348 {
1349 (void)(DMAMUXx);
1350 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1351 }
1352
1353 #endif /* DMAMUX1_Channel7 */
1354 #if defined(DMAMUX1_Channel8)
1355 /**
1356 * @brief Get Synchronization Event Overrun Flag Channel 8.
1357 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1358 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1359 * @retval State of bit (1 or 0).
1360 */
LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef * DMAMUXx)1361 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
1362 {
1363 (void)(DMAMUXx);
1364 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1365 }
1366
1367 #endif /* DMAMUX1_Channel8 */
1368 #if defined(DMAMUX1_Channel9)
1369 /**
1370 * @brief Get Synchronization Event Overrun Flag Channel 9.
1371 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1372 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1373 * @retval State of bit (1 or 0).
1374 */
LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef * DMAMUXx)1375 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
1376 {
1377 (void)(DMAMUXx);
1378 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1379 }
1380
1381 #endif /* DMAMUX1_Channel9 */
1382 #if defined(DMAMUX1_Channel10)
1383 /**
1384 * @brief Get Synchronization Event Overrun Flag Channel 10.
1385 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1386 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1387 * @retval State of bit (1 or 0).
1388 */
LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef * DMAMUXx)1389 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
1390 {
1391 (void)(DMAMUXx);
1392 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1393 }
1394
1395 #endif /* DMAMUX1_Channel10 */
1396 #if defined(DMAMUX1_Channel11)
1397 /**
1398 * @brief Get Synchronization Event Overrun Flag Channel 11.
1399 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1400 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1401 * @retval State of bit (1 or 0).
1402 */
LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef * DMAMUXx)1403 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
1404 {
1405 (void)(DMAMUXx);
1406 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1407 }
1408
1409 #endif /* DMAMUX1_Channel11 */
1410 /**
1411 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1412 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1413 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1414 * @retval State of bit (1 or 0).
1415 */
LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef * DMAMUXx)1416 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1417 {
1418 (void)(DMAMUXx);
1419 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1420 }
1421
1422 /**
1423 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1424 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1425 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1426 * @retval State of bit (1 or 0).
1427 */
LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef * DMAMUXx)1428 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1429 {
1430 (void)(DMAMUXx);
1431 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1432 }
1433
1434 /**
1435 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1436 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1437 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1438 * @retval State of bit (1 or 0).
1439 */
LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef * DMAMUXx)1440 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1441 {
1442 (void)(DMAMUXx);
1443 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1444 }
1445
1446 /**
1447 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1448 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1449 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1450 * @retval State of bit (1 or 0).
1451 */
LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef * DMAMUXx)1452 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1453 {
1454 (void)(DMAMUXx);
1455 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1456 }
1457
1458 /**
1459 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1460 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1461 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1462 * @retval None
1463 */
LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef * DMAMUXx)1464 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1465 {
1466 (void)(DMAMUXx);
1467 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
1468 }
1469
1470 /**
1471 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1472 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1473 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1474 * @retval None
1475 */
LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef * DMAMUXx)1476 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1477 {
1478 (void)(DMAMUXx);
1479 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
1480 }
1481
1482 /**
1483 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1484 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1485 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1486 * @retval None
1487 */
LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef * DMAMUXx)1488 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1489 {
1490 (void)(DMAMUXx);
1491 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
1492 }
1493
1494 /**
1495 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1496 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1497 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1498 * @retval None
1499 */
LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef * DMAMUXx)1500 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1501 {
1502 (void)(DMAMUXx);
1503 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
1504 }
1505
1506 /**
1507 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1508 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1509 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1510 * @retval None
1511 */
LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef * DMAMUXx)1512 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1513 {
1514 (void)(DMAMUXx);
1515 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
1516 }
1517
1518 /**
1519 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1520 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1521 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1522 * @retval None
1523 */
LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef * DMAMUXx)1524 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
1525 {
1526 (void)(DMAMUXx);
1527 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
1528 }
1529
1530 /**
1531 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1532 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1533 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1534 * @retval None
1535 */
LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef * DMAMUXx)1536 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
1537 {
1538 (void)(DMAMUXx);
1539 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
1540 }
1541
1542 #if defined(DMAMUX1_Channel7)
1543 /**
1544 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1545 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1546 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1547 * @retval None
1548 */
LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef * DMAMUXx)1549 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
1550 {
1551 (void)(DMAMUXx);
1552 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
1553 }
1554
1555 #endif /* DMAMUX1_Channel7 */
1556 #if defined(DMAMUX1_Channel8)
1557 /**
1558 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1559 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1560 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1561 * @retval None
1562 */
LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef * DMAMUXx)1563 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
1564 {
1565 (void)(DMAMUXx);
1566 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
1567 }
1568
1569 #endif /* DMAMUX1_Channel8 */
1570 #if defined(DMAMUX1_Channel9)
1571 /**
1572 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1573 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1574 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1575 * @retval None
1576 */
LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef * DMAMUXx)1577 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
1578 {
1579 (void)(DMAMUXx);
1580 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
1581 }
1582
1583 #endif /* DMAMUX1_Channel9 */
1584 #if defined(DMAMUX1_Channel10)
1585 /**
1586 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1587 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1588 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1589 * @retval None
1590 */
LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef * DMAMUXx)1591 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
1592 {
1593 (void)(DMAMUXx);
1594 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
1595 }
1596
1597 #endif /* DMAMUX1_Channel10 */
1598 #if defined(DMAMUX1_Channel11)
1599 /**
1600 * @brief Clear Synchronization Event Overrun Flag Channel 11.
1601 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
1602 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1603 * @retval None
1604 */
LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef * DMAMUXx)1605 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
1606 {
1607 (void)(DMAMUXx);
1608 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
1609 }
1610
1611 #endif /* DMAMUX1_Channel11 */
1612 /**
1613 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
1614 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
1615 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1616 * @retval None
1617 */
LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef * DMAMUXx)1618 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1619 {
1620 (void)(DMAMUXx);
1621 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
1622 }
1623
1624 /**
1625 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
1626 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
1627 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1628 * @retval None
1629 */
LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef * DMAMUXx)1630 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1631 {
1632 (void)(DMAMUXx);
1633 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
1634 }
1635
1636 /**
1637 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
1638 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
1639 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1640 * @retval None
1641 */
LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef * DMAMUXx)1642 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1643 {
1644 (void)(DMAMUXx);
1645 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
1646 }
1647
1648 /**
1649 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
1650 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
1651 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1652 * @retval None
1653 */
LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef * DMAMUXx)1654 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1655 {
1656 (void)(DMAMUXx);
1657 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
1658 }
1659
1660 /**
1661 * @}
1662 */
1663
1664 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
1665 * @{
1666 */
1667
1668 /**
1669 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1670 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1671 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
1672 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
1673 * @param DMAMUXx DMAMUXx Instance
1674 * @param Channel This parameter can be one of the following values:
1675 * @arg @ref LL_DMAMUX_CHANNEL_0
1676 * @arg @ref LL_DMAMUX_CHANNEL_1
1677 * @arg @ref LL_DMAMUX_CHANNEL_2
1678 * @arg @ref LL_DMAMUX_CHANNEL_3
1679 * @arg @ref LL_DMAMUX_CHANNEL_4
1680 * @arg @ref LL_DMAMUX_CHANNEL_5
1681 * @arg @ref LL_DMAMUX_CHANNEL_6
1682 *
1683 * @arg All the next values are only available on chip which support DMA2:
1684 * @arg @ref LL_DMAMUX_CHANNEL_7
1685 * @arg @ref LL_DMAMUX_CHANNEL_8
1686 * @arg @ref LL_DMAMUX_CHANNEL_9
1687 * @arg @ref LL_DMAMUX_CHANNEL_10
1688 * @arg @ref LL_DMAMUX_CHANNEL_11
1689 * @retval None
1690 */
LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1691 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1692 {
1693 (void)(DMAMUXx);
1694 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1695 }
1696
1697 /**
1698 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1699 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1700 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
1701 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
1702 * @param DMAMUXx DMAMUXx Instance
1703 * @param Channel This parameter can be one of the following values:
1704 * @arg @ref LL_DMAMUX_CHANNEL_0
1705 * @arg @ref LL_DMAMUX_CHANNEL_1
1706 * @arg @ref LL_DMAMUX_CHANNEL_2
1707 * @arg @ref LL_DMAMUX_CHANNEL_3
1708 * @arg @ref LL_DMAMUX_CHANNEL_4
1709 * @arg @ref LL_DMAMUX_CHANNEL_5
1710 * @arg @ref LL_DMAMUX_CHANNEL_6
1711 *
1712 * @arg All the next values are only available on chip which support DMA2:
1713 * @arg @ref LL_DMAMUX_CHANNEL_7
1714 * @arg @ref LL_DMAMUX_CHANNEL_8
1715 * @arg @ref LL_DMAMUX_CHANNEL_9
1716 * @arg @ref LL_DMAMUX_CHANNEL_10
1717 * @arg @ref LL_DMAMUX_CHANNEL_11
1718 * @retval None
1719 */
LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1720 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1721 {
1722 (void)(DMAMUXx);
1723 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1724 }
1725
1726 /**
1727 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1728 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1729 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
1730 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
1731 * @param DMAMUXx DMAMUXx Instance
1732 * @param Channel This parameter can be one of the following values:
1733 * @arg @ref LL_DMAMUX_CHANNEL_0
1734 * @arg @ref LL_DMAMUX_CHANNEL_1
1735 * @arg @ref LL_DMAMUX_CHANNEL_2
1736 * @arg @ref LL_DMAMUX_CHANNEL_3
1737 * @arg @ref LL_DMAMUX_CHANNEL_4
1738 * @arg @ref LL_DMAMUX_CHANNEL_5
1739 * @arg @ref LL_DMAMUX_CHANNEL_6
1740 *
1741 * @arg All the next values are only available on chip which support DMA2:
1742 * @arg @ref LL_DMAMUX_CHANNEL_7
1743 * @arg @ref LL_DMAMUX_CHANNEL_8
1744 * @arg @ref LL_DMAMUX_CHANNEL_9
1745 * @arg @ref LL_DMAMUX_CHANNEL_10
1746 * @arg @ref LL_DMAMUX_CHANNEL_11
1747 * @retval State of bit (1 or 0).
1748 */
LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1749 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1750 {
1751 (void)(DMAMUXx);
1752 return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
1753 }
1754
1755 /**
1756 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1757 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
1758 * @param DMAMUXx DMAMUXx Instance
1759 * @param RequestGenChannel This parameter can be one of the following values:
1760 * @arg @ref LL_DMAMUX_REQ_GEN_0
1761 * @arg @ref LL_DMAMUX_REQ_GEN_1
1762 * @arg @ref LL_DMAMUX_REQ_GEN_2
1763 * @arg @ref LL_DMAMUX_REQ_GEN_3
1764 * @retval None
1765 */
LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1766 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1767 {
1768 (void)(DMAMUXx);
1769 SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1770 }
1771
1772 /**
1773 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1774 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
1775 * @param DMAMUXx DMAMUXx Instance
1776 * @param RequestGenChannel This parameter can be one of the following values:
1777 * @arg @ref LL_DMAMUX_REQ_GEN_0
1778 * @arg @ref LL_DMAMUX_REQ_GEN_1
1779 * @arg @ref LL_DMAMUX_REQ_GEN_2
1780 * @arg @ref LL_DMAMUX_REQ_GEN_3
1781 * @retval None
1782 */
LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1783 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1784 {
1785 (void)(DMAMUXx);
1786 CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1787 }
1788
1789 /**
1790 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1791 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
1792 * @param DMAMUXx DMAMUXx Instance
1793 * @param RequestGenChannel This parameter can be one of the following values:
1794 * @arg @ref LL_DMAMUX_REQ_GEN_0
1795 * @arg @ref LL_DMAMUX_REQ_GEN_1
1796 * @arg @ref LL_DMAMUX_REQ_GEN_2
1797 * @arg @ref LL_DMAMUX_REQ_GEN_3
1798 * @retval State of bit (1 or 0).
1799 */
LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1800 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1801 {
1802 (void)(DMAMUXx);
1803 return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == \
1804 (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
1805 }
1806
1807 /**
1808 * @}
1809 */
1810
1811 /**
1812 * @}
1813 */
1814
1815 /**
1816 * @}
1817 */
1818
1819 #endif /* DMAMUX1 */
1820
1821 /**
1822 * @}
1823 */
1824
1825 #ifdef __cplusplus
1826 }
1827 #endif
1828
1829 #endif /* STM32U0xx_LL_DMAMUX_H */
1830
