1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_dma.h
4 * @author GPM Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_DMA_H
21 #define STM32U0xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29 #include "stm32u0xx_ll_dmamux.h"
30
31 /** @addtogroup STM32U0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
56 };
57 /**
58 * @}
59 */
60
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63
64 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
65 * @{
66 */
67 /**
68 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
69 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
70 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
71 * @param __DMA_INSTANCE__ DMAx
72 * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
73 */
74 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
75 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
76 /**
77 * @}
78 */
79 /* Exported types ------------------------------------------------------------*/
80 #if defined(USE_FULL_LL_DRIVER)
81 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
82 * @{
83 */
84 typedef struct
85 {
86 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
87 or as Source base address in case of memory to memory transfer direction.
88
89 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */
90
91 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
92 or as Destination base address in case of memory to memory transfer direction.
93
94 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */
95
96 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
97 from memory to memory or from peripheral to memory.
98 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_DMA_SetDataTransferDirection(). */
102
103 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
104 This parameter can be a value of @ref DMA_LL_EC_MODE
105 @note: The circular buffer mode cannot be used if the memory to memory
106 data transfer direction is configured on the selected Channel
107
108 This feature can be modified afterwards using unitary function
109 @ref LL_DMA_SetMode(). */
110
111 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of
112 memory to memory transfer direction is incremented or not.
113 This parameter can be a value of @ref DMA_LL_EC_PERIPH
114
115 This feature can be modified afterwards using unitary function
116 @ref LL_DMA_SetPeriphIncMode(). */
117
118 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory
119 to memory transfer direction is incremented or not.
120 This parameter can be a value of @ref DMA_LL_EC_MEMORY
121
122 This feature can be modified afterwards using unitary function
123 @ref LL_DMA_SetMemoryIncMode(). */
124
125 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment
126 (byte, half word, word) in case of memory to memory transfer direction.
127 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
128
129 This feature can be modified afterwards using unitary function
130 @ref LL_DMA_SetPeriphSize(). */
131
132 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment
133 (byte, half word, word) in case of memory to memory transfer direction.
134 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
135
136 This feature can be modified afterwards using unitary function
137 @ref LL_DMA_SetMemorySize(). */
138
139 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
140 The data unit is equal to the source buffer configuration set in PeripheralSize
141 or MemorySize parameters depending in the transfer direction.
142 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
143
144 This feature can be modified afterwards using unitary function
145 @ref LL_DMA_SetDataLength(). */
146
147 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
148 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
149
150 This feature can be modified afterwards using unitary function
151 @ref LL_DMA_SetPeriphRequest(). */
152
153 uint32_t Priority; /*!< Specifies the channel priority level.
154 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
155
156 This feature can be modified afterwards using unitary function
157 @ref LL_DMA_SetChannelPriorityLevel(). */
158
159 } LL_DMA_InitTypeDef;
160 /**
161 * @}
162 */
163 #endif /*USE_FULL_LL_DRIVER*/
164
165 /* Exported constants --------------------------------------------------------*/
166 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
167 * @{
168 */
169 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
170 * @brief Flags defines which can be used with LL_DMA_WriteReg function
171 * @{
172 */
173 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
174 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
175 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
176 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
177 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
178 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
179 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
180 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
181 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
182 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
183 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
184 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
185 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
186 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
187 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
188 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
189 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
190 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
191 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
192 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
193 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
194 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
195 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
196 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
197 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
198 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
199 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
200 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
201 /**
202 * @}
203 */
204
205 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
206 * @brief Flags defines which can be used with LL_DMA_ReadReg function
207 * @{
208 */
209 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
210 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
211 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
212 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
213 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
214 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
215 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
216 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
217 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
218 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
219 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
220 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
221 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
222 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
223 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
224 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
225 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
226 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
227 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
228 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
229 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
230 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
231 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
232 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
233 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
234 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
235 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
236 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
237 /**
238 * @}
239 */
240
241 /** @defgroup DMA_LL_EC_IT IT Defines
242 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
243 * @{
244 */
245 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
246 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
247 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
248 /**
249 * @}
250 */
251
252 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
253 * @{
254 */
255 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
256 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
257 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
258 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
259 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
260 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
261 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
262 #if defined(USE_FULL_LL_DRIVER)
263 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit() */
264 #endif /*USE_FULL_LL_DRIVER*/
265 /**
266 * @}
267 */
268
269 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
270 * @{
271 */
272 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
273 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
274 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
275 /**
276 * @}
277 */
278
279 /** @defgroup DMA_LL_EC_MODE Transfer mode
280 * @{
281 */
282 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
283 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
284 /**
285 * @}
286 */
287
288 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
289 * @{
290 */
291 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
292 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
293 /**
294 * @}
295 */
296
297 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
298 * @{
299 */
300 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
301 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
302 /**
303 * @}
304 */
305
306 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
307 * @{
308 */
309 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
310 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
311 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
312 /**
313 * @}
314 */
315
316 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
317 * @{
318 */
319 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
320 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
321 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
322 /**
323 * @}
324 */
325
326 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
327 * @{
328 */
329 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
330 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
331 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
332 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
333 /**
334 * @}
335 */
336
337 /**
338 * @}
339 */
340
341 /* Exported macro ------------------------------------------------------------*/
342 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
343 * @{
344 */
345
346 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
347 * @{
348 */
349 /**
350 * @brief Write a value in DMA register
351 * @param __INSTANCE__ DMA Instance
352 * @param __REG__ Register to be written
353 * @param __VALUE__ Value to be written in the register
354 * @retval None
355 */
356 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
357
358 /**
359 * @brief Read a value in DMA register
360 * @param __INSTANCE__ DMA Instance
361 * @param __REG__ Register to be read
362 * @retval Register value
363 */
364 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
365 /**
366 * @}
367 */
368
369 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
370 * @{
371 */
372 /**
373 * @brief Convert DMAx_Channely into DMAx
374 * @param __CHANNEL_INSTANCE__ DMAx_Channely
375 * @retval DMAx
376 */
377 #if defined(DMA2)
378 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
379 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
380 #else /* DMA1 */
381 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
382 #endif /* DMA2 */
383
384 /**
385 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
386 * @param __CHANNEL_INSTANCE__ DMAx_Channely
387 * @retval LL_DMA_CHANNEL_y
388 */
389 #if defined(DMA2)
390 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
391 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
400 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
401 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
402 LL_DMA_CHANNEL_7)
403 #else /* DMA1 */
404 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
405 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
411 LL_DMA_CHANNEL_7)
412 #endif /* DMA2 */
413
414 /**
415 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
416 * @param __DMA_INSTANCE__ DMAx
417 * @param __CHANNEL__ LL_DMA_CHANNEL_y
418 * @retval DMAx_Channely
419 */
420 #if defined(DMA2)
421 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
422 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
423 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
425 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
427 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
429 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
431 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
433 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
435 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
437 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
439 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && \
441 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
443 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
444 DMA1_Channel7)
445 #else /* DMA1 */
446 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
447 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
448 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
450 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
452 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
454 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
456 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && \
458 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
459 DMA1_Channel7)
460 #endif /* DMA2 */
461
462 /**
463 * @}
464 */
465
466 /**
467 * @}
468 */
469
470 /* Exported functions --------------------------------------------------------*/
471 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
472 * @{
473 */
474
475 /** @defgroup DMA_LL_EF_Configuration Configuration
476 * @{
477 */
478 /**
479 * @brief Enable DMA channel.
480 * @rmtoll CCR EN LL_DMA_EnableChannel
481 * @param DMAx DMAx Instance
482 * @param Channel This parameter can be one of the following values:
483 * @arg @ref LL_DMA_CHANNEL_1
484 * @arg @ref LL_DMA_CHANNEL_2
485 * @arg @ref LL_DMA_CHANNEL_3
486 * @arg @ref LL_DMA_CHANNEL_4
487 * @arg @ref LL_DMA_CHANNEL_5
488 * @arg @ref LL_DMA_CHANNEL_6
489 * @arg @ref LL_DMA_CHANNEL_7
490 * @retval None
491 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)492 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
493 {
494 uint32_t dma_base_addr = (uint32_t)DMAx;
495 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
496 }
497
498 /**
499 * @brief Disable DMA channel.
500 * @rmtoll CCR EN LL_DMA_DisableChannel
501 * @param DMAx DMAx Instance
502 * @param Channel This parameter can be one of the following values:
503 * @arg @ref LL_DMA_CHANNEL_1
504 * @arg @ref LL_DMA_CHANNEL_2
505 * @arg @ref LL_DMA_CHANNEL_3
506 * @arg @ref LL_DMA_CHANNEL_4
507 * @arg @ref LL_DMA_CHANNEL_5
508 * @arg @ref LL_DMA_CHANNEL_6
509 * @arg @ref LL_DMA_CHANNEL_7
510 * @retval None
511 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)512 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
513 {
514 uint32_t dma_base_addr = (uint32_t)DMAx;
515 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
516 }
517
518 /**
519 * @brief Check if DMA channel is enabled or disabled.
520 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
521 * @param DMAx DMAx Instance
522 * @param Channel This parameter can be one of the following values:
523 * @arg @ref LL_DMA_CHANNEL_1
524 * @arg @ref LL_DMA_CHANNEL_2
525 * @arg @ref LL_DMA_CHANNEL_3
526 * @arg @ref LL_DMA_CHANNEL_4
527 * @arg @ref LL_DMA_CHANNEL_5
528 * @arg @ref LL_DMA_CHANNEL_6
529 * @arg @ref LL_DMA_CHANNEL_7
530 * @retval State of bit (1 or 0).
531 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)532 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
533 {
534 uint32_t dma_base_addr = (uint32_t)DMAx;
535 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
536 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
537 }
538
539 /**
540 * @brief Configure all parameters link to DMA transfer.
541 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
542 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
543 * CCR CIRC LL_DMA_ConfigTransfer\n
544 * CCR PINC LL_DMA_ConfigTransfer\n
545 * CCR MINC LL_DMA_ConfigTransfer\n
546 * CCR PSIZE LL_DMA_ConfigTransfer\n
547 * CCR MSIZE LL_DMA_ConfigTransfer\n
548 * CCR PL LL_DMA_ConfigTransfer
549 * @param DMAx DMAx Instance
550 * @param Channel This parameter can be one of the following values:
551 * @arg @ref LL_DMA_CHANNEL_1
552 * @arg @ref LL_DMA_CHANNEL_2
553 * @arg @ref LL_DMA_CHANNEL_3
554 * @arg @ref LL_DMA_CHANNEL_4
555 * @arg @ref LL_DMA_CHANNEL_5
556 * @arg @ref LL_DMA_CHANNEL_6
557 * @arg @ref LL_DMA_CHANNEL_7
558 * @param Configuration This parameter must be a combination of all the following values:
559 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
560 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
561 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
562 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
563 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
564 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
565 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
566 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or
567 * @ref LL_DMA_PRIORITY_VERYHIGH
568 * @retval None
569 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)570 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
571 {
572 uint32_t dma_base_addr = (uint32_t)DMAx;
573 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
574 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | \
575 DMA_CCR_MSIZE | DMA_CCR_PL, Configuration);
576 }
577
578 /**
579 * @brief Set Data transfer direction (read from peripheral or from memory).
580 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
581 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
582 * @param DMAx DMAx Instance
583 * @param Channel This parameter can be one of the following values:
584 * @arg @ref LL_DMA_CHANNEL_1
585 * @arg @ref LL_DMA_CHANNEL_2
586 * @arg @ref LL_DMA_CHANNEL_3
587 * @arg @ref LL_DMA_CHANNEL_4
588 * @arg @ref LL_DMA_CHANNEL_5
589 * @arg @ref LL_DMA_CHANNEL_6
590 * @arg @ref LL_DMA_CHANNEL_7
591 * @param Direction This parameter can be one of the following values:
592 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
593 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
594 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
595 * @retval None
596 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)597 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
598 {
599 uint32_t dma_base_addr = (uint32_t)DMAx;
600 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
601 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
602 }
603
604 /**
605 * @brief Get Data transfer direction (read from peripheral or from memory).
606 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
607 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
608 * @param DMAx DMAx Instance
609 * @param Channel This parameter can be one of the following values:
610 * @arg @ref LL_DMA_CHANNEL_1
611 * @arg @ref LL_DMA_CHANNEL_2
612 * @arg @ref LL_DMA_CHANNEL_3
613 * @arg @ref LL_DMA_CHANNEL_4
614 * @arg @ref LL_DMA_CHANNEL_5
615 * @arg @ref LL_DMA_CHANNEL_6
616 * @arg @ref LL_DMA_CHANNEL_7
617 * @retval Returned value can be one of the following values:
618 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
619 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
620 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
621 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)622 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
623 {
624 uint32_t dma_base_addr = (uint32_t)DMAx;
625 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
626 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
627 }
628
629 /**
630 * @brief Set DMA mode circular or normal.
631 * @note The circular buffer mode cannot be used if the memory-to-memory
632 * data transfer is configured on the selected Channel.
633 * @rmtoll CCR CIRC LL_DMA_SetMode
634 * @param DMAx DMAx Instance
635 * @param Channel This parameter can be one of the following values:
636 * @arg @ref LL_DMA_CHANNEL_1
637 * @arg @ref LL_DMA_CHANNEL_2
638 * @arg @ref LL_DMA_CHANNEL_3
639 * @arg @ref LL_DMA_CHANNEL_4
640 * @arg @ref LL_DMA_CHANNEL_5
641 * @arg @ref LL_DMA_CHANNEL_6
642 * @arg @ref LL_DMA_CHANNEL_7
643 * @param Mode This parameter can be one of the following values:
644 * @arg @ref LL_DMA_MODE_NORMAL
645 * @arg @ref LL_DMA_MODE_CIRCULAR
646 * @retval None
647 */
LL_DMA_SetMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)648 __STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
649 {
650 uint32_t dma_base_addr = (uint32_t)DMAx;
651 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
652 Mode);
653 }
654
655 /**
656 * @brief Get DMA mode circular or normal.
657 * @rmtoll CCR CIRC LL_DMA_GetMode
658 * @param DMAx DMAx Instance
659 * @param Channel This parameter can be one of the following values:
660 * @arg @ref LL_DMA_CHANNEL_1
661 * @arg @ref LL_DMA_CHANNEL_2
662 * @arg @ref LL_DMA_CHANNEL_3
663 * @arg @ref LL_DMA_CHANNEL_4
664 * @arg @ref LL_DMA_CHANNEL_5
665 * @arg @ref LL_DMA_CHANNEL_6
666 * @arg @ref LL_DMA_CHANNEL_7
667 * @retval Returned value can be one of the following values:
668 * @arg @ref LL_DMA_MODE_NORMAL
669 * @arg @ref LL_DMA_MODE_CIRCULAR
670 */
LL_DMA_GetMode(const DMA_TypeDef * DMAx,uint32_t Channel)671 __STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel)
672 {
673 uint32_t dma_base_addr = (uint32_t)DMAx;
674 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
675 DMA_CCR_CIRC));
676 }
677
678 /**
679 * @brief Set Peripheral increment mode.
680 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
681 * @param DMAx DMAx Instance
682 * @param Channel This parameter can be one of the following values:
683 * @arg @ref LL_DMA_CHANNEL_1
684 * @arg @ref LL_DMA_CHANNEL_2
685 * @arg @ref LL_DMA_CHANNEL_3
686 * @arg @ref LL_DMA_CHANNEL_4
687 * @arg @ref LL_DMA_CHANNEL_5
688 * @arg @ref LL_DMA_CHANNEL_6
689 * @arg @ref LL_DMA_CHANNEL_7
690 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
691 * @arg @ref LL_DMA_PERIPH_INCREMENT
692 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
693 * @retval None
694 */
LL_DMA_SetPeriphIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)695 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
696 {
697 uint32_t dma_base_addr = (uint32_t)DMAx;
698 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
699 PeriphOrM2MSrcIncMode);
700 }
701
702 /**
703 * @brief Get Peripheral increment mode.
704 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
705 * @param DMAx DMAx Instance
706 * @param Channel This parameter can be one of the following values:
707 * @arg @ref LL_DMA_CHANNEL_1
708 * @arg @ref LL_DMA_CHANNEL_2
709 * @arg @ref LL_DMA_CHANNEL_3
710 * @arg @ref LL_DMA_CHANNEL_4
711 * @arg @ref LL_DMA_CHANNEL_5
712 * @arg @ref LL_DMA_CHANNEL_6
713 * @arg @ref LL_DMA_CHANNEL_7
714 * @retval Returned value can be one of the following values:
715 * @arg @ref LL_DMA_PERIPH_INCREMENT
716 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
717 */
LL_DMA_GetPeriphIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)718 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
719 {
720 uint32_t dma_base_addr = (uint32_t)DMAx;
721 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
722 DMA_CCR_PINC));
723 }
724
725 /**
726 * @brief Set Memory increment mode.
727 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
728 * @param DMAx DMAx Instance
729 * @param Channel This parameter can be one of the following values:
730 * @arg @ref LL_DMA_CHANNEL_1
731 * @arg @ref LL_DMA_CHANNEL_2
732 * @arg @ref LL_DMA_CHANNEL_3
733 * @arg @ref LL_DMA_CHANNEL_4
734 * @arg @ref LL_DMA_CHANNEL_5
735 * @arg @ref LL_DMA_CHANNEL_6
736 * @arg @ref LL_DMA_CHANNEL_7
737 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
738 * @arg @ref LL_DMA_MEMORY_INCREMENT
739 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
740 * @retval None
741 */
LL_DMA_SetMemoryIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)742 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
743 {
744 uint32_t dma_base_addr = (uint32_t)DMAx;
745 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
746 MemoryOrM2MDstIncMode);
747 }
748
749 /**
750 * @brief Get Memory increment mode.
751 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
752 * @param DMAx DMAx Instance
753 * @param Channel This parameter can be one of the following values:
754 * @arg @ref LL_DMA_CHANNEL_1
755 * @arg @ref LL_DMA_CHANNEL_2
756 * @arg @ref LL_DMA_CHANNEL_3
757 * @arg @ref LL_DMA_CHANNEL_4
758 * @arg @ref LL_DMA_CHANNEL_5
759 * @arg @ref LL_DMA_CHANNEL_6
760 * @arg @ref LL_DMA_CHANNEL_7
761 * @retval Returned value can be one of the following values:
762 * @arg @ref LL_DMA_MEMORY_INCREMENT
763 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
764 */
LL_DMA_GetMemoryIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)765 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
766 {
767 uint32_t dma_base_addr = (uint32_t)DMAx;
768 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
769 DMA_CCR_MINC));
770 }
771
772 /**
773 * @brief Set Peripheral size.
774 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
775 * @param DMAx DMAx Instance
776 * @param Channel This parameter can be one of the following values:
777 * @arg @ref LL_DMA_CHANNEL_1
778 * @arg @ref LL_DMA_CHANNEL_2
779 * @arg @ref LL_DMA_CHANNEL_3
780 * @arg @ref LL_DMA_CHANNEL_4
781 * @arg @ref LL_DMA_CHANNEL_5
782 * @arg @ref LL_DMA_CHANNEL_6
783 * @arg @ref LL_DMA_CHANNEL_7
784 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
785 * @arg @ref LL_DMA_PDATAALIGN_BYTE
786 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
787 * @arg @ref LL_DMA_PDATAALIGN_WORD
788 * @retval None
789 */
LL_DMA_SetPeriphSize(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)790 __STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
791 {
792 uint32_t dma_base_addr = (uint32_t)DMAx;
793 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
794 PeriphOrM2MSrcDataSize);
795 }
796
797 /**
798 * @brief Get Peripheral size.
799 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
800 * @param DMAx DMAx Instance
801 * @param Channel This parameter can be one of the following values:
802 * @arg @ref LL_DMA_CHANNEL_1
803 * @arg @ref LL_DMA_CHANNEL_2
804 * @arg @ref LL_DMA_CHANNEL_3
805 * @arg @ref LL_DMA_CHANNEL_4
806 * @arg @ref LL_DMA_CHANNEL_5
807 * @arg @ref LL_DMA_CHANNEL_6
808 * @arg @ref LL_DMA_CHANNEL_7
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_DMA_PDATAALIGN_BYTE
811 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
812 * @arg @ref LL_DMA_PDATAALIGN_WORD
813 */
LL_DMA_GetPeriphSize(const DMA_TypeDef * DMAx,uint32_t Channel)814 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel)
815 {
816 uint32_t dma_base_addr = (uint32_t)DMAx;
817 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
818 DMA_CCR_PSIZE));
819 }
820
821 /**
822 * @brief Set Memory size.
823 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
824 * @param DMAx DMAx Instance
825 * @param Channel This parameter can be one of the following values:
826 * @arg @ref LL_DMA_CHANNEL_1
827 * @arg @ref LL_DMA_CHANNEL_2
828 * @arg @ref LL_DMA_CHANNEL_3
829 * @arg @ref LL_DMA_CHANNEL_4
830 * @arg @ref LL_DMA_CHANNEL_5
831 * @arg @ref LL_DMA_CHANNEL_6
832 * @arg @ref LL_DMA_CHANNEL_7
833 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
834 * @arg @ref LL_DMA_MDATAALIGN_BYTE
835 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
836 * @arg @ref LL_DMA_MDATAALIGN_WORD
837 * @retval None
838 */
LL_DMA_SetMemorySize(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)839 __STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
840 {
841 uint32_t dma_base_addr = (uint32_t)DMAx;
842 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
843 MemoryOrM2MDstDataSize);
844 }
845
846 /**
847 * @brief Get Memory size.
848 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
849 * @param DMAx DMAx Instance
850 * @param Channel This parameter can be one of the following values:
851 * @arg @ref LL_DMA_CHANNEL_1
852 * @arg @ref LL_DMA_CHANNEL_2
853 * @arg @ref LL_DMA_CHANNEL_3
854 * @arg @ref LL_DMA_CHANNEL_4
855 * @arg @ref LL_DMA_CHANNEL_5
856 * @arg @ref LL_DMA_CHANNEL_6
857 * @arg @ref LL_DMA_CHANNEL_7
858 * @retval Returned value can be one of the following values:
859 * @arg @ref LL_DMA_MDATAALIGN_BYTE
860 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
861 * @arg @ref LL_DMA_MDATAALIGN_WORD
862 */
LL_DMA_GetMemorySize(const DMA_TypeDef * DMAx,uint32_t Channel)863 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel)
864 {
865 uint32_t dma_base_addr = (uint32_t)DMAx;
866 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
867 DMA_CCR_MSIZE));
868 }
869
870 /**
871 * @brief Set Channel priority level.
872 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
873 * @param DMAx DMAx Instance
874 * @param Channel This parameter can be one of the following values:
875 * @arg @ref LL_DMA_CHANNEL_1
876 * @arg @ref LL_DMA_CHANNEL_2
877 * @arg @ref LL_DMA_CHANNEL_3
878 * @arg @ref LL_DMA_CHANNEL_4
879 * @arg @ref LL_DMA_CHANNEL_5
880 * @arg @ref LL_DMA_CHANNEL_6
881 * @arg @ref LL_DMA_CHANNEL_7
882 * @param Priority This parameter can be one of the following values:
883 * @arg @ref LL_DMA_PRIORITY_LOW
884 * @arg @ref LL_DMA_PRIORITY_MEDIUM
885 * @arg @ref LL_DMA_PRIORITY_HIGH
886 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
887 * @retval None
888 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)889 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
890 {
891 uint32_t dma_base_addr = (uint32_t)DMAx;
892 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
893 Priority);
894 }
895
896 /**
897 * @brief Get Channel priority level.
898 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
899 * @param DMAx DMAx Instance
900 * @param Channel This parameter can be one of the following values:
901 * @arg @ref LL_DMA_CHANNEL_1
902 * @arg @ref LL_DMA_CHANNEL_2
903 * @arg @ref LL_DMA_CHANNEL_3
904 * @arg @ref LL_DMA_CHANNEL_4
905 * @arg @ref LL_DMA_CHANNEL_5
906 * @arg @ref LL_DMA_CHANNEL_6
907 * @arg @ref LL_DMA_CHANNEL_7
908 * @retval Returned value can be one of the following values:
909 * @arg @ref LL_DMA_PRIORITY_LOW
910 * @arg @ref LL_DMA_PRIORITY_MEDIUM
911 * @arg @ref LL_DMA_PRIORITY_HIGH
912 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
913 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)914 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
915 {
916 uint32_t dma_base_addr = (uint32_t)DMAx;
917 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
918 DMA_CCR_PL));
919 }
920
921 /**
922 * @brief Set Number of data to transfer.
923 * @note This action has no effect if
924 * channel is enabled.
925 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
926 * @param DMAx DMAx Instance
927 * @param Channel This parameter can be one of the following values:
928 * @arg @ref LL_DMA_CHANNEL_1
929 * @arg @ref LL_DMA_CHANNEL_2
930 * @arg @ref LL_DMA_CHANNEL_3
931 * @arg @ref LL_DMA_CHANNEL_4
932 * @arg @ref LL_DMA_CHANNEL_5
933 * @arg @ref LL_DMA_CHANNEL_6
934 * @arg @ref LL_DMA_CHANNEL_7
935 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
936 * @retval None
937 */
LL_DMA_SetDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)938 __STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
939 {
940 uint32_t dma_base_addr = (uint32_t)DMAx;
941 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
942 DMA_CNDTR_NDT, NbData);
943 }
944
945 /**
946 * @brief Get Number of data to transfer.
947 * @note Once the channel is enabled, the return value indicate the
948 * remaining bytes to be transmitted.
949 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
950 * @param DMAx DMAx Instance
951 * @param Channel This parameter can be one of the following values:
952 * @arg @ref LL_DMA_CHANNEL_1
953 * @arg @ref LL_DMA_CHANNEL_2
954 * @arg @ref LL_DMA_CHANNEL_3
955 * @arg @ref LL_DMA_CHANNEL_4
956 * @arg @ref LL_DMA_CHANNEL_5
957 * @arg @ref LL_DMA_CHANNEL_6
958 * @arg @ref LL_DMA_CHANNEL_7
959 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
960 */
LL_DMA_GetDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)961 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
962 {
963 uint32_t dma_base_addr = (uint32_t)DMAx;
964 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
965 DMA_CNDTR_NDT));
966 }
967
968 /**
969 * @brief Configure the Source and Destination addresses.
970 * @note This API must not be called when the DMA channel is enabled.
971 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
972 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
973 * CMAR MA LL_DMA_ConfigAddresses
974 * @param DMAx DMAx Instance
975 * @param Channel This parameter can be one of the following values:
976 * @arg @ref LL_DMA_CHANNEL_1
977 * @arg @ref LL_DMA_CHANNEL_2
978 * @arg @ref LL_DMA_CHANNEL_3
979 * @arg @ref LL_DMA_CHANNEL_4
980 * @arg @ref LL_DMA_CHANNEL_5
981 * @arg @ref LL_DMA_CHANNEL_6
982 * @arg @ref LL_DMA_CHANNEL_7
983 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
984 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
985 * @param Direction This parameter can be one of the following values:
986 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
987 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
988 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
989 * @retval None
990 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)991 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
992 uint32_t DstAddress, uint32_t Direction)
993 {
994 uint32_t dma_base_addr = (uint32_t)DMAx;
995 /* Direction Memory to Periph */
996 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
997 {
998 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
999 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1000 }
1001 /* Direction Periph to Memory and Memory to Memory */
1002 else
1003 {
1004 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1005 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
1006 }
1007 }
1008
1009 /**
1010 * @brief Set the Memory address.
1011 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1012 * @note This API must not be called when the DMA channel is enabled.
1013 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1014 * @param DMAx DMAx Instance
1015 * @param Channel This parameter can be one of the following values:
1016 * @arg @ref LL_DMA_CHANNEL_1
1017 * @arg @ref LL_DMA_CHANNEL_2
1018 * @arg @ref LL_DMA_CHANNEL_3
1019 * @arg @ref LL_DMA_CHANNEL_4
1020 * @arg @ref LL_DMA_CHANNEL_5
1021 * @arg @ref LL_DMA_CHANNEL_6
1022 * @arg @ref LL_DMA_CHANNEL_7
1023 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1024 * @retval None
1025 */
LL_DMA_SetMemoryAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1026 __STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1027 {
1028 uint32_t dma_base_addr = (uint32_t)DMAx;
1029 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1030 }
1031
1032 /**
1033 * @brief Set the Peripheral address.
1034 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1035 * @note This API must not be called when the DMA channel is enabled.
1036 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1037 * @param DMAx DMAx Instance
1038 * @param Channel This parameter can be one of the following values:
1039 * @arg @ref LL_DMA_CHANNEL_1
1040 * @arg @ref LL_DMA_CHANNEL_2
1041 * @arg @ref LL_DMA_CHANNEL_3
1042 * @arg @ref LL_DMA_CHANNEL_4
1043 * @arg @ref LL_DMA_CHANNEL_5
1044 * @arg @ref LL_DMA_CHANNEL_6
1045 * @arg @ref LL_DMA_CHANNEL_7
1046 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1047 * @retval None
1048 */
LL_DMA_SetPeriphAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1049 __STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1050 {
1051 uint32_t dma_base_addr = (uint32_t)DMAx;
1052 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1053 }
1054
1055 /**
1056 * @brief Get Memory address.
1057 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1058 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1059 * @param DMAx DMAx Instance
1060 * @param Channel This parameter can be one of the following values:
1061 * @arg @ref LL_DMA_CHANNEL_1
1062 * @arg @ref LL_DMA_CHANNEL_2
1063 * @arg @ref LL_DMA_CHANNEL_3
1064 * @arg @ref LL_DMA_CHANNEL_4
1065 * @arg @ref LL_DMA_CHANNEL_5
1066 * @arg @ref LL_DMA_CHANNEL_6
1067 * @arg @ref LL_DMA_CHANNEL_7
1068 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1069 */
LL_DMA_GetMemoryAddress(const DMA_TypeDef * DMAx,uint32_t Channel)1070 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
1071 {
1072 uint32_t dma_base_addr = (uint32_t)DMAx;
1073 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1074 }
1075
1076 /**
1077 * @brief Get Peripheral address.
1078 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1079 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1080 * @param DMAx DMAx Instance
1081 * @param Channel This parameter can be one of the following values:
1082 * @arg @ref LL_DMA_CHANNEL_1
1083 * @arg @ref LL_DMA_CHANNEL_2
1084 * @arg @ref LL_DMA_CHANNEL_3
1085 * @arg @ref LL_DMA_CHANNEL_4
1086 * @arg @ref LL_DMA_CHANNEL_5
1087 * @arg @ref LL_DMA_CHANNEL_6
1088 * @arg @ref LL_DMA_CHANNEL_7
1089 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1090 */
LL_DMA_GetPeriphAddress(const DMA_TypeDef * DMAx,uint32_t Channel)1091 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
1092 {
1093 uint32_t dma_base_addr = (uint32_t)DMAx;
1094 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1095 }
1096
1097 /**
1098 * @brief Set the Memory to Memory Source address.
1099 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1100 * @note This API must not be called when the DMA channel is enabled.
1101 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1102 * @param DMAx DMAx Instance
1103 * @param Channel This parameter can be one of the following values:
1104 * @arg @ref LL_DMA_CHANNEL_1
1105 * @arg @ref LL_DMA_CHANNEL_2
1106 * @arg @ref LL_DMA_CHANNEL_3
1107 * @arg @ref LL_DMA_CHANNEL_4
1108 * @arg @ref LL_DMA_CHANNEL_5
1109 * @arg @ref LL_DMA_CHANNEL_6
1110 * @arg @ref LL_DMA_CHANNEL_7
1111 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1112 * @retval None
1113 */
LL_DMA_SetM2MSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1114 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1115 {
1116 uint32_t dma_base_addr = (uint32_t)DMAx;
1117 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1118 }
1119
1120 /**
1121 * @brief Set the Memory to Memory Destination address.
1122 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1123 * @note This API must not be called when the DMA channel is enabled.
1124 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1125 * @param DMAx DMAx Instance
1126 * @param Channel This parameter can be one of the following values:
1127 * @arg @ref LL_DMA_CHANNEL_1
1128 * @arg @ref LL_DMA_CHANNEL_2
1129 * @arg @ref LL_DMA_CHANNEL_3
1130 * @arg @ref LL_DMA_CHANNEL_4
1131 * @arg @ref LL_DMA_CHANNEL_5
1132 * @arg @ref LL_DMA_CHANNEL_6
1133 * @arg @ref LL_DMA_CHANNEL_7
1134 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1135 * @retval None
1136 */
LL_DMA_SetM2MDstAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1137 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1138 {
1139 uint32_t dma_base_addr = (uint32_t)DMAx;
1140 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1141 }
1142
1143 /**
1144 * @brief Get the Memory to Memory Source address.
1145 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1146 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1147 * @param DMAx DMAx Instance
1148 * @param Channel This parameter can be one of the following values:
1149 * @arg @ref LL_DMA_CHANNEL_1
1150 * @arg @ref LL_DMA_CHANNEL_2
1151 * @arg @ref LL_DMA_CHANNEL_3
1152 * @arg @ref LL_DMA_CHANNEL_4
1153 * @arg @ref LL_DMA_CHANNEL_5
1154 * @arg @ref LL_DMA_CHANNEL_6
1155 * @arg @ref LL_DMA_CHANNEL_7
1156 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1157 */
LL_DMA_GetM2MSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)1158 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
1159 {
1160 uint32_t dma_base_addr = (uint32_t)DMAx;
1161 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1162 }
1163
1164 /**
1165 * @brief Get the Memory to Memory Destination address.
1166 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1167 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1168 * @param DMAx DMAx Instance
1169 * @param Channel This parameter can be one of the following values:
1170 * @arg @ref LL_DMA_CHANNEL_1
1171 * @arg @ref LL_DMA_CHANNEL_2
1172 * @arg @ref LL_DMA_CHANNEL_3
1173 * @arg @ref LL_DMA_CHANNEL_4
1174 * @arg @ref LL_DMA_CHANNEL_5
1175 * @arg @ref LL_DMA_CHANNEL_6
1176 * @arg @ref LL_DMA_CHANNEL_7
1177 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1178 */
LL_DMA_GetM2MDstAddress(const DMA_TypeDef * DMAx,uint32_t Channel)1179 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
1180 {
1181 uint32_t dma_base_addr = (uint32_t)DMAx;
1182 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1183 }
1184
1185 /**
1186 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1187 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1188 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
1189 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1190 * @param DMAx DMAx Instance
1191 * @param Channel This parameter can be one of the following values:
1192 * @arg @ref LL_DMA_CHANNEL_1
1193 * @arg @ref LL_DMA_CHANNEL_2
1194 * @arg @ref LL_DMA_CHANNEL_3
1195 * @arg @ref LL_DMA_CHANNEL_4
1196 * @arg @ref LL_DMA_CHANNEL_5
1197 * @arg @ref LL_DMA_CHANNEL_6
1198 * @arg @ref LL_DMA_CHANNEL_7
1199 * @param Request This parameter can be one of the following values:
1200 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1201 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1202 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1203 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1204 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1205 * @arg @ref LL_DMAMUX_REQ_ADC
1206 * @arg @ref LL_DMAMUX_REQ_AES_IN
1207 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1208 * @arg @ref LL_DMAMUX_REQ_DAC_CH1
1209 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1210 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1211 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1212 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1213 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1214 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1215 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1216 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1217 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC1
1218 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC2
1219 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC3
1220 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC4
1221 * @arg @ref LL_DMAMUX_REQ_LPTIM1_UE
1222 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC1
1223 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC2
1224 * @arg @ref LL_DMAMUX_REQ_LPTIM2_UE
1225 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC1
1226 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC2
1227 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC3
1228 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC4
1229 * @arg @ref LL_DMAMUX_REQ_LPTIM3_UE
1230 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1231 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1232 * @arg @ref LL_DMAMUX_REQ_LPUART2_RX
1233 * @arg @ref LL_DMAMUX_REQ_LPUART2_TX
1234 * @arg @ref LL_DMAMUX_REQ_LPUART3_RX
1235 * @arg @ref LL_DMAMUX_REQ_LPUART3_TX
1236 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1237 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1238 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1239 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1240 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1241 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1242 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1243 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1244 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1245 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1246 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1247 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1248 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1249 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1250 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1251 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1252 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
1253 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1254 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1255 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1256 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1257 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1258 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1259 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1260 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1261 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1262 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1263 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
1264 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
1265 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1266 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1267 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
1268 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1269 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1270 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1271 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1272 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1273 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1274 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1275 * @arg @ref LL_DMAMUX_REQ_USART4_RX
1276 * @arg @ref LL_DMAMUX_REQ_USART4_TX
1277
1278 * @retval None
1279 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1280 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1281 {
1282 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1283 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1284 }
1285
1286 /**
1287 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1288 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1289 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (** only available on chip which support DMA2 **).
1290 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1291 * @param DMAx DMAx Instance
1292 * @param Channel This parameter can be one of the following values:
1293 * @arg @ref LL_DMA_CHANNEL_1
1294 * @arg @ref LL_DMA_CHANNEL_2
1295 * @arg @ref LL_DMA_CHANNEL_3
1296 * @arg @ref LL_DMA_CHANNEL_4
1297 * @arg @ref LL_DMA_CHANNEL_5
1298 * @arg @ref LL_DMA_CHANNEL_6
1299 * @arg @ref LL_DMA_CHANNEL_7
1300 * @retval Returned value can be one of the following values:
1301 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1302 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1303 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1304 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1305 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1306 * @arg @ref LL_DMAMUX_REQ_ADC
1307 * @arg @ref LL_DMAMUX_REQ_AES_IN
1308 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1309 * @arg @ref LL_DMAMUX_REQ_DAC_CH1
1310 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1311 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1312 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1313 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1314 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1315 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1316 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1317 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1318 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC1
1319 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC2
1320 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC3
1321 * @arg @ref LL_DMAMUX_REQ_LPTIM1_IC4
1322 * @arg @ref LL_DMAMUX_REQ_LPTIM1_UE
1323 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC1
1324 * @arg @ref LL_DMAMUX_REQ_LPTIM2_IC2
1325 * @arg @ref LL_DMAMUX_REQ_LPTIM2_UE
1326 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC1
1327 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC2
1328 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC3
1329 * @arg @ref LL_DMAMUX_REQ_LPTIM3_IC4
1330 * @arg @ref LL_DMAMUX_REQ_LPTIM3_UE
1331 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1332 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1333 * @arg @ref LL_DMAMUX_REQ_LPUART2_RX
1334 * @arg @ref LL_DMAMUX_REQ_LPUART2_TX
1335 * @arg @ref LL_DMAMUX_REQ_LPUART3_RX
1336 * @arg @ref LL_DMAMUX_REQ_LPUART3_TX
1337 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1338 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1339 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1340 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1341 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1342 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1343 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1344 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1345 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1346 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1347 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1348 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1349 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1350 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1351 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1352 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1353 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
1354 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1355 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1356 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1357 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1358 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1359 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1360 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1361 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1362 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1363 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1364 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
1365 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
1366 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1367 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1368 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
1369 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1370 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1371 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1372 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1373 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1374 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1375 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1376 * @arg @ref LL_DMAMUX_REQ_USART4_RX
1377 * @arg @ref LL_DMAMUX_REQ_USART4_TX
1378 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)1379 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
1380 {
1381 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1382 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1383 }
1384
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1390 * @{
1391 */
1392
1393 /**
1394 * @brief Get Channel 1 global interrupt flag.
1395 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1396 * @param DMAx DMAx Instance
1397 * @retval State of bit (1 or 0).
1398 */
LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef * DMAx)1399 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx)
1400 {
1401 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1402 }
1403
1404 /**
1405 * @brief Get Channel 2 global interrupt flag.
1406 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1407 * @param DMAx DMAx Instance
1408 * @retval State of bit (1 or 0).
1409 */
LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef * DMAx)1410 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx)
1411 {
1412 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Get Channel 3 global interrupt flag.
1417 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1418 * @param DMAx DMAx Instance
1419 * @retval State of bit (1 or 0).
1420 */
LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef * DMAx)1421 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx)
1422 {
1423 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1424 }
1425
1426 /**
1427 * @brief Get Channel 4 global interrupt flag.
1428 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1429 * @param DMAx DMAx Instance
1430 * @retval State of bit (1 or 0).
1431 */
LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef * DMAx)1432 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx)
1433 {
1434 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1435 }
1436
1437 /**
1438 * @brief Get Channel 5 global interrupt flag.
1439 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1440 * @param DMAx DMAx Instance
1441 * @retval State of bit (1 or 0).
1442 */
LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef * DMAx)1443 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx)
1444 {
1445 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1446 }
1447
1448 /**
1449 * @brief Get Channel 6 global interrupt flag.
1450 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1451 * @param DMAx DMAx Instance
1452 * @retval State of bit (1 or 0).
1453 */
LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef * DMAx)1454 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx)
1455 {
1456 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1457 }
1458
1459 /**
1460 * @brief Get Channel 7 global interrupt flag.
1461 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1462 * @param DMAx DMAx Instance
1463 * @retval State of bit (1 or 0).
1464 */
LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef * DMAx)1465 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx)
1466 {
1467 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1468 }
1469
1470 /**
1471 * @brief Get Channel 1 transfer complete flag.
1472 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1473 * @param DMAx DMAx Instance
1474 * @retval State of bit (1 or 0).
1475 */
LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef * DMAx)1476 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx)
1477 {
1478 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1479 }
1480
1481 /**
1482 * @brief Get Channel 2 transfer complete flag.
1483 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1484 * @param DMAx DMAx Instance
1485 * @retval State of bit (1 or 0).
1486 */
LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef * DMAx)1487 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx)
1488 {
1489 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1490 }
1491
1492 /**
1493 * @brief Get Channel 3 transfer complete flag.
1494 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1495 * @param DMAx DMAx Instance
1496 * @retval State of bit (1 or 0).
1497 */
LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef * DMAx)1498 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx)
1499 {
1500 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1501 }
1502
1503 /**
1504 * @brief Get Channel 4 transfer complete flag.
1505 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1506 * @param DMAx DMAx Instance
1507 * @retval State of bit (1 or 0).
1508 */
LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef * DMAx)1509 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx)
1510 {
1511 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1512 }
1513
1514 /**
1515 * @brief Get Channel 5 transfer complete flag.
1516 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1517 * @param DMAx DMAx Instance
1518 * @retval State of bit (1 or 0).
1519 */
LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef * DMAx)1520 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx)
1521 {
1522 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1523 }
1524
1525 /**
1526 * @brief Get Channel 6 transfer complete flag.
1527 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1528 * @param DMAx DMAx Instance
1529 * @retval State of bit (1 or 0).
1530 */
LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef * DMAx)1531 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx)
1532 {
1533 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1534 }
1535
1536 /**
1537 * @brief Get Channel 7 transfer complete flag.
1538 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1539 * @param DMAx DMAx Instance
1540 * @retval State of bit (1 or 0).
1541 */
LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef * DMAx)1542 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx)
1543 {
1544 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Get Channel 1 half transfer flag.
1549 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1550 * @param DMAx DMAx Instance
1551 * @retval State of bit (1 or 0).
1552 */
LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef * DMAx)1553 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx)
1554 {
1555 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1556 }
1557
1558 /**
1559 * @brief Get Channel 2 half transfer flag.
1560 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1561 * @param DMAx DMAx Instance
1562 * @retval State of bit (1 or 0).
1563 */
LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef * DMAx)1564 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx)
1565 {
1566 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1567 }
1568
1569 /**
1570 * @brief Get Channel 3 half transfer flag.
1571 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1572 * @param DMAx DMAx Instance
1573 * @retval State of bit (1 or 0).
1574 */
LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef * DMAx)1575 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx)
1576 {
1577 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1578 }
1579
1580 /**
1581 * @brief Get Channel 4 half transfer flag.
1582 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1583 * @param DMAx DMAx Instance
1584 * @retval State of bit (1 or 0).
1585 */
LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef * DMAx)1586 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx)
1587 {
1588 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1589 }
1590
1591 /**
1592 * @brief Get Channel 5 half transfer flag.
1593 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1594 * @param DMAx DMAx Instance
1595 * @retval State of bit (1 or 0).
1596 */
LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef * DMAx)1597 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx)
1598 {
1599 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1600 }
1601
1602 /**
1603 * @brief Get Channel 6 half transfer flag.
1604 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1605 * @param DMAx DMAx Instance
1606 * @retval State of bit (1 or 0).
1607 */
LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef * DMAx)1608 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx)
1609 {
1610 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1611 }
1612
1613 /**
1614 * @brief Get Channel 7 half transfer flag.
1615 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1616 * @param DMAx DMAx Instance
1617 * @retval State of bit (1 or 0).
1618 */
LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef * DMAx)1619 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx)
1620 {
1621 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1622 }
1623
1624 /**
1625 * @brief Get Channel 1 transfer error flag.
1626 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1627 * @param DMAx DMAx Instance
1628 * @retval State of bit (1 or 0).
1629 */
LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef * DMAx)1630 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx)
1631 {
1632 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1633 }
1634
1635 /**
1636 * @brief Get Channel 2 transfer error flag.
1637 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1638 * @param DMAx DMAx Instance
1639 * @retval State of bit (1 or 0).
1640 */
LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef * DMAx)1641 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx)
1642 {
1643 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1644 }
1645
1646 /**
1647 * @brief Get Channel 3 transfer error flag.
1648 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1649 * @param DMAx DMAx Instance
1650 * @retval State of bit (1 or 0).
1651 */
LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef * DMAx)1652 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx)
1653 {
1654 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1655 }
1656
1657 /**
1658 * @brief Get Channel 4 transfer error flag.
1659 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1660 * @param DMAx DMAx Instance
1661 * @retval State of bit (1 or 0).
1662 */
LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef * DMAx)1663 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx)
1664 {
1665 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1666 }
1667
1668 /**
1669 * @brief Get Channel 5 transfer error flag.
1670 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1671 * @param DMAx DMAx Instance
1672 * @retval State of bit (1 or 0).
1673 */
LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef * DMAx)1674 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx)
1675 {
1676 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1677 }
1678
1679 /**
1680 * @brief Get Channel 6 transfer error flag.
1681 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1682 * @param DMAx DMAx Instance
1683 * @retval State of bit (1 or 0).
1684 */
LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef * DMAx)1685 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx)
1686 {
1687 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1688 }
1689
1690 /**
1691 * @brief Get Channel 7 transfer error flag.
1692 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1693 * @param DMAx DMAx Instance
1694 * @retval State of bit (1 or 0).
1695 */
LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef * DMAx)1696 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx)
1697 {
1698 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1699 }
1700
1701 /**
1702 * @brief Clear Channel 1 global interrupt flag.
1703 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1704 Instead clear specific flags transfer complete, half transfer & transfer
1705 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1706 LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
1707 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1708 * @param DMAx DMAx Instance
1709 * @retval None
1710 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1711 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1712 {
1713 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1714 }
1715
1716 /**
1717 * @brief Clear Channel 2 global interrupt flag.
1718 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1719 Instead clear specific flags transfer complete, half transfer & transfer
1720 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1721 LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
1722 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1723 * @param DMAx DMAx Instance
1724 * @retval None
1725 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1726 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1727 {
1728 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1729 }
1730
1731 /**
1732 * @brief Clear Channel 3 global interrupt flag.
1733 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1734 Instead clear specific flags transfer complete, half transfer & transfer
1735 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1736 LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
1737 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1738 * @param DMAx DMAx Instance
1739 * @retval None
1740 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1741 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1742 {
1743 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1744 }
1745
1746 /**
1747 * @brief Clear Channel 4 global interrupt flag.
1748 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1749 Instead clear specific flags transfer complete, half transfer & transfer
1750 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1751 LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
1752 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1753 * @param DMAx DMAx Instance
1754 * @retval None
1755 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1756 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1757 {
1758 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1759 }
1760
1761 /**
1762 * @brief Clear Channel 5 global interrupt flag.
1763 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1764 Instead clear specific flags transfer complete, half transfer & transfer
1765 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1766 LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
1767 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1768 * @param DMAx DMAx Instance
1769 * @retval None
1770 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1771 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1772 {
1773 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1774 }
1775
1776 /**
1777 * @brief Clear Channel 6 global interrupt flag.
1778 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1779 Instead clear specific flags transfer complete, half transfer & transfer
1780 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1781 LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
1782 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1783 * @param DMAx DMAx Instance
1784 * @retval None
1785 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1786 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1787 {
1788 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1789 }
1790
1791 /**
1792 * @brief Clear Channel 7 global interrupt flag.
1793 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1794 Instead clear specific flags transfer complete, half transfer & transfer
1795 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1796 LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
1797 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1798 * @param DMAx DMAx Instance
1799 * @retval None
1800 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1801 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1802 {
1803 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1804 }
1805
1806 /**
1807 * @brief Clear Channel 1 transfer complete flag.
1808 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1809 * @param DMAx DMAx Instance
1810 * @retval None
1811 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1812 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1813 {
1814 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1815 }
1816
1817 /**
1818 * @brief Clear Channel 2 transfer complete flag.
1819 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1820 * @param DMAx DMAx Instance
1821 * @retval None
1822 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1823 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1824 {
1825 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1826 }
1827
1828 /**
1829 * @brief Clear Channel 3 transfer complete flag.
1830 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1831 * @param DMAx DMAx Instance
1832 * @retval None
1833 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1834 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1835 {
1836 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1837 }
1838
1839 /**
1840 * @brief Clear Channel 4 transfer complete flag.
1841 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1842 * @param DMAx DMAx Instance
1843 * @retval None
1844 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1845 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1846 {
1847 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1848 }
1849
1850 /**
1851 * @brief Clear Channel 5 transfer complete flag.
1852 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1853 * @param DMAx DMAx Instance
1854 * @retval None
1855 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1856 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1857 {
1858 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1859 }
1860
1861 /**
1862 * @brief Clear Channel 6 transfer complete flag.
1863 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1864 * @param DMAx DMAx Instance
1865 * @retval None
1866 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1867 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1868 {
1869 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1870 }
1871
1872 /**
1873 * @brief Clear Channel 7 transfer complete flag.
1874 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1875 * @param DMAx DMAx Instance
1876 * @retval None
1877 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1878 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1879 {
1880 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1881 }
1882
1883 /**
1884 * @brief Clear Channel 1 half transfer flag.
1885 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1886 * @param DMAx DMAx Instance
1887 * @retval None
1888 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1889 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1890 {
1891 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1892 }
1893
1894 /**
1895 * @brief Clear Channel 2 half transfer flag.
1896 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1897 * @param DMAx DMAx Instance
1898 * @retval None
1899 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1900 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1901 {
1902 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1903 }
1904
1905 /**
1906 * @brief Clear Channel 3 half transfer flag.
1907 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1908 * @param DMAx DMAx Instance
1909 * @retval None
1910 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1911 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1912 {
1913 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1914 }
1915
1916 /**
1917 * @brief Clear Channel 4 half transfer flag.
1918 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1919 * @param DMAx DMAx Instance
1920 * @retval None
1921 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1922 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1923 {
1924 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1925 }
1926
1927 /**
1928 * @brief Clear Channel 5 half transfer flag.
1929 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1930 * @param DMAx DMAx Instance
1931 * @retval None
1932 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1933 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1934 {
1935 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1936 }
1937
1938 /**
1939 * @brief Clear Channel 6 half transfer flag.
1940 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1941 * @param DMAx DMAx Instance
1942 * @retval None
1943 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1944 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1945 {
1946 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1947 }
1948
1949 /**
1950 * @brief Clear Channel 7 half transfer flag.
1951 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1952 * @param DMAx DMAx Instance
1953 * @retval None
1954 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1955 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1956 {
1957 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1958 }
1959
1960 /**
1961 * @brief Clear Channel 1 transfer error flag.
1962 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1963 * @param DMAx DMAx Instance
1964 * @retval None
1965 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1966 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1967 {
1968 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1969 }
1970
1971 /**
1972 * @brief Clear Channel 2 transfer error flag.
1973 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1974 * @param DMAx DMAx Instance
1975 * @retval None
1976 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1977 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1978 {
1979 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1980 }
1981
1982 /**
1983 * @brief Clear Channel 3 transfer error flag.
1984 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1985 * @param DMAx DMAx Instance
1986 * @retval None
1987 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1988 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1989 {
1990 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1991 }
1992
1993 /**
1994 * @brief Clear Channel 4 transfer error flag.
1995 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1996 * @param DMAx DMAx Instance
1997 * @retval None
1998 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1999 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2000 {
2001 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2002 }
2003
2004 /**
2005 * @brief Clear Channel 5 transfer error flag.
2006 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2007 * @param DMAx DMAx Instance
2008 * @retval None
2009 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2010 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2011 {
2012 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2013 }
2014
2015 /**
2016 * @brief Clear Channel 6 transfer error flag.
2017 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2018 * @param DMAx DMAx Instance
2019 * @retval None
2020 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2021 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2022 {
2023 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2024 }
2025
2026 /**
2027 * @brief Clear Channel 7 transfer error flag.
2028 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2029 * @param DMAx DMAx Instance
2030 * @retval None
2031 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2032 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2033 {
2034 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2035 }
2036
2037 /**
2038 * @}
2039 */
2040
2041 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2042 * @{
2043 */
2044 /**
2045 * @brief Enable Transfer complete interrupt.
2046 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2047 * @param DMAx DMAx Instance
2048 * @param Channel This parameter can be one of the following values:
2049 * @arg @ref LL_DMA_CHANNEL_1
2050 * @arg @ref LL_DMA_CHANNEL_2
2051 * @arg @ref LL_DMA_CHANNEL_3
2052 * @arg @ref LL_DMA_CHANNEL_4
2053 * @arg @ref LL_DMA_CHANNEL_5
2054 * @arg @ref LL_DMA_CHANNEL_6
2055 * @arg @ref LL_DMA_CHANNEL_7
2056 * @retval None
2057 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2058 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2059 {
2060 uint32_t dma_base_addr = (uint32_t)DMAx;
2061 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2062 }
2063
2064 /**
2065 * @brief Enable Half transfer interrupt.
2066 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2067 * @param DMAx DMAx Instance
2068 * @param Channel This parameter can be one of the following values:
2069 * @arg @ref LL_DMA_CHANNEL_1
2070 * @arg @ref LL_DMA_CHANNEL_2
2071 * @arg @ref LL_DMA_CHANNEL_3
2072 * @arg @ref LL_DMA_CHANNEL_4
2073 * @arg @ref LL_DMA_CHANNEL_5
2074 * @arg @ref LL_DMA_CHANNEL_6
2075 * @arg @ref LL_DMA_CHANNEL_7
2076 * @retval None
2077 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)2078 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
2079 {
2080 uint32_t dma_base_addr = (uint32_t)DMAx;
2081 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2082 }
2083
2084 /**
2085 * @brief Enable Transfer error interrupt.
2086 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2087 * @param DMAx DMAx Instance
2088 * @param Channel This parameter can be one of the following values:
2089 * @arg @ref LL_DMA_CHANNEL_1
2090 * @arg @ref LL_DMA_CHANNEL_2
2091 * @arg @ref LL_DMA_CHANNEL_3
2092 * @arg @ref LL_DMA_CHANNEL_4
2093 * @arg @ref LL_DMA_CHANNEL_5
2094 * @arg @ref LL_DMA_CHANNEL_6
2095 * @arg @ref LL_DMA_CHANNEL_7
2096 * @retval None
2097 */
LL_DMA_EnableIT_TE(const DMA_TypeDef * DMAx,uint32_t Channel)2098 __STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel)
2099 {
2100 uint32_t dma_base_addr = (uint32_t)DMAx;
2101 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2102 }
2103
2104 /**
2105 * @brief Disable Transfer complete interrupt.
2106 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2107 * @param DMAx DMAx Instance
2108 * @param Channel This parameter can be one of the following values:
2109 * @arg @ref LL_DMA_CHANNEL_1
2110 * @arg @ref LL_DMA_CHANNEL_2
2111 * @arg @ref LL_DMA_CHANNEL_3
2112 * @arg @ref LL_DMA_CHANNEL_4
2113 * @arg @ref LL_DMA_CHANNEL_5
2114 * @arg @ref LL_DMA_CHANNEL_6
2115 * @arg @ref LL_DMA_CHANNEL_7
2116 * @retval None
2117 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)2118 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
2119 {
2120 uint32_t dma_base_addr = (uint32_t)DMAx;
2121 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2122 }
2123
2124 /**
2125 * @brief Disable Half transfer interrupt.
2126 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2127 * @param DMAx DMAx Instance
2128 * @param Channel This parameter can be one of the following values:
2129 * @arg @ref LL_DMA_CHANNEL_1
2130 * @arg @ref LL_DMA_CHANNEL_2
2131 * @arg @ref LL_DMA_CHANNEL_3
2132 * @arg @ref LL_DMA_CHANNEL_4
2133 * @arg @ref LL_DMA_CHANNEL_5
2134 * @arg @ref LL_DMA_CHANNEL_6
2135 * @arg @ref LL_DMA_CHANNEL_7
2136 * @retval None
2137 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)2138 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
2139 {
2140 uint32_t dma_base_addr = (uint32_t)DMAx;
2141 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2142 }
2143
2144 /**
2145 * @brief Disable Transfer error interrupt.
2146 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2147 * @param DMAx DMAx Instance
2148 * @param Channel This parameter can be one of the following values:
2149 * @arg @ref LL_DMA_CHANNEL_1
2150 * @arg @ref LL_DMA_CHANNEL_2
2151 * @arg @ref LL_DMA_CHANNEL_3
2152 * @arg @ref LL_DMA_CHANNEL_4
2153 * @arg @ref LL_DMA_CHANNEL_5
2154 * @arg @ref LL_DMA_CHANNEL_6
2155 * @arg @ref LL_DMA_CHANNEL_7
2156 * @retval None
2157 */
LL_DMA_DisableIT_TE(const DMA_TypeDef * DMAx,uint32_t Channel)2158 __STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel)
2159 {
2160 uint32_t dma_base_addr = (uint32_t)DMAx;
2161 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2162 }
2163
2164 /**
2165 * @brief Check if Transfer complete Interrupt is enabled.
2166 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2167 * @param DMAx DMAx Instance
2168 * @param Channel This parameter can be one of the following values:
2169 * @arg @ref LL_DMA_CHANNEL_1
2170 * @arg @ref LL_DMA_CHANNEL_2
2171 * @arg @ref LL_DMA_CHANNEL_3
2172 * @arg @ref LL_DMA_CHANNEL_4
2173 * @arg @ref LL_DMA_CHANNEL_5
2174 * @arg @ref LL_DMA_CHANNEL_6
2175 * @arg @ref LL_DMA_CHANNEL_7
2176 * @retval State of bit (1 or 0).
2177 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)2178 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
2179 {
2180 uint32_t dma_base_addr = (uint32_t)DMAx;
2181 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2182 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2183 }
2184
2185 /**
2186 * @brief Check if Half transfer Interrupt is enabled.
2187 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2188 * @param DMAx DMAx Instance
2189 * @param Channel This parameter can be one of the following values:
2190 * @arg @ref LL_DMA_CHANNEL_1
2191 * @arg @ref LL_DMA_CHANNEL_2
2192 * @arg @ref LL_DMA_CHANNEL_3
2193 * @arg @ref LL_DMA_CHANNEL_4
2194 * @arg @ref LL_DMA_CHANNEL_5
2195 * @arg @ref LL_DMA_CHANNEL_6
2196 * @arg @ref LL_DMA_CHANNEL_7
2197 * @retval State of bit (1 or 0).
2198 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)2199 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
2200 {
2201 uint32_t dma_base_addr = (uint32_t)DMAx;
2202 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2203 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2204 }
2205
2206 /**
2207 * @brief Check if Transfer error Interrupt is enabled.
2208 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2209 * @param DMAx DMAx Instance
2210 * @param Channel This parameter can be one of the following values:
2211 * @arg @ref LL_DMA_CHANNEL_1
2212 * @arg @ref LL_DMA_CHANNEL_2
2213 * @arg @ref LL_DMA_CHANNEL_3
2214 * @arg @ref LL_DMA_CHANNEL_4
2215 * @arg @ref LL_DMA_CHANNEL_5
2216 * @arg @ref LL_DMA_CHANNEL_6
2217 * @arg @ref LL_DMA_CHANNEL_7
2218 * @retval State of bit (1 or 0).
2219 */
LL_DMA_IsEnabledIT_TE(const DMA_TypeDef * DMAx,uint32_t Channel)2220 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel)
2221 {
2222 uint32_t dma_base_addr = (uint32_t)DMAx;
2223 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2224 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2225 }
2226
2227 /**
2228 * @}
2229 */
2230
2231 #if defined(USE_FULL_LL_DRIVER)
2232 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2233 * @{
2234 */
2235 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2236 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2237 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2238
2239 /**
2240 * @}
2241 */
2242 #endif /* USE_FULL_LL_DRIVER */
2243
2244 /**
2245 * @}
2246 */
2247
2248 /**
2249 * @}
2250 */
2251
2252 #endif /* DMA1 || DMA2 */
2253
2254 /**
2255 * @}
2256 */
2257
2258 #ifdef __cplusplus
2259 }
2260 #endif
2261
2262 #endif /* STM32U0xx_LL_DMA_H */
2263
