1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_DAC_H
21 #define STM32U0xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
58
59 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
60 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
61
62 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
63 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
64 DHR12Rx channel 1 (shifted left of 20 bits) */
65 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
66 DHR12Rx channel 1 (shifted left of 24 bits) */
67 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
68 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
69 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
70 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
71 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
72
73 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
74 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
75 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
76 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET)
77
78
79 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
80 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
81 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
82 to position 0 */
83 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
84 to position 0 */
85
86 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
87 channel 1 or 2 versus DHR12Rx channel 1
88 (shifted left of 28 bits) */
89 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
90 channel 1 or 2 versus DHR12Rx channel 1
91 (shifted left of 20 bits) */
92 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
93 channel 1 or 2 versus DHR12Rx channel 1
94 (shifted left of 24 bits) */
95 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
96 channel 1 or 2 versus DORx channel 1
97 (shifted left of 5 bits) */
98 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
99 channel 1 or 2 versus SHSRx channel 1
100 (shifted left of 6 bits) */
101
102 /* Miscellaneous data */
103 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
104 bits (voltage range determined by analog voltage
105 references Vref+ and Vref-, refer to reference manual) */
106
107 /**
108 * @}
109 */
110
111
112 /* Private macros ------------------------------------------------------------*/
113 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
114 * @{
115 */
116
117 /**
118 * @brief Driver macro reserved for internal use: set a pointer to
119 * a register from a register basis from which an offset
120 * is applied.
121 * @param __REG__ Register basis from which the offset is applied.
122 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
123 * @retval Pointer to register address
124 */
125 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
126 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
127
128 /**
129 * @}
130 */
131
132
133 /* Exported types ------------------------------------------------------------*/
134 #if defined(USE_FULL_LL_DRIVER)
135 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
136 * @{
137 */
138
139 /**
140 * @brief Structure definition of some features of DAC instance.
141 */
142 typedef struct
143 {
144 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
145 internal (SW start) or from external peripheral
146 (timer event, external interrupt line).
147 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
148
149 This feature can be modified afterwards using unitary
150 function @ref LL_DAC_SetTriggerSource(). */
151
152 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
153 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
154
155 This feature can be modified afterwards using unitary
156 function @ref LL_DAC_SetWaveAutoGeneration(). */
157
158 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
159 If waveform automatic generation mode is set to noise, this parameter
160 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
161 If waveform automatic generation mode is set to triangle,
162 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
163 @note If waveform automatic generation mode is disabled,
164 this parameter is discarded.
165
166 This feature can be modified afterwards using unitary
167 function @ref LL_DAC_SetWaveNoiseLFSR(),
168 @ref LL_DAC_SetWaveTriangleAmplitude()
169 depending on the wave automatic generation selected. */
170
171 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
172 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
173
174 This feature can be modified afterwards using unitary
175 function @ref LL_DAC_SetOutputBuffer(). */
176
177 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
178 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
179
180 This feature can be modified afterwards using unitary
181 function @ref LL_DAC_SetOutputConnection(). */
182
183 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
184 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
185
186 This feature can be modified afterwards using unitary
187 function @ref LL_DAC_SetOutputMode(). */
188 } LL_DAC_InitTypeDef;
189
190 /**
191 * @}
192 */
193 #endif /* USE_FULL_LL_DRIVER */
194
195 /* Exported constants --------------------------------------------------------*/
196 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
197 * @{
198 */
199
200 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
201 * @brief Flags defines which can be used with LL_DAC_ReadReg function
202 * @{
203 */
204 /* DAC channel 1 flags */
205 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
206 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
207 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
208 /**
209 * @}
210 */
211
212 /** @defgroup DAC_LL_EC_IT DAC interruptions
213 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
214 * @{
215 */
216 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
217 /**
218 * @}
219 */
220
221 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
222 * @{
223 */
224 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
225 /**
226 * @}
227 */
228
229 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
230 * @{
231 */
232 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
233 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
234 /**
235 * @}
236 */
237
238 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
239 * @{
240 */
241 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC channel conversion trigger internal (SW start) */
242 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
244 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
245 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
246 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
247 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
248 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
249 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
250 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
251 /**
252 * @}
253 */
254
255 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
256 * @{
257 */
258 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
259 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
260 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
261 /**
262 * @}
263 */
264
265 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
266 * @{
267 */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
280 /**
281 * @}
282 */
283
284 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
285 * @{
286 */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
295 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
298 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
299 /**
300 * @}
301 */
302
303 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
304 * @{
305 */
306 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
307 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
308 /**
309 * @}
310 */
311
312 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
313 * @{
314 */
315 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
316 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
317 /**
318 * @}
319 */
320
321 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
322 * @{
323 */
324 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
325 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
326 /**
327 * @}
328 */
329
330 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
331 * @{
332 */
333 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
334 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
335 /**
336 * @}
337 */
338
339 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
340 * @{
341 */
342 /* List of DAC registers intended to be used (most commonly) with */
343 /* DMA transfer. */
344 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
345 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
346 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
347 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
348 /**
349 * @}
350 */
351
352 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
353 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
354 * not timeout values.
355 * For details on delays values, refer to descriptions in source code
356 * above each literal definition.
357 * @{
358 */
359
360 /* Delay for DAC channel voltage settling time from DAC channel startup */
361 /* (transition from disable to enable). */
362 /* Note: DAC channel startup time depends on board application environment: */
363 /* impedance connected to DAC channel output. */
364 /* The delay below is specified under conditions: */
365 /* - voltage maximum transition (lowest to highest value) */
366 /* - until voltage reaches final value +-1LSB */
367 /* - DAC channel output buffer enabled */
368 /* - load impedance of 5kOhm (min), 50pF (max) */
369 /* Literal set to maximum value (refer to device datasheet, */
370 /* parameter "tWAKEUP"). */
371 /* Unit: us */
372 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
373
374 /* Delay for DAC channel voltage settling time. */
375 /* Note: DAC channel startup time depends on board application environment: */
376 /* impedance connected to DAC channel output. */
377 /* The delay below is specified under conditions: */
378 /* - voltage maximum transition (lowest to highest value) */
379 /* - until voltage reaches final value +-1LSB */
380 /* - DAC channel output buffer enabled */
381 /* - load impedance of 5kOhm min, 50pF max */
382 /* Literal set to maximum value (refer to device datasheet, */
383 /* parameter "tSETTLING"). */
384 /* Unit: us */
385 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
386
387 /**
388 * @}
389 */
390
391 /**
392 * @}
393 */
394
395 /* Exported macro ------------------------------------------------------------*/
396 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
397 * @{
398 */
399
400 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
401 * @{
402 */
403
404 /**
405 * @brief Write a value in DAC register
406 * @param __INSTANCE__ DAC Instance
407 * @param __REG__ Register to be written
408 * @param __VALUE__ Value to be written in the register
409 * @retval None
410 */
411 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
412
413 /**
414 * @brief Read a value in DAC register
415 * @param __INSTANCE__ DAC Instance
416 * @param __REG__ Register to be read
417 * @retval Register value
418 */
419 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
420
421 /**
422 * @}
423 */
424
425 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
426 * @{
427 */
428
429 /**
430 * @brief Helper macro to get DAC channel number in decimal format
431 * from literals LL_DAC_CHANNEL_x.
432 * Example:
433 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
434 * will return decimal number "1".
435 * @note The input can be a value from functions where a channel
436 * number is returned.
437 * @param __CHANNEL__ This parameter can be one of the following values:
438 * @arg @ref LL_DAC_CHANNEL_1
439 * @retval 1
440 */
441 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
442 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
443
444 /**
445 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
446 * from number in decimal format.
447 * Example:
448 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
449 * will return a data equivalent to "LL_DAC_CHANNEL_1".
450 * @note If the input parameter does not correspond to a DAC channel,
451 * this macro returns value '0'.
452 * @param __DECIMAL_NB__ 1...2
453 * @retval Returned value can be one of the following values:
454 * @arg @ref LL_DAC_CHANNEL_1
455 */
456 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
457 (((__DECIMAL_NB__) == 1UL) \
458 ? (LL_DAC_CHANNEL_1) \
459 : \
460 (0UL) \
461 )
462
463 /**
464 * @brief Helper macro to define the DAC conversion data full-scale digital
465 * value corresponding to the selected DAC resolution.
466 * @note DAC conversion data full-scale corresponds to voltage range
467 * determined by analog voltage references Vref+ and Vref-
468 * (refer to reference manual).
469 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
470 * @arg @ref LL_DAC_RESOLUTION_12B
471 * @arg @ref LL_DAC_RESOLUTION_8B
472 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
473 */
474 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
475 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
476
477 /**
478 * @brief Helper macro to calculate the DAC conversion data (unit: digital
479 * value) corresponding to a voltage (unit: mVolt).
480 * @note This helper macro is intended to provide input data in voltage
481 * rather than digital value,
482 * to be used with LL DAC functions such as
483 * @ref LL_DAC_ConvertData12RightAligned().
484 * @note Analog reference voltage (Vref+) must be either known from
485 * user board environment or can be calculated using ADC measurement
486 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
487 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
488 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
489 * (unit: mVolt).
490 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
491 * @arg @ref LL_DAC_RESOLUTION_12B
492 * @arg @ref LL_DAC_RESOLUTION_8B
493 * @retval DAC conversion data (unit: digital value)
494 */
495 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
496 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
497 / (__VREFANALOG_VOLTAGE__) \
498 )
499
500 /**
501 * @}
502 */
503
504 /**
505 * @}
506 */
507
508
509 /* Exported functions --------------------------------------------------------*/
510 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
511 * @{
512 */
513
514 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
515 * @{
516 */
517
518 /**
519 * @brief Set the operating mode for the selected DAC channel:
520 * calibration or normal operating mode.
521 * @rmtoll CR CEN1 LL_DAC_SetMode
522 * @param DACx DAC instance
523 * @param DAC_Channel This parameter can be one of the following values:
524 * @arg @ref LL_DAC_CHANNEL_1
525 * @param ChannelMode This parameter can be one of the following values:
526 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
527 * @arg @ref LL_DAC_MODE_CALIBRATION
528 * @retval None
529 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)530 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
531 {
532 MODIFY_REG(DACx->CR,
533 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
534 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
535 }
536
537 /**
538 * @brief Get the operating mode for the selected DAC channel:
539 * calibration or normal operating mode.
540 * @rmtoll CR CEN1 LL_DAC_GetMode
541 * @param DACx DAC instance
542 * @param DAC_Channel This parameter can be one of the following values:
543 * @arg @ref LL_DAC_CHANNEL_1
544 * @retval Returned value can be one of the following values:
545 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
546 * @arg @ref LL_DAC_MODE_CALIBRATION
547 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)548 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
549 {
550 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
551 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
552 );
553 }
554
555 /**
556 * @brief Set the offset trimming value for the selected DAC channel.
557 * Trimming has an impact when output buffer is enabled
558 * and is intended to replace factory calibration default values.
559 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue
560 * @param DACx DAC instance
561 * @param DAC_Channel This parameter can be one of the following values:
562 * @arg @ref LL_DAC_CHANNEL_1
563 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
564 * @retval None
565 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)566 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
567 {
568 MODIFY_REG(DACx->CCR,
569 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
570 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
571 }
572
573 /**
574 * @brief Get the offset trimming value for the selected DAC channel.
575 * Trimming has an impact when output buffer is enabled
576 * and is intended to replace factory calibration default values.
577 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue
578 * @param DACx DAC instance
579 * @param DAC_Channel This parameter can be one of the following values:
580 * @arg @ref LL_DAC_CHANNEL_1
581 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
582 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)583 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
584 {
585 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
586 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
587 );
588 }
589
590 /**
591 * @brief Set the conversion trigger source for the selected DAC channel.
592 * @note For conversion trigger source to be effective, DAC trigger
593 * must be enabled using function @ref LL_DAC_EnableTrigger().
594 * @note To set conversion trigger source, DAC channel must be disabled.
595 * Otherwise, the setting is discarded.
596 * @note Availability of parameters of trigger sources from timer
597 * depends on timers availability on the selected device.
598 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource
599 * @param DACx DAC instance
600 * @param DAC_Channel This parameter can be one of the following values:
601 * @arg @ref LL_DAC_CHANNEL_1
602 * @param TriggerSource This parameter can be one of the following values:
603 * @arg @ref LL_DAC_TRIG_SOFTWARE
604 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
605 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
606 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
607 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
608 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
609 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
610 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
611 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
612 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
613 * @retval None
614 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)615 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
616 {
617 MODIFY_REG(DACx->CR,
618 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
619 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
620 }
621
622 /**
623 * @brief Get the conversion trigger source for the selected DAC channel.
624 * @note For conversion trigger source to be effective, DAC trigger
625 * must be enabled using function @ref LL_DAC_EnableTrigger().
626 * @note Availability of parameters of trigger sources from timer
627 * depends on timers availability on the selected device.
628 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource
629 * @param DACx DAC instance
630 * @param DAC_Channel This parameter can be one of the following values:
631 * @arg @ref LL_DAC_CHANNEL_1
632 * @retval Returned value can be one of the following values:
633 * @arg @ref LL_DAC_TRIG_SOFTWARE
634 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
635 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
636 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
637 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
638 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
639 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
640 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
641 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
642 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
643 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)644 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
645 {
646 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
647 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
648 );
649 }
650
651 /**
652 * @brief Set the waveform automatic generation mode
653 * for the selected DAC channel.
654 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration
655 * @param DACx DAC instance
656 * @param DAC_Channel This parameter can be one of the following values:
657 * @arg @ref LL_DAC_CHANNEL_1
658 * @param WaveAutoGeneration This parameter can be one of the following values:
659 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
660 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
661 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
662 * @retval None
663 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)664 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
665 {
666 MODIFY_REG(DACx->CR,
667 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
668 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
669 }
670
671 /**
672 * @brief Get the waveform automatic generation mode
673 * for the selected DAC channel.
674 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration
675 * @param DACx DAC instance
676 * @param DAC_Channel This parameter can be one of the following values:
677 * @arg @ref LL_DAC_CHANNEL_1
678 * @retval Returned value can be one of the following values:
679 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
680 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
681 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
682 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)683 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
684 {
685 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
686 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
687 );
688 }
689
690 /**
691 * @brief Set the noise waveform generation for the selected DAC channel:
692 * Noise mode and parameters LFSR (linear feedback shift register).
693 * @note For wave generation to be effective, DAC channel
694 * wave generation mode must be enabled using
695 * function @ref LL_DAC_SetWaveAutoGeneration().
696 * @note This setting can be set when the selected DAC channel is disabled
697 * (otherwise, the setting operation is ignored).
698 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR
699 * @param DACx DAC instance
700 * @param DAC_Channel This parameter can be one of the following values:
701 * @arg @ref LL_DAC_CHANNEL_1
702 * @param NoiseLFSRMask This parameter can be one of the following values:
703 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
704 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
706 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
707 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
708 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
709 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
710 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
711 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
712 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
713 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
714 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
715 * @retval None
716 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)717 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
718 {
719 MODIFY_REG(DACx->CR,
720 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
721 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
722 }
723
724 /**
725 * @brief Get the noise waveform generation for the selected DAC channel:
726 * Noise mode and parameters LFSR (linear feedback shift register).
727 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR
728 * @param DACx DAC instance
729 * @param DAC_Channel This parameter can be one of the following values:
730 * @arg @ref LL_DAC_CHANNEL_1
731 * @retval Returned value can be one of the following values:
732 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
733 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
734 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
735 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
736 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
737 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
738 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
739 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
740 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
741 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
742 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
743 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
744 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)745 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
746 {
747 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
748 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
749 );
750 }
751
752 /**
753 * @brief Set the triangle waveform generation for the selected DAC channel:
754 * triangle mode and amplitude.
755 * @note For wave generation to be effective, DAC channel
756 * wave generation mode must be enabled using
757 * function @ref LL_DAC_SetWaveAutoGeneration().
758 * @note This setting can be set when the selected DAC channel is disabled
759 * (otherwise, the setting operation is ignored).
760 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
761 * @param DACx DAC instance
762 * @param DAC_Channel This parameter can be one of the following values:
763 * @arg @ref LL_DAC_CHANNEL_1
764 * @param TriangleAmplitude This parameter can be one of the following values:
765 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
766 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
767 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
768 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
769 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
770 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
771 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
772 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
773 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
774 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
775 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
776 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
777 * @retval None
778 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)779 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
780 uint32_t TriangleAmplitude)
781 {
782 MODIFY_REG(DACx->CR,
783 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
784 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
785 }
786
787 /**
788 * @brief Get the triangle waveform generation for the selected DAC channel:
789 * triangle mode and amplitude.
790 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
791 * @param DACx DAC instance
792 * @param DAC_Channel This parameter can be one of the following values:
793 * @arg @ref LL_DAC_CHANNEL_1
794 * @retval Returned value can be one of the following values:
795 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
796 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
797 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
798 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
799 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
800 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
801 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
802 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
803 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
804 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
805 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
806 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
807 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)808 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
809 {
810 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
811 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
812 );
813 }
814
815 /**
816 * @brief Set the output for the selected DAC channel.
817 * @note This function set several features:
818 * - mode normal or sample-and-hold
819 * - buffer
820 * - connection to GPIO or internal path.
821 * These features can also be set individually using
822 * dedicated functions:
823 * - @ref LL_DAC_SetOutputBuffer()
824 * - @ref LL_DAC_SetOutputMode()
825 * - @ref LL_DAC_SetOutputConnection()
826 * @note On this STM32 series, output connection depends on output mode
827 * (normal or sample and hold) and output buffer state.
828 * - if output connection is set to internal path and output buffer
829 * is enabled (whatever output mode):
830 * output connection is also connected to GPIO pin
831 * (both connections to GPIO pin and internal path).
832 * - if output connection is set to GPIO pin, output buffer
833 * is disabled, output mode set to sample and hold:
834 * output connection is also connected to internal path
835 * (both connections to GPIO pin and internal path).
836 * @note Mode sample-and-hold requires an external capacitor
837 * to be connected between DAC channel output and ground.
838 * Capacitor value depends on load on DAC channel output and
839 * sample-and-hold timings configured.
840 * As indication, capacitor typical value is 100nF
841 * (refer to device datasheet, parameter "CSH").
842 * @rmtoll CR MODE1 LL_DAC_ConfigOutput
843 * @param DACx DAC instance
844 * @param DAC_Channel This parameter can be one of the following values:
845 * @arg @ref LL_DAC_CHANNEL_1
846 * @param OutputMode This parameter can be one of the following values:
847 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
848 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
849 * @param OutputBuffer This parameter can be one of the following values:
850 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
851 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
852 * @param OutputConnection This parameter can be one of the following values:
853 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
854 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
855 * @retval None
856 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)857 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
858 uint32_t OutputBuffer, uint32_t OutputConnection)
859 {
860 MODIFY_REG(DACx->MCR,
861 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
862 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
863 }
864
865 /**
866 * @brief Set the output mode normal or sample-and-hold
867 * for the selected DAC channel.
868 * @note Mode sample-and-hold requires an external capacitor
869 * to be connected between DAC channel output and ground.
870 * Capacitor value depends on load on DAC channel output and
871 * sample-and-hold timings configured.
872 * As indication, capacitor typical value is 100nF
873 * (refer to device datasheet, parameter "CSH").
874 * @rmtoll CR MODE1 LL_DAC_SetOutputMode
875 * @param DACx DAC instance
876 * @param DAC_Channel This parameter can be one of the following values:
877 * @arg @ref LL_DAC_CHANNEL_1
878 * @param OutputMode This parameter can be one of the following values:
879 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
880 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
881 * @retval None
882 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)883 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
884 {
885 MODIFY_REG(DACx->MCR,
886 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
887 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
888 }
889
890 /**
891 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
892 * @rmtoll CR MODE1 LL_DAC_GetOutputMode
893 * @param DACx DAC instance
894 * @param DAC_Channel This parameter can be one of the following values:
895 * @arg @ref LL_DAC_CHANNEL_1
896 * @retval Returned value can be one of the following values:
897 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
898 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
899 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)900 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
901 {
902 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
903 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
904 );
905 }
906
907 /**
908 * @brief Set the output buffer for the selected DAC channel.
909 * @note On this STM32 series, when buffer is enabled, its offset can be
910 * trimmed: factory calibration default values can be
911 * replaced by user trimming values, using function
912 * @ref LL_DAC_SetTrimmingValue().
913 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer
914 * @param DACx DAC instance
915 * @param DAC_Channel This parameter can be one of the following values:
916 * @arg @ref LL_DAC_CHANNEL_1
917 * @param OutputBuffer This parameter can be one of the following values:
918 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
919 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
920 * @retval None
921 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)922 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
923 {
924 MODIFY_REG(DACx->MCR,
925 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
926 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
927 }
928
929 /**
930 * @brief Get the output buffer state for the selected DAC channel.
931 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer
932 * @param DACx DAC instance
933 * @param DAC_Channel This parameter can be one of the following values:
934 * @arg @ref LL_DAC_CHANNEL_1
935 * @retval Returned value can be one of the following values:
936 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
937 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
938 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)939 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
940 {
941 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
942 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
943 );
944 }
945
946 /**
947 * @brief Set the output connection for the selected DAC channel.
948 * @note On this STM32 series, output connection depends on output mode (normal or
949 * sample and hold) and output buffer state.
950 * - if output connection is set to internal path and output buffer
951 * is enabled (whatever output mode):
952 * output connection is also connected to GPIO pin
953 * (both connections to GPIO pin and internal path).
954 * - if output connection is set to GPIO pin, output buffer
955 * is disabled, output mode set to sample and hold:
956 * output connection is also connected to internal path
957 * (both connections to GPIO pin and internal path).
958 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection
959 * @param DACx DAC instance
960 * @param DAC_Channel This parameter can be one of the following values:
961 * @arg @ref LL_DAC_CHANNEL_1
962 * @param OutputConnection This parameter can be one of the following values:
963 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
964 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
965 * @retval None
966 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)967 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
968 {
969 MODIFY_REG(DACx->MCR,
970 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
971 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
972 }
973
974 /**
975 * @brief Get the output connection for the selected DAC channel.
976 * @note On this STM32 series, output connection depends on output mode (normal or
977 * sample and hold) and output buffer state.
978 * - if output connection is set to internal path and output buffer
979 * is enabled (whatever output mode):
980 * output connection is also connected to GPIO pin
981 * (both connections to GPIO pin and internal path).
982 * - if output connection is set to GPIO pin, output buffer
983 * is disabled, output mode set to sample and hold:
984 * output connection is also connected to internal path
985 * (both connections to GPIO pin and internal path).
986 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection
987 * @param DACx DAC instance
988 * @param DAC_Channel This parameter can be one of the following values:
989 * @arg @ref LL_DAC_CHANNEL_1
990 * @retval Returned value can be one of the following values:
991 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
992 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
993 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)994 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
995 {
996 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
997 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
998 );
999 }
1000
1001 /**
1002 * @brief Set the sample-and-hold timing for the selected DAC channel:
1003 * sample time
1004 * @note Sample time must be set when DAC channel is disabled
1005 * or during DAC operation when DAC channel flag BWSTx is reset,
1006 * otherwise the setting is ignored.
1007 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1008 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime
1009 * @param DACx DAC instance
1010 * @param DAC_Channel This parameter can be one of the following values:
1011 * @arg @ref LL_DAC_CHANNEL_1
1012 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1013 * @retval None
1014 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1015 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1016 {
1017 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1018 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1019
1020 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1021 }
1022
1023 /**
1024 * @brief Get the sample-and-hold timing for the selected DAC channel:
1025 * sample time
1026 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime
1027 * @param DACx DAC instance
1028 * @param DAC_Channel This parameter can be one of the following values:
1029 * @arg @ref LL_DAC_CHANNEL_1
1030 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1031 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1032 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1033 {
1034 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1035 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1036
1037 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1038 }
1039
1040 /**
1041 * @brief Set the sample-and-hold timing for the selected DAC channel:
1042 * hold time
1043 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime
1044 * @param DACx DAC instance
1045 * @param DAC_Channel This parameter can be one of the following values:
1046 * @arg @ref LL_DAC_CHANNEL_1
1047 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1048 * @retval None
1049 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1050 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1051 {
1052 MODIFY_REG(DACx->SHHR,
1053 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1054 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1055 }
1056
1057 /**
1058 * @brief Get the sample-and-hold timing for the selected DAC channel:
1059 * hold time
1060 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime
1061 * @param DACx DAC instance
1062 * @param DAC_Channel This parameter can be one of the following values:
1063 * @arg @ref LL_DAC_CHANNEL_1
1064 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1065 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1066 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1067 {
1068 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1069 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1070 );
1071 }
1072
1073 /**
1074 * @brief Set the sample-and-hold timing for the selected DAC channel:
1075 * refresh time
1076 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime
1077 * @param DACx DAC instance
1078 * @param DAC_Channel This parameter can be one of the following values:
1079 * @arg @ref LL_DAC_CHANNEL_1
1080 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1081 * @retval None
1082 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1083 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1084 {
1085 MODIFY_REG(DACx->SHRR,
1086 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1087 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1088 }
1089
1090 /**
1091 * @brief Get the sample-and-hold timing for the selected DAC channel:
1092 * refresh time
1093 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime
1094 * @param DACx DAC instance
1095 * @param DAC_Channel This parameter can be one of the following values:
1096 * @arg @ref LL_DAC_CHANNEL_1
1097 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1098 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1099 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1100 {
1101 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1102 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1103 );
1104 }
1105
1106 /**
1107 * @}
1108 */
1109
1110 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1111 * @{
1112 */
1113
1114 /**
1115 * @brief Enable DAC DMA transfer request of the selected channel.
1116 * @note To configure DMA source address (peripheral address),
1117 * use function @ref LL_DAC_DMA_GetRegAddr().
1118 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq
1119 * @param DACx DAC instance
1120 * @param DAC_Channel This parameter can be one of the following values:
1121 * @arg @ref LL_DAC_CHANNEL_1
1122 * @retval None
1123 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1124 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1125 {
1126 SET_BIT(DACx->CR,
1127 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1128 }
1129
1130 /**
1131 * @brief Disable DAC DMA transfer request of the selected channel.
1132 * @note To configure DMA source address (peripheral address),
1133 * use function @ref LL_DAC_DMA_GetRegAddr().
1134 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq
1135 * @param DACx DAC instance
1136 * @param DAC_Channel This parameter can be one of the following values:
1137 * @arg @ref LL_DAC_CHANNEL_1
1138 * @retval None
1139 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1140 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1141 {
1142 CLEAR_BIT(DACx->CR,
1143 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1144 }
1145
1146 /**
1147 * @brief Get DAC DMA transfer request state of the selected channel.
1148 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1149 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled
1150 * @param DACx DAC instance
1151 * @param DAC_Channel This parameter can be one of the following values:
1152 * @arg @ref LL_DAC_CHANNEL_1
1153 * @retval State of bit (1 or 0).
1154 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1155 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1156 {
1157 return ((READ_BIT(DACx->CR,
1158 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1159 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1160 }
1161
1162 /**
1163 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1164 * DAC register address from DAC instance and a list of DAC registers
1165 * intended to be used (most commonly) with DMA transfer.
1166 * @note These DAC registers are data holding registers:
1167 * when DAC conversion is requested, DAC generates a DMA transfer
1168 * request to have data available in DAC data holding registers.
1169 * @note This macro is intended to be used with LL DMA driver, refer to
1170 * function "LL_DMA_ConfigAddresses()".
1171 * Example:
1172 * LL_DMA_ConfigAddresses(DMA1,
1173 * LL_DMA_CHANNEL_1,
1174 * (uint32_t)&< array or variable >,
1175 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1176 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1177 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1178 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1179 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1180 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
1181 * @param DACx DAC instance
1182 * @param DAC_Channel This parameter can be one of the following values:
1183 * @arg @ref LL_DAC_CHANNEL_1
1184 * @param Register This parameter can be one of the following values:
1185 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1186 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1187 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1188 * @retval DAC register address
1189 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1190 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1191 {
1192 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1193 /* DAC channel selected. */
1194 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1195 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1196 }
1197 /**
1198 * @}
1199 */
1200
1201 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1202 * @{
1203 */
1204
1205 /**
1206 * @brief Enable DAC selected channel.
1207 * @rmtoll CR EN1 LL_DAC_Enable
1208 * @note After enable from off state, DAC channel requires a delay
1209 * for output voltage to reach accuracy +/- 1 LSB.
1210 * Refer to device datasheet, parameter "tWAKEUP".
1211 * @param DACx DAC instance
1212 * @param DAC_Channel This parameter can be one of the following values:
1213 * @arg @ref LL_DAC_CHANNEL_1
1214 * @retval None
1215 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1216 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1217 {
1218 SET_BIT(DACx->CR,
1219 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1220 }
1221
1222 /**
1223 * @brief Disable DAC selected channel.
1224 * @rmtoll CR EN1 LL_DAC_Disable
1225 * @param DACx DAC instance
1226 * @param DAC_Channel This parameter can be one of the following values:
1227 * @arg @ref LL_DAC_CHANNEL_1
1228 * @retval None
1229 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1230 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1231 {
1232 CLEAR_BIT(DACx->CR,
1233 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1234 }
1235
1236 /**
1237 * @brief Get DAC enable state of the selected channel.
1238 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1239 * @rmtoll CR EN1 LL_DAC_IsEnabled
1240 * @param DACx DAC instance
1241 * @param DAC_Channel This parameter can be one of the following values:
1242 * @arg @ref LL_DAC_CHANNEL_1
1243 * @retval State of bit (1 or 0).
1244 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1245 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1246 {
1247 return ((READ_BIT(DACx->CR,
1248 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1249 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1250 }
1251
1252 /**
1253 * @brief Enable DAC trigger of the selected channel.
1254 * @note - If DAC trigger is disabled, DAC conversion is performed
1255 * automatically once the data holding register is updated,
1256 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1257 * @ref LL_DAC_ConvertData12RightAligned(), ...
1258 * - If DAC trigger is enabled, DAC conversion is performed
1259 * only when a hardware of software trigger event is occurring.
1260 * Select trigger source using
1261 * function @ref LL_DAC_SetTriggerSource().
1262 * @rmtoll CR TEN1 LL_DAC_EnableTrigger
1263 * @param DACx DAC instance
1264 * @param DAC_Channel This parameter can be one of the following values:
1265 * @arg @ref LL_DAC_CHANNEL_1
1266 * @retval None
1267 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1268 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1269 {
1270 SET_BIT(DACx->CR,
1271 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1272 }
1273
1274 /**
1275 * @brief Disable DAC trigger of the selected channel.
1276 * @rmtoll CR TEN1 LL_DAC_DisableTrigger
1277 * @param DACx DAC instance
1278 * @param DAC_Channel This parameter can be one of the following values:
1279 * @arg @ref LL_DAC_CHANNEL_1
1280 * @retval None
1281 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1282 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1283 {
1284 CLEAR_BIT(DACx->CR,
1285 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1286 }
1287
1288 /**
1289 * @brief Get DAC trigger state of the selected channel.
1290 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1291 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled
1292 * @param DACx DAC instance
1293 * @param DAC_Channel This parameter can be one of the following values:
1294 * @arg @ref LL_DAC_CHANNEL_1
1295 * @retval State of bit (1 or 0).
1296 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1297 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1298 {
1299 return ((READ_BIT(DACx->CR,
1300 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1301 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1302 }
1303
1304 /**
1305 * @brief Trig DAC conversion by software for the selected DAC channel.
1306 * @note Preliminarily, DAC trigger must be set to software trigger
1307 * using function
1308 * @ref LL_DAC_Init()
1309 * @ref LL_DAC_SetTriggerSource()
1310 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1311 * and DAC trigger must be enabled using
1312 * function @ref LL_DAC_EnableTrigger().
1313 * @note For devices featuring DAC with 2 channels: this function
1314 * can perform a SW start of both DAC channels simultaneously.
1315 * Two channels can be selected as parameter.
1316 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1317 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
1318 * @param DACx DAC instance
1319 * @param DAC_Channel This parameter can a combination of the following values:
1320 * @arg @ref LL_DAC_CHANNEL_1
1321 * @retval None
1322 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1323 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1324 {
1325 SET_BIT(DACx->SWTRIGR,
1326 (DAC_Channel & DAC_SWTR_CHX_MASK));
1327 }
1328
1329 /**
1330 * @brief Set the data to be loaded in the data holding register
1331 * in format 12 bits left alignment (LSB aligned on bit 0),
1332 * for the selected DAC channel.
1333 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
1334 * @param DACx DAC instance
1335 * @param DAC_Channel This parameter can be one of the following values:
1336 * @arg @ref LL_DAC_CHANNEL_1
1337 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1338 * @retval None
1339 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1340 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1341 {
1342 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1343 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1344
1345 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1346 }
1347
1348 /**
1349 * @brief Set the data to be loaded in the data holding register
1350 * in format 12 bits left alignment (MSB aligned on bit 15),
1351 * for the selected DAC channel.
1352 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
1353 * @param DACx DAC instance
1354 * @param DAC_Channel This parameter can be one of the following values:
1355 * @arg @ref LL_DAC_CHANNEL_1
1356 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1357 * @retval None
1358 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1359 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1360 {
1361 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1362 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1363
1364 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1365 }
1366
1367 /**
1368 * @brief Set the data to be loaded in the data holding register
1369 * in format 8 bits left alignment (LSB aligned on bit 0),
1370 * for the selected DAC channel.
1371 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
1372 * @param DACx DAC instance
1373 * @param DAC_Channel This parameter can be one of the following values:
1374 * @arg @ref LL_DAC_CHANNEL_1
1375 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1376 * @retval None
1377 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1378 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1379 {
1380 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1381 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1382
1383 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1384 }
1385
1386 /**
1387 * @brief Retrieve output data currently generated for the selected DAC channel.
1388 * @note Whatever alignment and resolution settings
1389 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1390 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1391 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1392 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData
1393 * @param DACx DAC instance
1394 * @param DAC_Channel This parameter can be one of the following values:
1395 * @arg @ref LL_DAC_CHANNEL_1
1396 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1397 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1398 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1399 {
1400 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1401 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1402
1403 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1404 }
1405
1406 /**
1407 * @}
1408 */
1409
1410 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1411 * @{
1412 */
1413
1414 /**
1415 * @brief Get DAC calibration offset flag for DAC channel 1
1416 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1417 * @param DACx DAC instance
1418 * @retval State of bit (1 or 0).
1419 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1420 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1421 {
1422 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1423 }
1424
1425 /**
1426 * @brief Get DAC busy writing sample time flag for DAC channel 1
1427 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1428 * @param DACx DAC instance
1429 * @retval State of bit (1 or 0).
1430 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1431 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1432 {
1433 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1434 }
1435
1436 /**
1437 * @brief Get DAC underrun flag for DAC channel 1
1438 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1439 * @param DACx DAC instance
1440 * @retval State of bit (1 or 0).
1441 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1442 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1443 {
1444 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1445 }
1446
1447 /**
1448 * @brief Clear DAC underrun flag for DAC channel 1
1449 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1450 * @param DACx DAC instance
1451 * @retval None
1452 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1453 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1454 {
1455 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1456 }
1457
1458 /**
1459 * @}
1460 */
1461
1462 /** @defgroup DAC_LL_EF_IT_Management IT management
1463 * @{
1464 */
1465
1466 /**
1467 * @brief Enable DMA underrun interrupt for DAC channel 1
1468 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1469 * @param DACx DAC instance
1470 * @retval None
1471 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1472 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1473 {
1474 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1475 }
1476
1477 /**
1478 * @brief Disable DMA underrun interrupt for DAC channel 1
1479 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1480 * @param DACx DAC instance
1481 * @retval None
1482 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1483 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1484 {
1485 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1486 }
1487
1488 /**
1489 * @brief Get DMA underrun interrupt for DAC channel 1
1490 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1491 * @param DACx DAC instance
1492 * @retval State of bit (1 or 0).
1493 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1494 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1495 {
1496 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1497 }
1498
1499 /**
1500 * @}
1501 */
1502
1503 #if defined(USE_FULL_LL_DRIVER)
1504 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1505 * @{
1506 */
1507
1508 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1509 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1510 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1511
1512 /**
1513 * @}
1514 */
1515 #endif /* USE_FULL_LL_DRIVER */
1516
1517 /**
1518 * @}
1519 */
1520
1521 /**
1522 * @}
1523 */
1524
1525 #endif /* DAC1 */
1526
1527 /**
1528 * @}
1529 */
1530
1531 #ifdef __cplusplus
1532 }
1533 #endif
1534
1535 #endif /* STM32U0xx_LL_DAC_H */
1536
