1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_ADC_H
21 #define STM32U0xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66 /* Internal mask for ADC group regular trigger: */
67 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
68 /* - regular trigger source */
69 /* - regular trigger edge */
70 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
71 compatibility with some ADC on other STM32 series
72 having this setting set by HW default value) */
73
74 /* Mask containing trigger source masks for each of possible */
75 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
76 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
77 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
78 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
80 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
81
82 /* Mask containing trigger edge masks for each of possible */
83 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
84 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
85 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
86 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
88 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
89
90 /* Definition of ADC group regular trigger bits information. */
91 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
92 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
93
94
95 /* Internal mask for ADC channel: */
96 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
97 /* - channel identifier defined by number */
98 /* - channel identifier defined by bitfield */
99 /* - channel differentiation between external channels (connected to */
100 /* GPIO pins) and internal channels (connected to internal paths) */
101 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
102 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
103 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
104 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
105 if set to mode "fully configurable", can contain channels with a restricted channel number.
106 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
107 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
108 position in register */
109 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
110 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
111 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
112 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
113 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
114
115 /* Channel differentiation between external and internal channels */
116 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
117 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
118
119 /* Definition of channels ID number information to be inserted into */
120 /* channels literals definition. */
121 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
122 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
123 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
124 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
125 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
126 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
127 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
128 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
129 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
130 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
131 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
132 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
134 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
136 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
137 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
138 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
139 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
141 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
142
143 /* Definition of channels ID bitfield information to be inserted into */
144 /* channels literals definition. */
145 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
146 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
147 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
148 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
149 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
150 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
151 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
152 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
153 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
154 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
155 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
156 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
157 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
158 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
159 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
160 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
161 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
162 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
163 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
164 #define ADC_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
165
166 /* Internal mask for ADC channel sampling time: */
167 /* To select into literals LL_ADC_SAMPLINGTIME_x */
168 /* the relevant bits for: */
169 /* (concatenation of multiple bits used in register SMPR) */
170 /* - ADC channels sampling time: setting channel wise, to map each channel */
171 /* on one of the common sampling time available. */
172 /* - ADC channels common sampling time: set a sampling time into one of the */
173 /* common sampling time available. */
174 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
175 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
176 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
177
178 /* Internal mask for ADC analog watchdog: */
179 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
180 /* (concatenation of multiple bits used in different analog watchdogs, */
181 /* (feature of several watchdogs not available on all STM32 series)). */
182 /* - analog watchdog 1: monitored channel defined by number, */
183 /* selection of ADC group (ADC group regular). */
184 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
185 /* selection on groups. */
186
187 /* Internal register offset for ADC analog watchdog channel configuration */
188 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
189 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
190 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
191
192 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
193 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
194 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
195 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
196
197 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
198 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
199
200 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
201 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
202 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
203
204 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
205 in ADC_AWD_CRX_REGOFFSET_MASK */
206
207 /* Internal register offset for ADC analog watchdog threshold configuration */
208 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
209 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
210 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
211 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
212 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
213 in ADC_AWD_TRX_REGOFFSET_MASK */
214 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
215 threshold high: mask of bit */
216 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
217 threshold high: position of bit */
218 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
219 position to perform a shift of 4 ranks */
220 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
221
222
223 /* ADC registers bits positions */
224 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
225 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
226 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
227 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
228 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
229 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
230 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
231 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
232 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
233 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
234 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
235 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
236 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
237 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
238 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
239 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
240 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
241 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
242 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
243 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
244 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
245 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
246 #define ADC_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL19" position in register */
247 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
248 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
249 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
250
251
252 /* ADC registers bits groups */
253 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
254 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
255 HW property "rs": Software can read as well as set this bit.
256 Writing '0' has no effect on the bit value. */
257
258
259 /* ADC internal channels related definitions */
260 /* Internal voltage reference VrefInt */
261 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF6EA4UL)) /* Internal voltage reference, address of
262 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 Deg
263 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
264 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value
265 with which VrefInt has been calibrated in production
266 (tolerance: +-10 mV) (unit: mV). */
267 /* Temperature sensor */
268 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF6E68UL)) /* Address of parameter TS_CAL1: On STM32U0,
269 temperature sensor ADC raw data acquired at temperature 30 DegC
270 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
271 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF6E8AUL)) /* Address of parameter TS_CAL2: On STM32U0,
272 temperature sensor ADC raw data acquired at temperature 130 DegC
273 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
274 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
275 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
276 (tolerance: +-5 DegC) (unit: DegC). */
277 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
278 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
279 (tolerance: +-5 DegC) (unit: DegC). */
280 #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value
281 with which temperature sensor has been calibrated in production
282 (tolerance: +-10 mV) (unit: mV). */
283
284 /**
285 * @}
286 */
287
288
289 /* Private macros ------------------------------------------------------------*/
290 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
291 * @{
292 */
293
294 /**
295 * @brief Driver macro reserved for internal use: set a pointer to
296 * a register from a register basis from which an offset
297 * is applied.
298 * @param __REG__ Register basis from which the offset is applied.
299 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
300 * @retval Pointer to register address
301 */
302 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
303 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
304
305 /**
306 * @}
307 */
308
309
310 /* Exported types ------------------------------------------------------------*/
311 #if defined(USE_FULL_LL_DRIVER)
312 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
313 * @{
314 */
315
316 /**
317 * @brief Structure definition of some features of ADC common parameters
318 * and multimode
319 * (all ADC instances belonging to the same ADC common instance).
320 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
321 * is conditioned to ADC instances state (all ADC instances
322 * sharing the same ADC common instance):
323 * All ADC instances sharing the same ADC common instance must be
324 * disabled.
325 */
326 typedef struct
327 {
328 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
329 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
330 This feature can be modified afterwards using unitary function
331 @ref LL_ADC_SetCommonClock(). */
332
333 } LL_ADC_CommonInitTypeDef;
334
335 /**
336 * @brief Structure definition of some features of ADC instance.
337 * @note These parameters have an impact on ADC scope: ADC instance.
338 * Refer to corresponding unitary functions into
339 * @ref ADC_LL_EF_Configuration_ADC_Instance .
340 * @note The setting of these parameters by function @ref LL_ADC_Init()
341 * is conditioned to ADC state:
342 * ADC instance must be disabled.
343 * This condition is applied to all ADC features, for efficiency
344 * and compatibility over all STM32 series. However, the different
345 * features can be set under different ADC state conditions
346 * (setting possible with ADC enabled without conversion on going,
347 * ADC enabled with conversion on going, ...)
348 * Each feature can be updated afterwards with a unitary function
349 * and potentially with ADC in a different state than disabled,
350 * refer to description of each function for setting
351 * conditioned to ADC state.
352 */
353 typedef struct
354 {
355 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
356 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
357 @note On this STM32 series, this parameter has some clock ratio constraints:
358 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
359 only if PCLK has a 50% duty clock cycle (APB prescaler configured
360 inside the RCC must be bypassed and the system clock must by 50% duty
361 cycle).
362 This feature can be modified afterwards using unitary function
363 @ref LL_ADC_SetClock().
364 For more details, refer to description of this function. */
365
366 uint32_t Resolution; /*!< Set ADC resolution.
367 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
368 This feature can be modified afterwards using unitary function
369 @ref LL_ADC_SetResolution(). */
370
371 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
372 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
373 This feature can be modified afterwards using unitary function
374 @ref LL_ADC_SetDataAlignment(). */
375
376 uint32_t LowPowerMode; /*!< Set ADC low power mode.
377 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
378 This feature can be modified afterwards using unitary function
379 @ref LL_ADC_SetLowPowerMode(). */
380
381 } LL_ADC_InitTypeDef;
382
383 /**
384 * @brief Structure definition of some features of ADC group regular.
385 * @note These parameters have an impact on ADC scope: ADC group regular.
386 * Refer to corresponding unitary functions into
387 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
388 * (functions with prefix "REG").
389 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
390 * is conditioned to ADC state:
391 * ADC instance must be disabled.
392 * This condition is applied to all ADC features, for efficiency
393 * and compatibility over all STM32 series. However, the different
394 * features can be set under different ADC state conditions
395 * (setting possible with ADC enabled without conversion on going,
396 * ADC enabled with conversion on going, ...)
397 * Each feature can be updated afterwards with a unitary function
398 * and potentially with ADC in a different state than disabled,
399 * refer to description of each function for setting
400 * conditioned to ADC state.
401 */
402 typedef struct
403 {
404 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
405 from external peripheral (timer event, external interrupt line).
406 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
407 @note On this STM32 series, setting trigger source to external trigger also
408 set trigger polarity to rising edge(default setting for compatibility
409 with some ADC on other STM32 series having this setting set by HW
410 default value).
411 In case of need to modify trigger edge, use function
412 @ref LL_ADC_REG_SetTriggerEdge().
413 This feature can be modified afterwards using unitary function
414 @ref LL_ADC_REG_SetTriggerSource(). */
415
416 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
417 @note This parameter has an effect only if group regular sequencer is set
418 to mode "fully configurable". Refer to function
419 @ref LL_ADC_REG_SetSequencerConfigurable().
420 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
421 This feature can be modified afterwards using unitary function
422 @ref LL_ADC_REG_SetSequencerLength(). */
423
424 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
425 and scan conversions interrupted every selected number of ranks.
426 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
427 @note This parameter has an effect only if group regular sequencer is
428 enabled (depending on the sequencer mode: scan length of 2 ranks or
429 more, or several ADC channels enabled in group regular sequencer.
430 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
431 This feature can be modified afterwards using unitary function
432 @ref LL_ADC_REG_SetSequencerDiscont(). */
433
434 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
435 conversions are performed in single mode (one conversion per trigger) or in
436 continuous mode (after the first trigger, following conversions launched
437 successively automatically).
438 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
439 Note: It is not possible to enable both ADC group regular continuous mode
440 and discontinuous mode.
441 This feature can be modified afterwards using unitary function
442 @ref LL_ADC_REG_SetContinuousMode(). */
443
444 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
445 by DMA, and DMA requests mode.
446 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
447 This feature can be modified afterwards using unitary function
448 @ref LL_ADC_REG_SetDMATransfer(). */
449
450 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
451 data preserved or overwritten.
452 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
453 This feature can be modified afterwards using unitary function
454 @ref LL_ADC_REG_SetOverrun(). */
455
456 } LL_ADC_REG_InitTypeDef;
457
458 /**
459 * @}
460 */
461 #endif /* USE_FULL_LL_DRIVER */
462
463 /* Exported constants --------------------------------------------------------*/
464 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
465 * @{
466 */
467
468 /** @defgroup ADC_LL_EC_FLAG ADC flags
469 * @brief Flags defines which can be used with LL_ADC_ReadReg function
470 * @{
471 */
472 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
473 #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
474 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
475 conversion */
476 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
477 conversions */
478 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
479 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
480 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
481 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
482 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
483 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
484 /**
485 * @}
486 */
487
488 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
489 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
490 * @{
491 */
492 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
493 #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
494 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
495 conversion */
496 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
497 conversions */
498 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
499 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
500 phase */
501 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
502 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
503 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
504 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
505 /**
506 * @}
507 */
508
509 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
510 * @{
511 */
512 /* List of ADC registers intended to be used (most commonly) with */
513 /* DMA transfer. */
514 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
515 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
516 (corresponding to register DR) to be used with ADC configured in independent
517 mode. Without DMA transfer, register accessed by LL function
518 @ref LL_ADC_REG_ReadConversionData32() and other
519 functions @ref LL_ADC_REG_ReadConversionDatax() */
520 /**
521 * @}
522 */
523
524 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
525 * @{
526 */
527 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
528 prescaler */
529 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
530 prescaler division by 2. Setting common to ADC instances of ADC common
531 group, applied ADC instance wise to each instance clock set to clock source
532 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
533 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
534 prescaler division by 4. Setting common to ADC instances of ADC common
535 group, applied ADC instance wise to each instance clock set to clock source
536 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
537 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
538 prescaler division by 6. Setting common to ADC instances of ADC common
539 group, applied ADC instance wise to each instance clock set to clock source
540 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
541 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
542 prescaler division by 8. Setting common to ADC instances of ADC common
543 group, applied ADC instance wise to each instance clock set to clock source
544 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
545 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
546 prescaler division by 10. Setting common to ADC instances of ADC common
547 group, applied ADC instance wise to each instance clock set to clock source
548 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
549 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
550 prescaler division by 12. Setting common to ADC instances of ADC common
551 group, applied ADC instance wise to each instance clock set to clock source
552 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
553 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
554 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
555 prescaler division by 16. Setting common to ADC instances of ADC common
556 group, applied ADC instance wise to each instance clock set to clock source
557 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
558 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
559 prescaler division by 32. Setting common to ADC instances of ADC common
560 group, applied ADC instance wise to each instance clock set to clock source
561 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
562 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
563 prescaler division by 64. Setting common to ADC instances of ADC common
564 group, applied ADC instance wise to each instance clock set to clock source
565 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
566 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
567 prescaler division by 128. Setting common to ADC instances of ADC common
568 group, applied ADC instance wise to each instance clock set to clock source
569 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
570 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
571 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
572 prescaler division by 256. Setting common to ADC instances of ADC common
573 group, applied ADC instance wise to each instance clock set to clock source
574 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
575 /**
576 * @}
577 */
578
579 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
580 * @{
581 */
582 /* Note: Other measurement paths to internal channels may be available */
583 /* (connections to other peripherals). */
584 /* If they are not listed below, they do not require any specific */
585 /* path enable. In this case, Access to measurement path is done */
586 /* only by selecting the corresponding ADC internal channel. */
587 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
588 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
589 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
590 temperature sensor */
591 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
592 /**
593 * @}
594 */
595
596 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
597 * @{
598 */
599 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock
600 divided by 4 */
601 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
602 divided by 2 */
603 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \
604 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
605 not divided */
606 #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock
607 prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
608 /**
609 * @}
610 */
611
612 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
613 * @{
614 */
615 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
616 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
617 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
618 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
619 /**
620 * @}
621 */
622
623 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
624 * @{
625 */
626 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
627 (alignment on data register LSB bit 0)*/
628 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
629 (alignment on data register MSB bit 15)*/
630 /**
631 * @}
632 */
633
634 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
635 * @{
636 */
637 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
638 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power
639 mode, ADC conversions are performed only when necessary
640 (when previous ADC conversion data is read).
641 See description with function @ref LL_ADC_SetLowPowerMode(). */
642 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC
643 automatically powers-off after a ADC conversion and automatically wakes up
644 when a new ADC conversion is triggered (with startup time between trigger
645 and start of sampling). See description with function
646 @ref LL_ADC_SetLowPowerMode(). */
647 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait
648 and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
649 /**
650 * @}
651 */
652
653 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
654 * @{
655 */
656 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency.
657 Note: ADC trigger frequency mode must be set to low frequency when a duration
658 is exceeded before ADC conversion start trigger event (between ADC enable
659 and ADC conversion start trigger event or between two ADC conversion start
660 trigger event).
661 Duration value: Refer to device datasheet, parameter "tIdle". */
662 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
663 Note: ADC trigger frequency mode must be set to low frequency when a duration
664 is exceeded before ADC conversion start trigger event (between ADC enable
665 and ADC conversion start trigger event or between two ADC conversion start
666 trigger event).
667 Duration value: Refer to device datasheet, parameter "tIdle". */
668 /**
669 * @}
670 */
671
672 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
673 * @{
674 */
675 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
676 of channels: sampling time nb 1 */
677 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \
678 | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group
679 of channels: sampling time nb 2 */
680 /**
681 * @}
682 */
683
684 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
685 * @{
686 */
687 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
688 /**
689 * @}
690 */
691
692 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
693 * @{
694 */
695 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \
696 | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */
697 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \
698 | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */
699 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \
700 | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */
701 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \
702 | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */
703 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \
704 | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */
705 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \
706 | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */
707 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \
708 | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */
709 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \
710 | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */
711 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \
712 | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */
713 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \
714 | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */
715 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \
716 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
717 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \
718 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
719 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \
720 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
721 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \
722 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
723 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \
724 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
725 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \
726 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
727 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \
728 | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
729 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \
730 | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
731 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \
732 | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
733 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER \
734 | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */
735 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_11 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
736 connected to internal temperature sensor. */
737 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
738 connected to VrefInt: Internal voltage reference. */
739 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
740 connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3
741 to have channel voltage always below Vdda. */
742 #define LL_ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
743 connected to DAC channel 1. */
744 /**
745 * @}
746 */
747
748 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
749 * @{
750 */
751 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
752 conversion trigger internal: SW start. */
753 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
754 conversion trigger from external peripheral: TIM1 TRGO.
755 Trigger edge set to rising edge (default setting). */
756 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
757 conversion trigger from external peripheral: TIM1 channel 4 event
758 (capture compare: input capture or output capture).
759 Trigger edge set to rising edge (default setting). */
760 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
761 conversion trigger from external peripheral: TIM2 TRGO.
762 Trigger edge set to rising edge (default setting). */
763 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
764 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
765 conversion trigger from external peripheral: TIM3 TRGO.
766 Trigger edge set to rising edge (default setting). */
767 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
768 conversion trigger from external peripheral: TIM15 TRGO.
769 Trigger edge set to rising edge (default setting). */
770 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
771 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
772 conversion trigger from external peripheral: TIM6 TRGO.
773 Trigger edge set to rising edge (default setting). */
774 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
775 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
776 conversion trigger from external peripheral: external interrupt line 11.
777 Trigger edge set to rising edge (default setting). */
778 /**
779 * @}
780 */
781
782 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
783 * @{
784 */
785 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
786 trigger polarity set to rising edge */
787 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
788 trigger polarity set to falling edge */
789 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
790 trigger polarity set to both rising and falling edges */
791 /**
792 * @}
793 */
794
795 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
796 * @{
797 */
798 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
799 one conversion per trigger */
800 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
801 after the first trigger, following conversions launched successively
802 automatically */
803 /**
804 * @}
805 */
806
807 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
808 * @{
809 */
810 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
811 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA,
812 in limited mode (one shot mode): DMA transfer requests are stopped when
813 number of DMA data transfers (number of ADC conversions) is reached.
814 This ADC mode is intended to be used with DMA mode non-circular. */
815 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are
816 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
817 whatever number of DMA data transferred (number of ADC conversions).
818 This ADC mode is intended to be used with DMA mode circular. */
819 /**
820 * @}
821 */
822
823 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
824 * @{
825 */
826 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
827 data preserved */
828 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
829 data overwritten */
830 /**
831 * @}
832 */
833
834 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
835 * @{
836 */
837 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable:
838 sequencer length and each rank affectation to a channel are fixed
839 by channel HW number. Refer to description of function
840 @ref LL_ADC_REG_SetSequencerChannels(). */
841 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
842 sequencer length and each rank affectation to a channel are configurable.
843 Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
844 /**
845 * @}
846 */
847
848 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
849 * @{
850 */
851 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable
852 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
853 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable
854 with 2 ranks in the sequence */
855 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable
856 with 3 ranks in the sequence */
857 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable
858 with 4 ranks in the sequence */
859 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable
860 with 5 ranks in the sequence */
861 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable
862 with 6 ranks in the sequence */
863 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable
864 with 7 ranks in the sequence */
865 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable
866 with 8 ranks in the sequence */
867 /**
868 * @}
869 */
870
871 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
872 * @{
873 */
874 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if
875 sequencer set to mode not fully configurable, refer to function
876 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
877 direction forward: from lowest channel number to highest channel number
878 (scan of all ranks, ADC conversion of ranks with channels enabled in
879 sequencer). On some other STM32 series, this setting is not available
880 and the default scan direction is forward. */
881 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
882 sequencer set to mode not fully configurable, refer to function
883 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
884 direction backward: from highest channel number to lowest channel number
885 (scan of all ranks, ADC conversion of ranks with channels enabled in
886 sequencer) */
887 /**
888 * @}
889 */
890
891 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
892 * @{
893 */
894 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
895 discontinuous mode disable */
896 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
897 discontinuous mode enable with sequence interruption every rank */
898 /**
899 * @}
900 */
901
902 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
903 * @{
904 */
905 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
906 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
907 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
908 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
909 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
910 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
911 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
912 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
913 /**
914 * @}
915 */
916
917 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
918 * @{
919 */
920 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
921 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
922 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
923 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \
924 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
925 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
926 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \
927 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
928 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \
929 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
930 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \
931 | ADC_SMPR_SMP1_1 \
932 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
933 /**
934 * @}
935 */
936
937 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
938 * @{
939 */
940 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
941 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
942 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
943 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
944 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
945 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
946 /**
947 * @}
948 */
949
950 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
951 * @{
952 */
953 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
954 disabled */
955 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
956 | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
957 of all channels, converted by group regular only */
958 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
959 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
960 of ADC channel ADCx_IN0, converted by group regular only */
961 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
962 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
963 of ADC channel ADCx_IN1, converted by group regular only */
964 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
965 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
966 of ADC channel ADCx_IN2, converted by group regular only */
967 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
968 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
969 of ADC channel ADCx_IN3, converted by group regular only */
970 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
971 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
972 of ADC channel ADCx_IN4, converted by group regular only */
973 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
974 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
975 of ADC channel ADCx_IN5, converted by group regular only */
976 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
977 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
978 of ADC channel ADCx_IN6, converted by group regular only */
979 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
980 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
981 of ADC channel ADCx_IN7, converted by group regular only */
982 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
983 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
984 of ADC channel ADCx_IN8, converted by group regular only */
985 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
986 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
987 of ADC channel ADCx_IN9, converted by group regular only */
988 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
989 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
990 of ADC channel ADCx_IN10, converted by group regular only */
991 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
992 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
993 of ADC channel ADCx_IN11, converted by group regular only */
994 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
995 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
996 of ADC channel ADCx_IN12, converted by group regular only */
997 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
998 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
999 of ADC channel ADCx_IN13, converted by group regular only */
1000 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1001 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1002 of ADC channel ADCx_IN14, converted by group regular only */
1003 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1004 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1005 of ADC channel ADCx_IN15, converted by group regular only */
1006 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1007 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1008 of ADC channel ADCx_IN16, converted by group regular only */
1009 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1010 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1011 of ADC channel ADCx_IN17, converted by group regular only */
1012 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1013 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1014 of ADC channel ADCx_IN18, converted by group regular only */
1015 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \
1016 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1017 of ADC channel ADCx_IN19, converted by group regular only */
1018 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1019 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1020 of ADC internal channel connected to VrefInt: Internal
1021 voltage reference, converted by group regular only */
1022 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1023 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1024 of ADC internal channel connected to internal temperature sensor,
1025 converted by group regular only */
1026 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1027 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1028 of ADC internal channel connected to Vbat/3: Vbat
1029 voltage through a divider ladder of factor 1/3 to have channel voltage always
1030 below Vdda, converted by group regular only */
1031 #define LL_ADC_AWD_CH_DACCH1_REG ((LL_ADC_CHANNEL_DACCH1 & ADC_CHANNEL_ID_MASK) \
1032 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1033 of ADC internal channel connected to DAC channel 1,
1034 converted by group regular only */
1035 /**
1036 * @}
1037 */
1038
1039 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1040 * @{
1041 */
1042 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */
1043 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
1044 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \
1045 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low
1046 concatenated into the same data */
1047 /**
1048 * @}
1049 */
1050
1051 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1052 * @{
1053 */
1054 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1055 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of
1056 ADC group regular. Literal suffix "continued" is kept for compatibility
1057 with other STM32 devices featuring ADC group injected, in this case other
1058 oversampling scope parameters are available. */
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1064 * @{
1065 */
1066 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1067 (all conversions of oversampling ratio are done from 1 trigger) */
1068 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous
1069 mode (each conversion of oversampling ratio needs a trigger) */
1070 /**
1071 * @}
1072 */
1073
1074 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1075 * @{
1076 */
1077 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1078 (sum of conversions data computed to result as oversampling conversion data
1079 (before potential shift) */
1080 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1081 (sum of conversions data computed to result as oversampling conversion data
1082 (before potential shift) */
1083 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1084 (sum of conversions data computed to result as oversampling conversion data
1085 (before potential shift) */
1086 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1087 (sum of conversions data computed to result as oversampling conversion data
1088 (before potential shift) */
1089 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1090 (sum of conversions data computed to result as oversampling conversion data
1091 (before potential shift) */
1092 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1093 (sum of conversions data computed to result as oversampling conversion data
1094 (before potential shift) */
1095 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1096 (sum of conversions data computed to result as oversampling conversion data
1097 (before potential shift) */
1098 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1099 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1100 (sum of conversions data computed to result as oversampling conversion data
1101 (before potential shift) */
1102 /**
1103 * @}
1104 */
1105
1106 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1107 * @{
1108 */
1109 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1110 (sum of the ADC conversions data is not divided to result as oversampling
1111 conversion data) */
1112 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1113 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1114 to result as oversampling conversion data) */
1115 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1116 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1117 to result as oversampling conversion data) */
1118 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1119 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1120 to result as oversampling conversion data) */
1121 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1122 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1123 to result as oversampling conversion data) */
1124 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1125 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1126 to result as oversampling conversion data) */
1127 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1128 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1129 to result as oversampling conversion data) */
1130 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1131 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1132 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1133 to result as oversampling conversion data) */
1134 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1135 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1136 to result as oversampling conversion data) */
1137 /**
1138 * @}
1139 */
1140
1141 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
1142 * @{
1143 */
1144 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
1145 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
1146 calibration parameters. This value is coded on 16 bits
1147 (to fit on signed word or double word) and corresponds
1148 to an inconsistent temperature value. */
1149 /**
1150 * @}
1151 */
1152
1153 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1154 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1155 * not timeout values.
1156 * For details on delays values, refer to descriptions in source code
1157 * above each literal definition.
1158 * @{
1159 */
1160
1161 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1162 /* not timeout values. */
1163 /* Timeout values for ADC operations are dependent to device clock */
1164 /* configuration (system clock versus ADC clock), */
1165 /* and therefore must be defined in user application. */
1166 /* Indications for estimation of ADC timeout delays, for this */
1167 /* STM32 series: */
1168 /* - ADC calibration time: maximum delay is 82/fADC. */
1169 /* (refer to device datasheet, parameter "tCAL") */
1170 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1171 /* (refer to device datasheet, parameter "tSTAB") */
1172 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1173 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1174 /* cycles */
1175 /* - ADC conversion time: duration depending on ADC clock and ADC */
1176 /* configuration. */
1177 /* (refer to device reference manual, section "Timing") */
1178
1179 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1180 /* Delay set to maximum value (refer to device datasheet, */
1181 /* parameter "tADCVREG_STUP"). */
1182 /* Unit: us */
1183 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
1184 regulator start-up time) */
1185
1186 /* Delay for internal voltage reference stabilization time. */
1187 /* Delay set to maximum value (refer to device datasheet, */
1188 /* parameter "tstart_vrefint"). */
1189 /* Unit: us */
1190 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
1191 time */
1192
1193 /* Delay for temperature sensor stabilization time. */
1194 /* Literal set to maximum value (refer to device datasheet, */
1195 /* parameter "tSTART"). */
1196 /* Unit: us */
1197 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time
1198 (starting from temperature sensor enable, refer to
1199 @ref LL_ADC_SetCommonPathInternalCh()) */
1200 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
1201 time (starting from ADC enable, refer to
1202 @ref LL_ADC_Enable()) */
1203
1204 /* Delay required between ADC end of calibration and ADC enable. */
1205 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1206 /* are required between ADC end of calibration and ADC enable. */
1207 /* Wait time can be computed in user application by waiting for the */
1208 /* equivalent number of CPU cycles, by taking into account */
1209 /* ratio of CPU clock versus ADC clock prescalers. */
1210 /* Unit: ADC clock cycles. */
1211 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration
1212 and ADC enable */
1213
1214 /**
1215 * @}
1216 */
1217
1218 /**
1219 * @}
1220 */
1221
1222
1223 /* Exported macro ------------------------------------------------------------*/
1224 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1225 * @{
1226 */
1227
1228 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1229 * @{
1230 */
1231
1232 /**
1233 * @brief Write a value in ADC register
1234 * @param __INSTANCE__ ADC Instance
1235 * @param __REG__ Register to be written
1236 * @param __VALUE__ Value to be written in the register
1237 * @retval None
1238 */
1239 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1240
1241 /**
1242 * @brief Read a value in ADC register
1243 * @param __INSTANCE__ ADC Instance
1244 * @param __REG__ Register to be read
1245 * @retval Register value
1246 */
1247 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1253 * @{
1254 */
1255
1256 /**
1257 * @brief Helper macro to get ADC channel number in decimal format
1258 * from literals LL_ADC_CHANNEL_x.
1259 * @note Example:
1260 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1261 * will return decimal number "4".
1262 * @note The input can be a value from functions where a channel
1263 * number is returned, either defined with number
1264 * or with bitfield (only one bit must be set).
1265 * @param __CHANNEL__ This parameter can be one of the following values:
1266 * @arg @ref LL_ADC_CHANNEL_0
1267 * @arg @ref LL_ADC_CHANNEL_1
1268 * @arg @ref LL_ADC_CHANNEL_2
1269 * @arg @ref LL_ADC_CHANNEL_3
1270 * @arg @ref LL_ADC_CHANNEL_4
1271 * @arg @ref LL_ADC_CHANNEL_5
1272 * @arg @ref LL_ADC_CHANNEL_6
1273 * @arg @ref LL_ADC_CHANNEL_7
1274 * @arg @ref LL_ADC_CHANNEL_8
1275 * @arg @ref LL_ADC_CHANNEL_9
1276 * @arg @ref LL_ADC_CHANNEL_10
1277 * @arg @ref LL_ADC_CHANNEL_11
1278 * @arg @ref LL_ADC_CHANNEL_12
1279 * @arg @ref LL_ADC_CHANNEL_13
1280 * @arg @ref LL_ADC_CHANNEL_14
1281 * @arg @ref LL_ADC_CHANNEL_15
1282 * @arg @ref LL_ADC_CHANNEL_16
1283 * @arg @ref LL_ADC_CHANNEL_17
1284 * @arg @ref LL_ADC_CHANNEL_18
1285 * @arg @ref LL_ADC_CHANNEL_19
1286 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1287 * @arg @ref LL_ADC_CHANNEL_VREFINT
1288 * @arg @ref LL_ADC_CHANNEL_VBAT
1289 * @arg @ref LL_ADC_CHANNEL_DACCH1
1290 * @retval Value between Min_Data=0 and Max_Data=18
1291 */
1292 #if defined(CORE_CM0PLUS)
1293 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1294 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1295 ( \
1296 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1297 ) \
1298 : \
1299 ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \
1300 ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \
1301 ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \
1302 ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \
1303 ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \
1304 ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \
1305 ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \
1306 ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \
1307 ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \
1308 ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \
1309 ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \
1310 ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \
1311 ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \
1312 ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \
1313 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \
1314 ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \
1315 ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \
1316 ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \
1317 (0UL))))))))))))))))))))
1318
1319 #else
1320 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1321 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1322 ( \
1323 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1324 ) \
1325 : \
1326 ( \
1327 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1328 ) \
1329 )
1330 #endif /* CORE_CM0PLUS */
1331
1332 /**
1333 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1334 * from number in decimal format.
1335 * @note Example:
1336 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1337 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1338 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1339 * @retval Returned value can be one of the following values:
1340 * @arg @ref LL_ADC_CHANNEL_0
1341 * @arg @ref LL_ADC_CHANNEL_1
1342 * @arg @ref LL_ADC_CHANNEL_2
1343 * @arg @ref LL_ADC_CHANNEL_3
1344 * @arg @ref LL_ADC_CHANNEL_4
1345 * @arg @ref LL_ADC_CHANNEL_5
1346 * @arg @ref LL_ADC_CHANNEL_6
1347 * @arg @ref LL_ADC_CHANNEL_7
1348 * @arg @ref LL_ADC_CHANNEL_8
1349 * @arg @ref LL_ADC_CHANNEL_9
1350 * @arg @ref LL_ADC_CHANNEL_10
1351 * @arg @ref LL_ADC_CHANNEL_11
1352 * @arg @ref LL_ADC_CHANNEL_12
1353 * @arg @ref LL_ADC_CHANNEL_13
1354 * @arg @ref LL_ADC_CHANNEL_14
1355 * @arg @ref LL_ADC_CHANNEL_15
1356 * @arg @ref LL_ADC_CHANNEL_16
1357 * @arg @ref LL_ADC_CHANNEL_17
1358 * @arg @ref LL_ADC_CHANNEL_18
1359 * @arg @ref LL_ADC_CHANNEL_19
1360 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1361 * @arg @ref LL_ADC_CHANNEL_VREFINT
1362 * @arg @ref LL_ADC_CHANNEL_VBAT
1363 * @arg @ref LL_ADC_CHANNEL_DACCH1
1364 */
1365 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1366 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1367 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1368
1369 /**
1370 * @brief Helper macro to determine whether the selected channel
1371 * corresponds to literal definitions of driver.
1372 * @note The different literal definitions of ADC channels are:
1373 * - ADC internal channel:
1374 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1375 * - ADC external channel (channel connected to a GPIO pin):
1376 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1377 * @note The channel parameter must be a value defined from literal
1378 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1379 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1380 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1381 * must not be a value from functions where a channel number is
1382 * returned from ADC registers,
1383 * because internal and external channels share the same channel
1384 * number in ADC registers. The differentiation is made only with
1385 * parameters definitions of driver.
1386 * @param __CHANNEL__ This parameter can be one of the following values:
1387 * @arg @ref LL_ADC_CHANNEL_0
1388 * @arg @ref LL_ADC_CHANNEL_1
1389 * @arg @ref LL_ADC_CHANNEL_2
1390 * @arg @ref LL_ADC_CHANNEL_3
1391 * @arg @ref LL_ADC_CHANNEL_4
1392 * @arg @ref LL_ADC_CHANNEL_5
1393 * @arg @ref LL_ADC_CHANNEL_6
1394 * @arg @ref LL_ADC_CHANNEL_7
1395 * @arg @ref LL_ADC_CHANNEL_8
1396 * @arg @ref LL_ADC_CHANNEL_9
1397 * @arg @ref LL_ADC_CHANNEL_10
1398 * @arg @ref LL_ADC_CHANNEL_11
1399 * @arg @ref LL_ADC_CHANNEL_12
1400 * @arg @ref LL_ADC_CHANNEL_13
1401 * @arg @ref LL_ADC_CHANNEL_14
1402 * @arg @ref LL_ADC_CHANNEL_15
1403 * @arg @ref LL_ADC_CHANNEL_16
1404 * @arg @ref LL_ADC_CHANNEL_17
1405 * @arg @ref LL_ADC_CHANNEL_18
1406 * @arg @ref LL_ADC_CHANNEL_19
1407 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1408 * @arg @ref LL_ADC_CHANNEL_VREFINT
1409 * @arg @ref LL_ADC_CHANNEL_VBAT
1410 * @arg @ref LL_ADC_CHANNEL_DACCH1
1411 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
1412 connected to a GPIO pin).
1413 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1414 */
1415 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1416 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1417
1418 /**
1419 * @brief Helper macro to convert a channel defined from parameter
1420 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1421 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1422 * to its equivalent parameter definition of a ADC external channel
1423 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1424 * @note The channel parameter can be, additionally to a value
1425 * defined from parameter definition of a ADC internal channel
1426 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1427 * a value defined from parameter definition of
1428 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1429 * or a value from functions where a channel number is returned
1430 * from ADC registers.
1431 * @param __CHANNEL__ This parameter can be one of the following values:
1432 * @arg @ref LL_ADC_CHANNEL_0
1433 * @arg @ref LL_ADC_CHANNEL_1
1434 * @arg @ref LL_ADC_CHANNEL_2
1435 * @arg @ref LL_ADC_CHANNEL_3
1436 * @arg @ref LL_ADC_CHANNEL_4
1437 * @arg @ref LL_ADC_CHANNEL_5
1438 * @arg @ref LL_ADC_CHANNEL_6
1439 * @arg @ref LL_ADC_CHANNEL_7
1440 * @arg @ref LL_ADC_CHANNEL_8
1441 * @arg @ref LL_ADC_CHANNEL_9
1442 * @arg @ref LL_ADC_CHANNEL_10
1443 * @arg @ref LL_ADC_CHANNEL_11
1444 * @arg @ref LL_ADC_CHANNEL_12
1445 * @arg @ref LL_ADC_CHANNEL_13
1446 * @arg @ref LL_ADC_CHANNEL_14
1447 * @arg @ref LL_ADC_CHANNEL_15
1448 * @arg @ref LL_ADC_CHANNEL_16
1449 * @arg @ref LL_ADC_CHANNEL_17
1450 * @arg @ref LL_ADC_CHANNEL_18
1451 * @arg @ref LL_ADC_CHANNEL_19
1452 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1453 * @arg @ref LL_ADC_CHANNEL_VREFINT
1454 * @arg @ref LL_ADC_CHANNEL_VBAT
1455 * @arg @ref LL_ADC_CHANNEL_DACCH1
1456 * @retval Returned value can be one of the following values:
1457 * @arg @ref LL_ADC_CHANNEL_0
1458 * @arg @ref LL_ADC_CHANNEL_1
1459 * @arg @ref LL_ADC_CHANNEL_2
1460 * @arg @ref LL_ADC_CHANNEL_3
1461 * @arg @ref LL_ADC_CHANNEL_4
1462 * @arg @ref LL_ADC_CHANNEL_5
1463 * @arg @ref LL_ADC_CHANNEL_6
1464 * @arg @ref LL_ADC_CHANNEL_7
1465 * @arg @ref LL_ADC_CHANNEL_8
1466 * @arg @ref LL_ADC_CHANNEL_9
1467 * @arg @ref LL_ADC_CHANNEL_10
1468 * @arg @ref LL_ADC_CHANNEL_11
1469 * @arg @ref LL_ADC_CHANNEL_12
1470 * @arg @ref LL_ADC_CHANNEL_13
1471 * @arg @ref LL_ADC_CHANNEL_14
1472 * @arg @ref LL_ADC_CHANNEL_15
1473 * @arg @ref LL_ADC_CHANNEL_16
1474 * @arg @ref LL_ADC_CHANNEL_17
1475 * @arg @ref LL_ADC_CHANNEL_18
1476 * @arg @ref LL_ADC_CHANNEL_19
1477 */
1478 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1479 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1480
1481 /**
1482 * @brief Helper macro to determine whether the internal channel
1483 * selected is available on the ADC instance selected.
1484 * @note The channel parameter must be a value defined from parameter
1485 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1486 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1487 * must not be a value defined from parameter definition of
1488 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1489 * or a value from functions where a channel number is
1490 * returned from ADC registers,
1491 * because internal and external channels share the same channel
1492 * number in ADC registers. The differentiation is made only with
1493 * parameters definitions of driver.
1494 * @param __ADC_INSTANCE__ ADC instance
1495 * @param __CHANNEL__ This parameter can be one of the following values:
1496 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1497 * @arg @ref LL_ADC_CHANNEL_VREFINT
1498 * @arg @ref LL_ADC_CHANNEL_VBAT
1499 * @arg @ref LL_ADC_CHANNEL_DACCH1
1500 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1501 * Value "1" if the internal channel selected is available on the ADC instance selected.
1502 */
1503 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1504 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1505 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1506 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1507 ((__CHANNEL__) == LL_ADC_CHANNEL_DACCH1))
1508
1509 /**
1510 * @brief Helper macro to define ADC analog watchdog parameter:
1511 * define a single channel to monitor with analog watchdog
1512 * from sequencer channel and groups definition.
1513 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1514 * Example:
1515 * LL_ADC_SetAnalogWDMonitChannels(
1516 * ADC1, LL_ADC_AWD1,
1517 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1518 * @param __CHANNEL__ This parameter can be one of the following values:
1519 * @arg @ref LL_ADC_CHANNEL_0
1520 * @arg @ref LL_ADC_CHANNEL_1
1521 * @arg @ref LL_ADC_CHANNEL_2
1522 * @arg @ref LL_ADC_CHANNEL_3
1523 * @arg @ref LL_ADC_CHANNEL_4
1524 * @arg @ref LL_ADC_CHANNEL_5
1525 * @arg @ref LL_ADC_CHANNEL_6
1526 * @arg @ref LL_ADC_CHANNEL_7
1527 * @arg @ref LL_ADC_CHANNEL_8
1528 * @arg @ref LL_ADC_CHANNEL_9
1529 * @arg @ref LL_ADC_CHANNEL_10
1530 * @arg @ref LL_ADC_CHANNEL_11
1531 * @arg @ref LL_ADC_CHANNEL_12
1532 * @arg @ref LL_ADC_CHANNEL_13
1533 * @arg @ref LL_ADC_CHANNEL_14
1534 * @arg @ref LL_ADC_CHANNEL_15
1535 * @arg @ref LL_ADC_CHANNEL_16
1536 * @arg @ref LL_ADC_CHANNEL_17
1537 * @arg @ref LL_ADC_CHANNEL_18
1538 * @arg @ref LL_ADC_CHANNEL_19
1539 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1540 * @arg @ref LL_ADC_CHANNEL_VREFINT
1541 * @arg @ref LL_ADC_CHANNEL_VBAT
1542 * @arg @ref LL_ADC_CHANNEL_DACCH1
1543 * @param __GROUP__ This parameter can be one of the following values:
1544 * @arg @ref LL_ADC_GROUP_REGULAR
1545 * @retval Returned value can be one of the following values:
1546 * @arg @ref LL_ADC_AWD_DISABLE
1547 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1548 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1549 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1550 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1551 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1552 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1553 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1554 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1555 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1556 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1557 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1558 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1559 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1560 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1561 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1562 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1563 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1564 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1565 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1566 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1567 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG
1568 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1569 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1570 * @arg @ref LL_ADC_AWD_CH_VBAT_REG
1571 * @arg @ref LL_ADC_AWD_CH_DACCH1_REG
1572 */
1573 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1574 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1575
1576 /**
1577 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1578 * or low in function of ADC resolution, when ADC resolution is
1579 * different of 12 bits.
1580 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1581 * or @ref LL_ADC_SetAnalogWDThresholds().
1582 * Example, with a ADC resolution of 8 bits, to set the value of
1583 * analog watchdog threshold high (on 8 bits):
1584 * LL_ADC_SetAnalogWDThresholds
1585 * (< ADCx param >,
1586 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1587 * );
1588 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1589 * @arg @ref LL_ADC_RESOLUTION_12B
1590 * @arg @ref LL_ADC_RESOLUTION_10B
1591 * @arg @ref LL_ADC_RESOLUTION_8B
1592 * @arg @ref LL_ADC_RESOLUTION_6B
1593 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1594 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1595 */
1596 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1597 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1598
1599 /**
1600 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1601 * or low in function of ADC resolution, when ADC resolution is
1602 * different of 12 bits.
1603 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1604 * Example, with a ADC resolution of 8 bits, to get the value of
1605 * analog watchdog threshold high (on 8 bits):
1606 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1607 * (LL_ADC_RESOLUTION_8B,
1608 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1609 * );
1610 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1611 * @arg @ref LL_ADC_RESOLUTION_12B
1612 * @arg @ref LL_ADC_RESOLUTION_10B
1613 * @arg @ref LL_ADC_RESOLUTION_8B
1614 * @arg @ref LL_ADC_RESOLUTION_6B
1615 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1616 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1617 */
1618 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1619 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1620
1621 /**
1622 * @brief Helper macro to get the ADC analog watchdog threshold high
1623 * or low from raw value containing both thresholds concatenated.
1624 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1625 * Example, to get analog watchdog threshold high from the register raw value:
1626 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1627 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1628 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1629 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1630 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1631 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1632 */
1633 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1634 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
1635 & LL_ADC_AWD_THRESHOLD_LOW)
1636
1637 /**
1638 * @brief Helper macro to select the ADC common instance
1639 * to which is belonging the selected ADC instance.
1640 * @note ADC common register instance can be used for:
1641 * - Set parameters common to several ADC instances
1642 * - Multimode (for devices with several ADC instances)
1643 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1644 * @param __ADCx__ ADC instance
1645 * @retval ADC common register instance
1646 */
1647 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1648 (ADC1_COMMON)
1649
1650 /**
1651 * @brief Helper macro to check if all ADC instances sharing the same
1652 * ADC common instance are disabled.
1653 * @note This check is required by functions with setting conditioned to
1654 * ADC state:
1655 * All ADC instances of the ADC common group must be disabled.
1656 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1657 * @note On devices with only 1 ADC common instance, parameter of this macro
1658 * is useless and can be ignored (parameter kept for compatibility
1659 * with devices featuring several ADC common instances).
1660 * @param __ADCXY_COMMON__ ADC common instance
1661 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1662 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1663 * are disabled.
1664 * Value "1" if at least one ADC instance sharing the same ADC common instance
1665 * is enabled.
1666 */
1667 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1668 LL_ADC_IsEnabled(ADC1)
1669
1670 /**
1671 * @brief Helper macro to define the ADC conversion data full-scale digital
1672 * value corresponding to the selected ADC resolution.
1673 * @note ADC conversion data full-scale corresponds to voltage range
1674 * determined by analog voltage references Vref+ and Vref-
1675 * (refer to reference manual).
1676 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1677 * @arg @ref LL_ADC_RESOLUTION_12B
1678 * @arg @ref LL_ADC_RESOLUTION_10B
1679 * @arg @ref LL_ADC_RESOLUTION_8B
1680 * @arg @ref LL_ADC_RESOLUTION_6B
1681 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1682 */
1683 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1684 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
1685
1686 /**
1687 * @brief Helper macro to convert the ADC conversion data from
1688 * a resolution to another resolution.
1689 * @param __DATA__ ADC conversion data to be converted
1690 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1691 * This parameter can be one of the following values:
1692 * @arg @ref LL_ADC_RESOLUTION_12B
1693 * @arg @ref LL_ADC_RESOLUTION_10B
1694 * @arg @ref LL_ADC_RESOLUTION_8B
1695 * @arg @ref LL_ADC_RESOLUTION_6B
1696 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1697 * This parameter can be one of the following values:
1698 * @arg @ref LL_ADC_RESOLUTION_12B
1699 * @arg @ref LL_ADC_RESOLUTION_10B
1700 * @arg @ref LL_ADC_RESOLUTION_8B
1701 * @arg @ref LL_ADC_RESOLUTION_6B
1702 * @retval ADC conversion data to the requested resolution
1703 */
1704 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1705 __ADC_RESOLUTION_CURRENT__,\
1706 __ADC_RESOLUTION_TARGET__) \
1707 (((__DATA__) \
1708 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \
1709 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \
1710 )
1711
1712 /**
1713 * @brief Helper macro to calculate the voltage (unit: mVolt)
1714 * corresponding to a ADC conversion data (unit: digital value).
1715 * @note Analog reference voltage (Vref+) must be either known from
1716 * user board environment or can be calculated using ADC measurement
1717 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1718 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1719 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1720 * (unit: digital value).
1721 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1722 * @arg @ref LL_ADC_RESOLUTION_12B
1723 * @arg @ref LL_ADC_RESOLUTION_10B
1724 * @arg @ref LL_ADC_RESOLUTION_8B
1725 * @arg @ref LL_ADC_RESOLUTION_6B
1726 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1727 */
1728 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1729 __ADC_DATA__,\
1730 __ADC_RESOLUTION__) \
1731 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1732 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1733 )
1734
1735 /**
1736 * @brief Helper macro to calculate analog reference voltage (Vref+)
1737 * (unit: mVolt) from ADC conversion data of internal voltage
1738 * reference VrefInt.
1739 * @note Computation is using VrefInt calibration value
1740 * stored in system memory for each device during production.
1741 * @note This voltage depends on user board environment: voltage level
1742 * connected to pin Vref+.
1743 * On devices with small package, the pin Vref+ is not present
1744 * and internally bonded to pin Vdda.
1745 * @note On this STM32 series, calibration data of internal voltage reference
1746 * VrefInt corresponds to a resolution of 12 bits,
1747 * this is the recommended ADC resolution to convert voltage of
1748 * internal voltage reference VrefInt.
1749 * Otherwise, this macro performs the processing to scale
1750 * ADC conversion data to 12 bits.
1751 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1752 * of internal voltage reference VrefInt (unit: digital value).
1753 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1754 * @arg @ref LL_ADC_RESOLUTION_12B
1755 * @arg @ref LL_ADC_RESOLUTION_10B
1756 * @arg @ref LL_ADC_RESOLUTION_8B
1757 * @arg @ref LL_ADC_RESOLUTION_6B
1758 * @retval Analog reference voltage (unit: mV)
1759 */
1760 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1761 __ADC_RESOLUTION__) \
1762 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1763 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1764 (__ADC_RESOLUTION__), \
1765 LL_ADC_RESOLUTION_12B) \
1766 )
1767
1768 /**
1769 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1770 * from ADC conversion data of internal temperature sensor.
1771 * @note Computation is using temperature sensor calibration values
1772 * stored in system memory for each device during production.
1773 * @note Calculation formula:
1774 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1775 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1776 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1777 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1778 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1779 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1780 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1781 * TEMP_DEGC_CAL1 (calibrated in factory)
1782 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1783 * TEMP_DEGC_CAL2 (calibrated in factory)
1784 * Caution: Calculation relevancy under reserve that calibration
1785 * parameters are correct (address and data).
1786 * To calculate temperature using temperature sensor
1787 * datasheet typical values (generic values less, therefore
1788 * less accurate than calibrated values),
1789 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1790 * @note As calculation input, the analog reference voltage (Vref+) must be
1791 * defined as it impacts the ADC LSB equivalent voltage.
1792 * @note Analog reference voltage (Vref+) must be either known from
1793 * user board environment or can be calculated using ADC measurement
1794 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1795 * @note On this STM32 series, calibration data of temperature sensor
1796 * corresponds to a resolution of 12 bits,
1797 * this is the recommended ADC resolution to convert voltage of
1798 * temperature sensor.
1799 * Otherwise, this macro performs the processing to scale
1800 * ADC conversion data to 12 bits.
1801 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1802 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1803 * temperature sensor (unit: digital value).
1804 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1805 * sensor voltage has been measured.
1806 * This parameter can be one of the following values:
1807 * @arg @ref LL_ADC_RESOLUTION_12B
1808 * @arg @ref LL_ADC_RESOLUTION_10B
1809 * @arg @ref LL_ADC_RESOLUTION_8B
1810 * @arg @ref LL_ADC_RESOLUTION_6B
1811 * @retval Temperature (unit: degree Celsius)
1812 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
1813 */
1814 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1815 __TEMPSENSOR_ADC_DATA__,\
1816 __ADC_RESOLUTION__)\
1817 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
1818 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1819 (__ADC_RESOLUTION__), \
1820 LL_ADC_RESOLUTION_12B) \
1821 * (__VREFANALOG_VOLTAGE__)) \
1822 / TEMPSENSOR_CAL_VREFANALOG) \
1823 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1824 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1825 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1826 ) + TEMPSENSOR_CAL1_TEMP \
1827 ) \
1828 : \
1829 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
1830 )
1831
1832 /**
1833 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1834 * from ADC conversion data of internal temperature sensor.
1835 * @note Computation is using temperature sensor typical values
1836 * (refer to device datasheet).
1837 * @note Calculation formula:
1838 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1839 * / Avg_Slope + CALx_TEMP
1840 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1841 * (unit: digital value)
1842 * Avg_Slope = temperature sensor slope
1843 * (unit: uV/Degree Celsius)
1844 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1845 * temperature CALx_TEMP (unit: mV)
1846 * Caution: Calculation relevancy under reserve the temperature sensor
1847 * of the current device has characteristics in line with
1848 * datasheet typical values.
1849 * If temperature sensor calibration values are available on
1850 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1851 * temperature calculation will be more accurate using
1852 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1853 * @note As calculation input, the analog reference voltage (Vref+) must be
1854 * defined as it impacts the ADC LSB equivalent voltage.
1855 * @note Analog reference voltage (Vref+) must be either known from
1856 * user board environment or can be calculated using ADC measurement
1857 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1858 * @note ADC measurement data must correspond to a resolution of 12 bits
1859 * (full scale digital value 4095). If not the case, the data must be
1860 * preliminarily rescaled to an equivalent resolution of 12 bits.
1861 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1862 (unit: uV/DegCelsius).
1863 * On this STM32 series, refer to device datasheet parameter "Avg_Slope".
1864 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
1865 (at temperature and Vref+ defined in parameters below) (unit: mV).
1866 * On this STM32 series, refer to datasheet parameter "V30" (corresponding
1867 * to TS_CAL1).
1868 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
1869 (see parameter above) is corresponding (unit: mV)
1870 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
1871 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1872 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1873 * This parameter can be one of the following values:
1874 * @arg @ref LL_ADC_RESOLUTION_12B
1875 * @arg @ref LL_ADC_RESOLUTION_10B
1876 * @arg @ref LL_ADC_RESOLUTION_8B
1877 * @arg @ref LL_ADC_RESOLUTION_6B
1878 * @retval Temperature (unit: degree Celsius)
1879 */
1880 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1881 __TEMPSENSOR_TYP_CALX_V__,\
1882 __TEMPSENSOR_CALX_TEMP__,\
1883 __VREFANALOG_VOLTAGE__,\
1884 __TEMPSENSOR_ADC_DATA__,\
1885 __ADC_RESOLUTION__) \
1886 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1887 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1888 * 1000UL) \
1889 - \
1890 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1891 * 1000UL) \
1892 ) \
1893 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1894 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1895 )
1896
1897 /**
1898 * @}
1899 */
1900
1901 /**
1902 * @}
1903 */
1904
1905
1906 /* Exported functions --------------------------------------------------------*/
1907 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1908 * @{
1909 */
1910
1911 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1912 * @{
1913 */
1914 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1915 /* configuration of ADC instance, groups and multimode (if available): */
1916 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1917
1918 /**
1919 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1920 * ADC register address from ADC instance and a list of ADC registers
1921 * intended to be used (most commonly) with DMA transfer.
1922 * @note These ADC registers are data registers:
1923 * when ADC conversion data is available in ADC data registers,
1924 * ADC generates a DMA transfer request.
1925 * @note This macro is intended to be used with LL DMA driver, refer to
1926 * function "LL_DMA_ConfigAddresses()".
1927 * Example:
1928 * LL_DMA_ConfigAddresses(DMA1,
1929 * LL_DMA_CHANNEL_1,
1930 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1931 * (uint32_t)&< array or variable >,
1932 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1933 * @note For devices with several ADC: in multimode, some devices
1934 * use a different data register outside of ADC instance scope
1935 * (common data register). This macro manages this register difference,
1936 * only ADC instance has to be set as parameter.
1937 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1938 * @param ADCx ADC instance
1939 * @param Register This parameter can be one of the following values:
1940 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1941 * @retval ADC register address
1942 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)1943 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
1944 {
1945 /* Prevent unused argument(s) compilation warning */
1946 (void)(Register);
1947
1948 /* Retrieve address of register DR */
1949 return (uint32_t) &(ADCx->DR);
1950 }
1951
1952 /**
1953 * @}
1954 */
1955
1956 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
1957 * ADC instances
1958 * @{
1959 */
1960
1961 /**
1962 * @brief Set parameter common to several ADC: Clock source and prescaler.
1963 * @note On this STM32 series, setting of this feature is conditioned to
1964 * ADC state:
1965 * All ADC instances of the ADC common group must be disabled.
1966 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1967 * ADC instance or by using helper macro helper macro
1968 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1969 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1970 * @param ADCxy_COMMON ADC common instance
1971 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1972 * @param CommonClock This parameter can be one of the following values:
1973 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1974 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1975 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1976 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1977 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1978 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1979 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1980 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1981 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1982 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1983 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1984 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1985 *
1986 * (1) ADC common clock asynchronous prescaler is applied to
1987 * each ADC instance if the corresponding ADC instance clock
1988 * is set to clock source asynchronous.
1989 * (refer to function @ref LL_ADC_SetClock() ).
1990 * @retval None
1991 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1992 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1993 {
1994 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
1995 }
1996
1997 /**
1998 * @brief Get parameter common to several ADC: Clock source and prescaler.
1999 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
2000 * @param ADCxy_COMMON ADC common instance
2001 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2002 * @retval Returned value can be one of the following values:
2003 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
2004 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
2005 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
2006 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
2007 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
2008 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
2009 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
2010 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
2011 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
2012 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
2013 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
2014 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
2015 *
2016 * (1) ADC common clock asynchronous prescaler is applied to
2017 * each ADC instance if the corresponding ADC instance clock
2018 * is set to clock source asynchronous.
2019 * (refer to function @ref LL_ADC_SetClock() ).
2020 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)2021 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
2022 {
2023 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
2024 }
2025
2026 /**
2027 * @brief Set parameter common to several ADC: measurement path to
2028 * internal channels (VrefInt, temperature sensor, ...).
2029 * Configure all paths (overwrite current configuration).
2030 * @note One or several values can be selected.
2031 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2032 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2033 * The values not selected are removed from configuration.
2034 * @note Stabilization time of measurement path to internal channel:
2035 * After enabling internal paths, before starting ADC conversion,
2036 * a delay is required for internal voltage reference and
2037 * temperature sensor stabilization time.
2038 * Refer to device datasheet.
2039 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2040 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2041 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2042 * @note ADC internal channel sampling time constraint:
2043 * For ADC conversion of internal channels,
2044 * a sampling time minimum value is required.
2045 * Refer to device datasheet.
2046 * @note On this STM32 series, setting of this feature is conditioned to
2047 * ADC state:
2048 * All ADC instances of the ADC common group must be disabled.
2049 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2050 * ADC instance or by using helper macro helper macro
2051 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2052 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2053 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2054 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2055 * @param ADCxy_COMMON ADC common instance
2056 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2057 * @param PathInternal This parameter can be a combination of the following values:
2058 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2059 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2060 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2061 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2062 * @retval None
2063 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2064 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2065 {
2066 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2067 }
2068
2069 /**
2070 * @brief Set parameter common to several ADC: measurement path to
2071 * internal channels (VrefInt, temperature sensor, ...).
2072 * Add paths to the current configuration.
2073 * @note One or several values can be selected.
2074 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2075 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2076 * @note Stabilization time of measurement path to internal channel:
2077 * After enabling internal paths, before starting ADC conversion,
2078 * a delay is required for internal voltage reference and
2079 * temperature sensor stabilization time.
2080 * Refer to device datasheet.
2081 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2082 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2083 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2084 * @note ADC internal channel sampling time constraint:
2085 * For ADC conversion of internal channels,
2086 * a sampling time minimum value is required.
2087 * Refer to device datasheet.
2088 * @note On this STM32 series, setting of this feature is conditioned to
2089 * ADC state:
2090 * All ADC instances of the ADC common group must be disabled.
2091 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2092 * ADC instance or by using helper macro helper macro
2093 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2094 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2095 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2096 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2097 * @param ADCxy_COMMON ADC common instance
2098 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2099 * @param PathInternal This parameter can be a combination of the following values:
2100 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2101 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2102 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2103 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2104 * @retval None
2105 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2106 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2107 {
2108 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2109 }
2110
2111 /**
2112 * @brief Set parameter common to several ADC: measurement path to
2113 * internal channels (VrefInt, temperature sensor, ...).
2114 * Remove paths to the current configuration.
2115 * @note One or several values can be selected.
2116 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2117 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2118 * @note On this STM32 series, setting of this feature is conditioned to
2119 * ADC state:
2120 * All ADC instances of the ADC common group must be disabled.
2121 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2122 * ADC instance or by using helper macro helper macro
2123 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2124 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2125 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2126 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2127 * @param ADCxy_COMMON ADC common instance
2128 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2129 * @param PathInternal This parameter can be a combination of the following values:
2130 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2131 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2132 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2133 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2134 * @retval None
2135 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2136 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2137 {
2138 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2139 }
2140
2141 /**
2142 * @brief Get parameter common to several ADC: measurement path to internal
2143 * channels (VrefInt, temperature sensor, ...).
2144 * @note One or several values can be selected.
2145 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2146 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2147 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2148 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2149 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2150 * @param ADCxy_COMMON ADC common instance
2151 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2152 * @retval Returned value can be a combination of the following values:
2153 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2154 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2155 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2156 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2157 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)2158 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2159 {
2160 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2161 }
2162
2163 /**
2164 * @}
2165 */
2166
2167 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2168 * @{
2169 */
2170
2171 /**
2172 * @brief Set ADC instance clock source and prescaler.
2173 * @note On this STM32 series, setting of this feature is conditioned to
2174 * ADC state:
2175 * ADC must be disabled.
2176 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
2177 * @param ADCx ADC instance
2178 * @param ClockSource This parameter can be one of the following values:
2179 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2180 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2181 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2182 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2183 *
2184 * (1) Asynchronous clock prescaler can be configured using
2185 * function @ref LL_ADC_SetCommonClock().\n
2186 * (2) Caution: This parameter has some clock ratio constraints:
2187 * This configuration must be enabled only if PCLK has a 50%
2188 * duty clock cycle (APB prescaler configured inside the RCC
2189 * must be bypassed and the system clock must by 50% duty
2190 * cycle).
2191 * Refer to reference manual.
2192 * @retval None
2193 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)2194 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
2195 {
2196 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
2197 }
2198
2199 /**
2200 * @brief Get ADC instance clock source and prescaler.
2201 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
2202 * @param ADCx ADC instance
2203 * @retval Returned value can be one of the following values:
2204 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2205 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2206 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2207 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2208 *
2209 * (1) Asynchronous clock prescaler can be retrieved using
2210 * function @ref LL_ADC_GetCommonClock().\n
2211 * (2) Caution: This parameter has some clock ratio constraints:
2212 * This configuration must be enabled only if PCLK has a 50%
2213 * duty clock cycle (APB prescaler configured inside the RCC
2214 * must be bypassed and the system clock must by 50% duty
2215 * cycle).
2216 * Refer to reference manual.
2217 */
LL_ADC_GetClock(const ADC_TypeDef * ADCx)2218 __STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx)
2219 {
2220 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
2221 }
2222
2223 /**
2224 * @brief Set ADC calibration factor in the mode single-ended
2225 * or differential (for devices with differential mode available).
2226 * @note This function is intended to set calibration parameters
2227 * without having to perform a new calibration using
2228 * @ref LL_ADC_StartCalibration().
2229 * @note On this STM32 series, setting of this feature is conditioned to
2230 * ADC state:
2231 * ADC must be enabled, without calibration on going, without conversion
2232 * on going on group regular.
2233 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
2234 * @param ADCx ADC instance
2235 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2236 * @retval None
2237 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)2238 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
2239 {
2240 MODIFY_REG(ADCx->CALFACT,
2241 ADC_CALFACT_CALFACT,
2242 CalibrationFactor);
2243 }
2244
2245 /**
2246 * @brief Get ADC calibration factor in the mode single-ended
2247 * or differential (for devices with differential mode available).
2248 * @note Calibration factors are set by hardware after performing
2249 * a calibration run using function @ref LL_ADC_StartCalibration().
2250 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
2251 * @param ADCx ADC instance
2252 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2253 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx)2254 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
2255 {
2256 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
2257 }
2258
2259 /**
2260 * @brief Set ADC resolution.
2261 * Refer to reference manual for alignments formats
2262 * dependencies to ADC resolutions.
2263 * @note On this STM32 series, setting of this feature is conditioned to
2264 * ADC state:
2265 * ADC must be disabled.
2266 * @rmtoll CFGR1 RES LL_ADC_SetResolution
2267 * @param ADCx ADC instance
2268 * @param Resolution This parameter can be one of the following values:
2269 * @arg @ref LL_ADC_RESOLUTION_12B
2270 * @arg @ref LL_ADC_RESOLUTION_10B
2271 * @arg @ref LL_ADC_RESOLUTION_8B
2272 * @arg @ref LL_ADC_RESOLUTION_6B
2273 * @retval None
2274 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2275 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2276 {
2277 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2278 }
2279
2280 /**
2281 * @brief Get ADC resolution.
2282 * Refer to reference manual for alignments formats
2283 * dependencies to ADC resolutions.
2284 * @rmtoll CFGR1 RES LL_ADC_GetResolution
2285 * @param ADCx ADC instance
2286 * @retval Returned value can be one of the following values:
2287 * @arg @ref LL_ADC_RESOLUTION_12B
2288 * @arg @ref LL_ADC_RESOLUTION_10B
2289 * @arg @ref LL_ADC_RESOLUTION_8B
2290 * @arg @ref LL_ADC_RESOLUTION_6B
2291 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)2292 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2293 {
2294 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2295 }
2296
2297 /**
2298 * @brief Set ADC conversion data alignment.
2299 * @note Refer to reference manual for alignments formats
2300 * dependencies to ADC resolutions.
2301 * @note On this STM32 series, setting of this feature is conditioned to
2302 * ADC state:
2303 * ADC must be disabled.
2304 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
2305 * @param ADCx ADC instance
2306 * @param DataAlignment This parameter can be one of the following values:
2307 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2308 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2309 * @retval None
2310 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2311 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2312 {
2313 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2314 }
2315
2316 /**
2317 * @brief Get ADC conversion data alignment.
2318 * @note Refer to reference manual for alignments formats
2319 * dependencies to ADC resolutions.
2320 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2321 * @param ADCx ADC instance
2322 * @retval Returned value can be one of the following values:
2323 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2324 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2325 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)2326 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2327 {
2328 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2329 }
2330
2331 /**
2332 * @brief Set ADC low power mode.
2333 * @note Description of ADC low power modes:
2334 * - ADC low power mode "auto wait": Dynamic low power mode,
2335 * ADC conversions occurrences are limited to the minimum necessary
2336 * in order to reduce power consumption.
2337 * New ADC conversion starts only when the previous
2338 * unitary conversion data (for ADC group regular)
2339 * has been retrieved by user software.
2340 * In the meantime, ADC remains idle: does not performs any
2341 * other conversion.
2342 * This mode allows to automatically adapt the ADC conversions
2343 * triggers to the speed of the software that reads the data.
2344 * Moreover, this avoids risk of overrun for low frequency
2345 * applications.
2346 * How to use this low power mode:
2347 * - It is not recommended to use with interruption or DMA
2348 * since these modes have to clear immediately the EOC flag
2349 * (by CPU to free the IRQ pending event or by DMA).
2350 * Auto wait will work but fort a very short time, discarding
2351 * its intended benefit (except specific case of high load of CPU
2352 * or DMA transfers which can justify usage of auto wait).
2353 * - Do use with polling: 1. Start conversion,
2354 * 2. Later on, when conversion data is needed: poll for end of
2355 * conversion to ensure that conversion is completed and
2356 * retrieve ADC conversion data. This will trig another
2357 * ADC conversion start.
2358 * - ADC low power mode "auto power-off" (feature available on
2359 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2360 * the ADC automatically powers-off after a conversion and
2361 * automatically wakes up when a new conversion is triggered
2362 * (with startup time between trigger and start of sampling).
2363 * This feature can be combined with low power mode "auto wait".
2364 * @note With ADC low power mode "auto wait", the ADC conversion data read
2365 * is corresponding to previous ADC conversion start, independently
2366 * of delay during which ADC was idle.
2367 * Therefore, the ADC conversion data may be outdated: does not
2368 * correspond to the current voltage level on the selected
2369 * ADC channel.
2370 * @note On this STM32 series, setting of this feature is conditioned to
2371 * ADC state:
2372 * ADC must be disabled.
2373 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
2374 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
2375 * @param ADCx ADC instance
2376 * @param LowPowerMode This parameter can be one of the following values:
2377 * @arg @ref LL_ADC_LP_MODE_NONE
2378 * @arg @ref LL_ADC_LP_AUTOWAIT
2379 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2380 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2381 * @retval None
2382 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2383 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2384 {
2385 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2386 }
2387
2388 /**
2389 * @brief Get ADC low power mode:
2390 * @note Description of ADC low power modes:
2391 * - ADC low power mode "auto wait": Dynamic low power mode,
2392 * ADC conversions occurrences are limited to the minimum necessary
2393 * in order to reduce power consumption.
2394 * New ADC conversion starts only when the previous
2395 * unitary conversion data (for ADC group regular)
2396 * has been retrieved by user software.
2397 * In the meantime, ADC remains idle: does not performs any
2398 * other conversion.
2399 * This mode allows to automatically adapt the ADC conversions
2400 * triggers to the speed of the software that reads the data.
2401 * Moreover, this avoids risk of overrun for low frequency
2402 * applications.
2403 * How to use this low power mode:
2404 * - It is not recommended to use with interruption or DMA
2405 * since these modes have to clear immediately the EOC flag
2406 * (by CPU to free the IRQ pending event or by DMA).
2407 * Auto wait will work but fort a very short time, discarding
2408 * its intended benefit (except specific case of high load of CPU
2409 * or DMA transfers which can justify usage of auto wait).
2410 * - Do use with polling: 1. Start conversion,
2411 * 2. Later on, when conversion data is needed: poll for end of
2412 * conversion to ensure that conversion is completed and
2413 * retrieve ADC conversion data. This will trig another
2414 * ADC conversion start.
2415 * - ADC low power mode "auto power-off" (feature available on
2416 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2417 * the ADC automatically powers-off after a conversion and
2418 * automatically wakes up when a new conversion is triggered
2419 * (with startup time between trigger and start of sampling).
2420 * This feature can be combined with low power mode "auto wait".
2421 * @note With ADC low power mode "auto wait", the ADC conversion data read
2422 * is corresponding to previous ADC conversion start, independently
2423 * of delay during which ADC was idle.
2424 * Therefore, the ADC conversion data may be outdated: does not
2425 * correspond to the current voltage level on the selected
2426 * ADC channel.
2427 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
2428 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
2429 * @param ADCx ADC instance
2430 * @retval Returned value can be one of the following values:
2431 * @arg @ref LL_ADC_LP_MODE_NONE
2432 * @arg @ref LL_ADC_LP_AUTOWAIT
2433 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2434 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2435 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)2436 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
2437 {
2438 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2439 }
2440
2441 /**
2442 * @brief Set ADC trigger frequency mode.
2443 * @note ADC trigger frequency mode must be set to low frequency when
2444 * a duration is exceeded before ADC conversion start trigger event
2445 * (between ADC enable and ADC conversion start trigger event
2446 * or between two ADC conversion start trigger event).
2447 * Duration value: Refer to device datasheet, parameter "tIdle".
2448 * @note When ADC trigger frequency mode is set to low frequency,
2449 * some rearm cycles are inserted before performing ADC conversion
2450 * start, inducing a delay of 2 ADC clock cycles.
2451 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2452 * - Low power mode auto wait: Only the first ADC conversion
2453 * start trigger inserts the rearm delay.
2454 * - Low power mode auto power-off: ADC trigger frequency mode
2455 * is discarded.
2456 * @note On this STM32 series, setting of this feature is conditioned to
2457 * ADC state:
2458 * ADC must be disabled.
2459 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2460 * @param ADCx ADC instance
2461 * @param TriggerFrequencyMode This parameter can be one of the following values:
2462 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2463 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2464 * @retval None
2465 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2466 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2467 {
2468 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2469 }
2470
2471 /**
2472 * @brief Get ADC trigger frequency mode.
2473 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2474 * @param ADCx ADC instance
2475 * @retval Returned value can be one of the following values:
2476 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2477 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2478 */
LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef * ADCx)2479 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
2480 {
2481 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2482 }
2483
2484 /**
2485 * @brief Set sampling time common to a group of channels.
2486 * @note Unit: ADC clock cycles.
2487 * @note On this STM32 series, sampling time scope is on ADC instance:
2488 * Sampling time common to all channels.
2489 * (on some other STM32 series, sampling time is channel wise)
2490 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2491 * converted:
2492 * sampling time constraints must be respected (sampling time can be
2493 * adjusted in function of ADC clock frequency and sampling time
2494 * setting).
2495 * Refer to device datasheet for timings values (parameters TS_vrefint,
2496 * TS_temp, ...).
2497 * @note Conversion time is the addition of sampling time and processing time.
2498 * On this STM32 series, ADC processing time is:
2499 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2500 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2501 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2502 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2503 * @note In case of ADC conversion of internal channel (VrefInt,
2504 * temperature sensor, ...), a sampling time minimum value
2505 * is required.
2506 * Refer to device datasheet.
2507 * @note On this STM32 series, setting of this feature is conditioned to
2508 * ADC state:
2509 * ADC must be disabled or enabled without conversion on going
2510 * on group regular.
2511 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2512 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2513 * @param ADCx ADC instance
2514 * @param SamplingTimeY This parameter can be one of the following values:
2515 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2516 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2517 * @param SamplingTime This parameter can be one of the following values:
2518 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2519 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2520 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2521 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2522 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2523 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2524 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2525 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2526 * @retval None
2527 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2528 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2529 uint32_t SamplingTime)
2530 {
2531 MODIFY_REG(ADCx->SMPR,
2532 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2533 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2534 }
2535
2536 /**
2537 * @brief Get sampling time common to a group of channels.
2538 * @note Unit: ADC clock cycles.
2539 * @note On this STM32 series, sampling time scope is on ADC instance:
2540 * Sampling time common to all channels.
2541 * (on some other STM32 series, sampling time is channel wise)
2542 * @note Conversion time is the addition of sampling time and processing time.
2543 * Refer to reference manual for ADC processing time of
2544 * this STM32 series.
2545 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2546 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2547 * @param ADCx ADC instance
2548 * @param SamplingTimeY This parameter can be one of the following values:
2549 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2550 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2551 * @retval Returned value can be one of the following values:
2552 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2553 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2554 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2555 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2556 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2557 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2558 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2559 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2560 */
LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2561 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2562 {
2563 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2564 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2565 }
2566
2567 /**
2568 * @}
2569 */
2570
2571 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2572 * @{
2573 */
2574
2575 /**
2576 * @brief Set ADC group regular conversion trigger source:
2577 * internal (SW start) or from external peripheral (timer event,
2578 * external interrupt line).
2579 * @note On this STM32 series, setting trigger source to external trigger
2580 * also set trigger polarity to rising edge
2581 * (default setting for compatibility with some ADC on other
2582 * STM32 series having this setting set by HW default value).
2583 * In case of need to modify trigger edge, use
2584 * function @ref LL_ADC_REG_SetTriggerEdge().
2585 * @note On this STM32 series, ADC trigger frequency mode must be set
2586 * in function of frequency of ADC group regular conversion trigger.
2587 * Refer to description of function
2588 * @ref LL_ADC_SetTriggerFrequencyMode().
2589 * @note Availability of parameters of trigger sources from timer
2590 * depends on timers availability on the selected device.
2591 * @note On this STM32 series, setting of this feature is conditioned to
2592 * ADC state:
2593 * ADC must be disabled.
2594 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2595 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2596 * @param ADCx ADC instance
2597 * @param TriggerSource This parameter can be one of the following values:
2598 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2599 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2600 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2601 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2602 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2603 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
2604 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2605 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2606 * @retval None
2607 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2608 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2609 {
2610 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2611 }
2612
2613 /**
2614 * @brief Get ADC group regular conversion trigger source:
2615 * internal (SW start) or from external peripheral (timer event,
2616 * external interrupt line).
2617 * @note To determine whether group regular trigger source is
2618 * internal (SW start) or external, without detail
2619 * of which peripheral is selected as external trigger,
2620 * (equivalent to
2621 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2622 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2623 * @note Availability of parameters of trigger sources from timer
2624 * depends on timers availability on the selected device.
2625 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2626 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2627 * @param ADCx ADC instance
2628 * @retval Returned value can be one of the following values:
2629 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2630 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2631 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2632 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2633 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2634 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
2635 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2636 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2637 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)2638 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
2639 {
2640 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2641
2642 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2643 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2644 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2645
2646 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2647 /* to match with triggers literals definition. */
2648 return ((trigger_source
2649 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
2650 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
2651 );
2652 }
2653
2654 /**
2655 * @brief Get ADC group regular conversion trigger source internal (SW start)
2656 * or external.
2657 * @note In case of group regular trigger source set to external trigger,
2658 * to determine which peripheral is selected as external trigger,
2659 * use function @ref LL_ADC_REG_GetTriggerSource().
2660 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2661 * @param ADCx ADC instance
2662 * @retval Value "0" if trigger source external trigger
2663 * Value "1" if trigger source SW start.
2664 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)2665 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2666 {
2667 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2668 }
2669
2670 /**
2671 * @brief Set ADC group regular conversion trigger polarity.
2672 * @note Applicable only for trigger source set to external trigger.
2673 * @note On this STM32 series, setting of this feature is conditioned to
2674 * ADC state:
2675 * ADC must be disabled.
2676 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2677 * @param ADCx ADC instance
2678 * @param ExternalTriggerEdge This parameter can be one of the following values:
2679 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2680 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2681 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2682 * @retval None
2683 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2684 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2685 {
2686 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2687 }
2688
2689 /**
2690 * @brief Get ADC group regular conversion trigger polarity.
2691 * @note Applicable only for trigger source set to external trigger.
2692 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2693 * @param ADCx ADC instance
2694 * @retval Returned value can be one of the following values:
2695 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2696 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2697 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2698 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)2699 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
2700 {
2701 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2702 }
2703
2704 /**
2705 * @brief Set ADC group regular sequencer configuration flexibility.
2706 * @note On this STM32 series, ADC group regular sequencer both modes
2707 * "fully configurable" or "not fully configurable" are
2708 * available:
2709 * - sequencer configured to fully configurable:
2710 * sequencer length and each rank
2711 * affectation to a channel are configurable.
2712 * Refer to description of function
2713 * @ref LL_ADC_REG_SetSequencerLength().
2714 * - sequencer configured to not fully configurable:
2715 * sequencer length and each rank affectation to a channel
2716 * are fixed by channel HW number.
2717 * Refer to description of function
2718 * @ref LL_ADC_REG_SetSequencerChannels().
2719 * @note On this STM32 series, after modifying sequencer (functions
2720 * @ref LL_ADC_REG_SetSequencerLength()
2721 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2722 * it is mandatory to wait for the assertion of CCRDY flag
2723 * Otherwise, some actions may be ignored.
2724 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2725 * for more details.
2726 * @note On this STM32 series, setting of this feature is conditioned to
2727 * ADC state:
2728 * ADC must be disabled.
2729 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2730 * @param ADCx ADC instance
2731 * @param Configurability This parameter can be one of the following values:
2732 * @arg @ref LL_ADC_REG_SEQ_FIXED
2733 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2734 * @retval None
2735 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2736 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2737 {
2738 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2739 }
2740
2741 /**
2742 * @brief Get ADC group regular sequencer configuration flexibility.
2743 * @note On this STM32 series, ADC group regular sequencer both modes
2744 * "fully configurable" or "not fully configurable" are
2745 * available:
2746 * - sequencer configured to fully configurable:
2747 * sequencer length and each rank
2748 * affectation to a channel are configurable.
2749 * Refer to description of function
2750 * @ref LL_ADC_REG_SetSequencerLength().
2751 * - sequencer configured to not fully configurable:
2752 * sequencer length and each rank affectation to a channel
2753 * are fixed by channel HW number.
2754 * Refer to description of function
2755 * @ref LL_ADC_REG_SetSequencerChannels().
2756 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2757 * @param ADCx ADC instance
2758 * @retval Returned value can be one of the following values:
2759 * @arg @ref LL_ADC_REG_SEQ_FIXED
2760 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2761 */
LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef * ADCx)2762 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
2763 {
2764 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2765 }
2766
2767 /**
2768 * @brief Set ADC group regular sequencer length and scan direction.
2769 * @note Description of ADC group regular sequencer features:
2770 * - For devices with sequencer fully configurable
2771 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2772 * sequencer length and each rank affectation to a channel
2773 * are configurable.
2774 * This function performs configuration of:
2775 * - Sequence length: Number of ranks in the scan sequence.
2776 * - Sequence direction: Unless specified in parameters, sequencer
2777 * scan direction is forward (from rank 1 to rank n).
2778 * Sequencer ranks are selected using
2779 * function "LL_ADC_REG_SetSequencerRanks()".
2780 * - For devices with sequencer not fully configurable
2781 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2782 * sequencer length and each rank affectation to a channel
2783 * are defined by channel number.
2784 * This function performs configuration of:
2785 * - Sequence length: Number of ranks in the scan sequence is
2786 * defined by number of channels set in the sequence,
2787 * rank of each channel is fixed by channel HW number.
2788 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2789 * - Sequence direction: Unless specified in parameters, sequencer
2790 * scan direction is forward (from lowest channel number to
2791 * highest channel number).
2792 * Sequencer ranks are selected using
2793 * function "LL_ADC_REG_SetSequencerChannels()".
2794 * To set scan direction differently, refer to function
2795 * @ref LL_ADC_REG_SetSequencerScanDirection().
2796 * @note On this STM32 series, ADC group regular sequencer both modes
2797 * "fully configurable" or "not fully configurable"
2798 * are available, they can be chosen using
2799 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2800 * @note On this STM32 series, after modifying sequencer (functions
2801 * @ref LL_ADC_REG_SetSequencerLength()
2802 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2803 * it is mandatory to wait for the assertion of CCRDY flag
2804 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2805 * Otherwise, some actions may be ignored.
2806 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2807 * for more details.
2808 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2809 * ADC conversion on only 1 channel.
2810 * @note On this STM32 series, setting of this feature is conditioned to
2811 * ADC state:
2812 * ADC must be disabled or enabled without conversion on going
2813 * on group regular.
2814 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2815 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2816 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2817 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2818 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2819 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2820 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2821 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2822 * @param ADCx ADC instance
2823 * @param SequencerNbRanks This parameter can be one of the following values:
2824 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2825 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2826 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2827 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2828 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2829 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2830 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2831 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2832 * @retval None
2833 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2834 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2835 {
2836 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2837 }
2838
2839 /**
2840 * @brief Get ADC group regular sequencer length and scan direction.
2841 * @note Description of ADC group regular sequencer features:
2842 * - For devices with sequencer fully configurable
2843 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2844 * sequencer length and each rank affectation to a channel
2845 * are configurable.
2846 * This function retrieves:
2847 * - Sequence length: Number of ranks in the scan sequence.
2848 * - Sequence direction: Unless specified in parameters, sequencer
2849 * scan direction is forward (from rank 1 to rank n).
2850 * Sequencer ranks are selected using
2851 * function "LL_ADC_REG_SetSequencerRanks()".
2852 * - For devices with sequencer not fully configurable
2853 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2854 * sequencer length and each rank affectation to a channel
2855 * are defined by channel number.
2856 * This function retrieves:
2857 * - Sequence length: Number of ranks in the scan sequence is
2858 * defined by number of channels set in the sequence,
2859 * rank of each channel is fixed by channel HW number.
2860 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2861 * - Sequence direction: Unless specified in parameters, sequencer
2862 * scan direction is forward (from lowest channel number to
2863 * highest channel number).
2864 * Sequencer ranks are selected using
2865 * function "LL_ADC_REG_SetSequencerChannels()".
2866 * To set scan direction differently, refer to function
2867 * @ref LL_ADC_REG_SetSequencerScanDirection().
2868 * @note On this STM32 series, ADC group regular sequencer both modes
2869 * "fully configurable" or "not fully configurable"
2870 * are available, they can be chosen using
2871 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2872 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2873 * ADC conversion on only 1 channel.
2874 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2875 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2876 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2877 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2878 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2879 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2880 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2881 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2882 * @param ADCx ADC instance
2883 * @retval Returned value can be one of the following values:
2884 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2885 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2886 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2887 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2888 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2889 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2890 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2891 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2892 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)2893 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
2894 {
2895 __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2896 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2897 uint32_t rank_index;
2898 uint32_t rank_shifted;
2899
2900 /* Parse register for end of sequence identifier */
2901 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
2902 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
2903 identifier (0xF) */
2904 for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U)
2905 {
2906 rank_shifted = (uint32_t)(0xF0UL << rank_index);
2907 if ((channels_ranks & rank_shifted) == rank_shifted)
2908 {
2909 sequencer_length = rank_shifted;
2910 break;
2911 }
2912 }
2913
2914 return sequencer_length;
2915 }
2916
2917 /**
2918 * @brief Set ADC group regular sequencer scan direction.
2919 * @note On this STM32 series, parameter relevant only is sequencer is set
2920 * to mode not fully configurable,
2921 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2922 * @note On some other STM32 series, this setting is not available and
2923 * the default scan direction is forward.
2924 * @note On this STM32 series, after modifying sequencer (functions
2925 * @ref LL_ADC_REG_SetSequencerLength()
2926 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2927 * it is mandatory to wait for the assertion of CCRDY flag
2928 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2929 * Otherwise, some actions may be ignored.
2930 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2931 * for more details.
2932 * @note On this STM32 series, setting of this feature is conditioned to
2933 * ADC state:
2934 * ADC must be disabled.
2935 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2936 * @param ADCx ADC instance
2937 * @param ScanDirection This parameter can be one of the following values:
2938 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2939 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2940 * @retval None
2941 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2942 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2943 {
2944 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2945 }
2946
2947 /**
2948 * @brief Get ADC group regular sequencer scan direction.
2949 * @note On this STM32 series, parameter relevant only is sequencer is set
2950 * to mode not fully configurable,
2951 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2952 * @note On some other STM32 series, this setting is not available and
2953 * the default scan direction is forward.
2954 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2955 * @param ADCx ADC instance
2956 * @retval Returned value can be one of the following values:
2957 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2958 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2959 */
LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * ADCx)2960 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
2961 {
2962 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2963 }
2964
2965 /**
2966 * @brief Set ADC group regular sequencer discontinuous mode:
2967 * sequence subdivided and scan conversions interrupted every selected
2968 * number of ranks.
2969 * @note It is not possible to enable both ADC group regular
2970 * continuous mode and sequencer discontinuous mode.
2971 * @note On this STM32 series, setting of this feature is conditioned to
2972 * ADC state:
2973 * ADC must be disabled.
2974 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2975 * @param ADCx ADC instance
2976 * @param SeqDiscont This parameter can be one of the following values:
2977 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2978 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2979 * @retval None
2980 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2981 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2982 {
2983 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2984 }
2985
2986 /**
2987 * @brief Get ADC group regular sequencer discontinuous mode:
2988 * sequence subdivided and scan conversions interrupted every selected
2989 * number of ranks.
2990 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2991 * @param ADCx ADC instance
2992 * @retval Returned value can be one of the following values:
2993 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2994 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2995 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)2996 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2997 {
2998 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2999 }
3000
3001 /**
3002 * @brief Set ADC group regular sequence: channel on the selected
3003 * scan sequence rank.
3004 * @note This function performs configuration of:
3005 * - Channels ordering into each rank of scan sequence:
3006 * whatever channel can be placed into whatever rank.
3007 * @note On this STM32 series, ADC group regular sequencer is
3008 * fully configurable: sequencer length and each rank
3009 * affectation to a channel are configurable.
3010 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3011 * @note Depending on devices and packages, some channels may not be available.
3012 * Refer to device datasheet for channels availability.
3013 * @note On this STM32 series, to measure internal channels (VrefInt,
3014 * TempSensor, ...), measurement paths to internal channels must be
3015 * enabled separately.
3016 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3017 * @note On this STM32 series, after modifying sequencer (functions
3018 * @ref LL_ADC_REG_SetSequencerLength()
3019 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3020 * it is mandatory to wait for the assertion of CCRDY flag
3021 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3022 * Otherwise, some actions may be ignored.
3023 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3024 * for more details.
3025 * @note On this STM32 series, setting of this feature is conditioned to
3026 * ADC state:
3027 * ADC must be disabled or enabled without conversion on going
3028 * on group regular.
3029 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
3030 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
3031 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
3032 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
3033 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
3034 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
3035 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
3036 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
3037 * @param ADCx ADC instance
3038 * @param Rank This parameter can be one of the following values:
3039 * @arg @ref LL_ADC_REG_RANK_1
3040 * @arg @ref LL_ADC_REG_RANK_2
3041 * @arg @ref LL_ADC_REG_RANK_3
3042 * @arg @ref LL_ADC_REG_RANK_4
3043 * @arg @ref LL_ADC_REG_RANK_5
3044 * @arg @ref LL_ADC_REG_RANK_6
3045 * @arg @ref LL_ADC_REG_RANK_7
3046 * @arg @ref LL_ADC_REG_RANK_8
3047 * @param Channel This parameter can be one of the following values:
3048 * @arg @ref LL_ADC_CHANNEL_0
3049 * @arg @ref LL_ADC_CHANNEL_1
3050 * @arg @ref LL_ADC_CHANNEL_2
3051 * @arg @ref LL_ADC_CHANNEL_3
3052 * @arg @ref LL_ADC_CHANNEL_4
3053 * @arg @ref LL_ADC_CHANNEL_5
3054 * @arg @ref LL_ADC_CHANNEL_6
3055 * @arg @ref LL_ADC_CHANNEL_7
3056 * @arg @ref LL_ADC_CHANNEL_8
3057 * @arg @ref LL_ADC_CHANNEL_9
3058 * @arg @ref LL_ADC_CHANNEL_10
3059 * @arg @ref LL_ADC_CHANNEL_11
3060 * @arg @ref LL_ADC_CHANNEL_12
3061 * @arg @ref LL_ADC_CHANNEL_13
3062 * @arg @ref LL_ADC_CHANNEL_14
3063 * @arg @ref LL_ADC_CHANNEL_15
3064 * @arg @ref LL_ADC_CHANNEL_16
3065 * @arg @ref LL_ADC_CHANNEL_17
3066 * @arg @ref LL_ADC_CHANNEL_18
3067 * @arg @ref LL_ADC_CHANNEL_19
3068 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3069 * @arg @ref LL_ADC_CHANNEL_VREFINT
3070 * @arg @ref LL_ADC_CHANNEL_VBAT
3071 * @arg @ref LL_ADC_CHANNEL_DACCH1
3072 * @retval None
3073 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3074 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3075 {
3076 /* Set bits with content of parameter "Channel" with bits position */
3077 /* in register depending on parameter "Rank". */
3078 /* Parameters "Rank" and "Channel" are used with masks because containing */
3079 /* other bits reserved for other purpose. */
3080 MODIFY_REG(ADCx->CHSELR,
3081 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3082 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3083 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3084 }
3085
3086 /**
3087 * @brief Get ADC group regular sequence: channel on the selected
3088 * scan sequence rank.
3089 * @note On this STM32 series, ADC group regular sequencer is
3090 * fully configurable: sequencer length and each rank
3091 * affectation to a channel are configurable.
3092 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3093 * @note Depending on devices and packages, some channels may not be available.
3094 * Refer to device datasheet for channels availability.
3095 * @note Usage of the returned channel number:
3096 * - To reinject this channel into another function LL_ADC_xxx:
3097 * the returned channel number is only partly formatted on definition
3098 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3099 * with parts of literals LL_ADC_CHANNEL_x or using
3100 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3101 * Then the selected literal LL_ADC_CHANNEL_x can be used
3102 * as parameter for another function.
3103 * - To get the channel number in decimal format:
3104 * process the returned value with the helper macro
3105 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3106 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
3107 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
3108 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
3109 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
3110 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
3111 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
3112 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
3113 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
3114 * @param ADCx ADC instance
3115 * @param Rank This parameter can be one of the following values:
3116 * @arg @ref LL_ADC_REG_RANK_1
3117 * @arg @ref LL_ADC_REG_RANK_2
3118 * @arg @ref LL_ADC_REG_RANK_3
3119 * @arg @ref LL_ADC_REG_RANK_4
3120 * @arg @ref LL_ADC_REG_RANK_5
3121 * @arg @ref LL_ADC_REG_RANK_6
3122 * @arg @ref LL_ADC_REG_RANK_7
3123 * @arg @ref LL_ADC_REG_RANK_8
3124 * @retval Returned value can be one of the following values:
3125 * @arg @ref LL_ADC_CHANNEL_0
3126 * @arg @ref LL_ADC_CHANNEL_1
3127 * @arg @ref LL_ADC_CHANNEL_2
3128 * @arg @ref LL_ADC_CHANNEL_3
3129 * @arg @ref LL_ADC_CHANNEL_4
3130 * @arg @ref LL_ADC_CHANNEL_5
3131 * @arg @ref LL_ADC_CHANNEL_6
3132 * @arg @ref LL_ADC_CHANNEL_7
3133 * @arg @ref LL_ADC_CHANNEL_8
3134 * @arg @ref LL_ADC_CHANNEL_9
3135 * @arg @ref LL_ADC_CHANNEL_10
3136 * @arg @ref LL_ADC_CHANNEL_11
3137 * @arg @ref LL_ADC_CHANNEL_12
3138 * @arg @ref LL_ADC_CHANNEL_13
3139 * @arg @ref LL_ADC_CHANNEL_14
3140 * @arg @ref LL_ADC_CHANNEL_15
3141 * @arg @ref LL_ADC_CHANNEL_16
3142 * @arg @ref LL_ADC_CHANNEL_17
3143 * @arg @ref LL_ADC_CHANNEL_18
3144 * @arg @ref LL_ADC_CHANNEL_19
3145 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3146 * @arg @ref LL_ADC_CHANNEL_VREFINT
3147 * @arg @ref LL_ADC_CHANNEL_VBAT
3148 * @arg @ref LL_ADC_CHANNEL_DACCH1
3149 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)3150 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
3151 {
3152 return (uint32_t)((READ_BIT(ADCx->CHSELR,
3153 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3154 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
3155 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3156 );
3157 }
3158
3159 /**
3160 * @brief Set ADC group regular sequence: channel on rank corresponding to
3161 * channel number.
3162 * @note This function performs:
3163 * - Channels ordering into each rank of scan sequence:
3164 * rank of each channel is fixed by channel HW number
3165 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3166 * - Set channels selected by overwriting the current sequencer
3167 * configuration.
3168 * @note On this STM32 series, ADC group regular sequencer both modes
3169 * "fully configurable" or "not fully configurable"
3170 * are available, they can be chosen using
3171 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3172 * This function can be used with setting "not fully configurable".
3173 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3174 * and @ref LL_ADC_REG_SetSequencerLength().
3175 * @note On this STM32 series, after modifying sequencer (functions
3176 * @ref LL_ADC_REG_SetSequencerLength()
3177 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3178 * it is mandatory to wait for the assertion of CCRDY flag
3179 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3180 * Otherwise, some actions may be ignored.
3181 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3182 * for more details.
3183 * @note Depending on devices and packages, some channels may not be available.
3184 * Refer to device datasheet for channels availability.
3185 * @note On this STM32 series, to measure internal channels (VrefInt,
3186 * TempSensor, ...), measurement paths to internal channels must be
3187 * enabled separately.
3188 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3189 * @note On this STM32 series, setting of this feature is conditioned to
3190 * ADC state:
3191 * ADC must be disabled or enabled without conversion on going
3192 * on group regular.
3193 * @note One or several values can be selected.
3194 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3195 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
3196 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
3197 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
3198 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
3199 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
3200 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
3201 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
3202 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
3203 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
3204 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
3205 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
3206 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
3207 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
3208 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
3209 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
3210 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
3211 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
3212 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
3213 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
3214 * @param ADCx ADC instance
3215 * @param Channel This parameter can be a combination of the following values:
3216 * @arg @ref LL_ADC_CHANNEL_0
3217 * @arg @ref LL_ADC_CHANNEL_1
3218 * @arg @ref LL_ADC_CHANNEL_2
3219 * @arg @ref LL_ADC_CHANNEL_3
3220 * @arg @ref LL_ADC_CHANNEL_4
3221 * @arg @ref LL_ADC_CHANNEL_5
3222 * @arg @ref LL_ADC_CHANNEL_6
3223 * @arg @ref LL_ADC_CHANNEL_7
3224 * @arg @ref LL_ADC_CHANNEL_8
3225 * @arg @ref LL_ADC_CHANNEL_9
3226 * @arg @ref LL_ADC_CHANNEL_10
3227 * @arg @ref LL_ADC_CHANNEL_11
3228 * @arg @ref LL_ADC_CHANNEL_12
3229 * @arg @ref LL_ADC_CHANNEL_13
3230 * @arg @ref LL_ADC_CHANNEL_14
3231 * @arg @ref LL_ADC_CHANNEL_15
3232 * @arg @ref LL_ADC_CHANNEL_16
3233 * @arg @ref LL_ADC_CHANNEL_17
3234 * @arg @ref LL_ADC_CHANNEL_18
3235 * @arg @ref LL_ADC_CHANNEL_19
3236 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3237 * @arg @ref LL_ADC_CHANNEL_VREFINT
3238 * @arg @ref LL_ADC_CHANNEL_VBAT
3239 * @arg @ref LL_ADC_CHANNEL_DACCH1
3240 * @retval None
3241 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)3242 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
3243 {
3244 /* Parameter "Channel" is used with masks because containing */
3245 /* other bits reserved for other purpose. */
3246 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3247 }
3248
3249 /**
3250 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
3251 * channel number.
3252 * @note This function performs:
3253 * - Channels ordering into each rank of scan sequence:
3254 * rank of each channel is fixed by channel HW number
3255 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3256 * - Set channels selected by adding them to the current sequencer
3257 * configuration.
3258 * @note On this STM32 series, ADC group regular sequencer both modes
3259 * "fully configurable" or "not fully configurable"
3260 * are available, they can be chosen using
3261 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3262 * This function can be used with setting "not fully configurable".
3263 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3264 * and @ref LL_ADC_REG_SetSequencerLength().
3265 * @note On this STM32 series, after modifying sequencer (functions
3266 * @ref LL_ADC_REG_SetSequencerLength()
3267 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3268 * it is mandatory to wait for the assertion of CCRDY flag
3269 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3270 * Otherwise, some actions may be ignored.
3271 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3272 * for more details.
3273 * @note Depending on devices and packages, some channels may not be available.
3274 * Refer to device datasheet for channels availability.
3275 * @note On this STM32 series, to measure internal channels (VrefInt,
3276 * TempSensor, ...), measurement paths to internal channels must be
3277 * enabled separately.
3278 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3279 * @note On this STM32 series, setting of this feature is conditioned to
3280 * ADC state:
3281 * ADC must be disabled or enabled without conversion on going
3282 * on group regular.
3283 * @note One or several values can be selected.
3284 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3285 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
3286 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
3287 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
3288 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
3289 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
3290 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
3291 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
3292 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
3293 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
3294 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
3295 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3296 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3297 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3298 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3299 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3300 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3301 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3302 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3303 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3304 * @param ADCx ADC instance
3305 * @param Channel This parameter can be a combination of the following values:
3306 * @arg @ref LL_ADC_CHANNEL_0
3307 * @arg @ref LL_ADC_CHANNEL_1
3308 * @arg @ref LL_ADC_CHANNEL_2
3309 * @arg @ref LL_ADC_CHANNEL_3
3310 * @arg @ref LL_ADC_CHANNEL_4
3311 * @arg @ref LL_ADC_CHANNEL_5
3312 * @arg @ref LL_ADC_CHANNEL_6
3313 * @arg @ref LL_ADC_CHANNEL_7
3314 * @arg @ref LL_ADC_CHANNEL_8
3315 * @arg @ref LL_ADC_CHANNEL_9
3316 * @arg @ref LL_ADC_CHANNEL_10
3317 * @arg @ref LL_ADC_CHANNEL_11
3318 * @arg @ref LL_ADC_CHANNEL_12
3319 * @arg @ref LL_ADC_CHANNEL_13
3320 * @arg @ref LL_ADC_CHANNEL_14
3321 * @arg @ref LL_ADC_CHANNEL_15
3322 * @arg @ref LL_ADC_CHANNEL_16
3323 * @arg @ref LL_ADC_CHANNEL_17
3324 * @arg @ref LL_ADC_CHANNEL_18
3325 * @arg @ref LL_ADC_CHANNEL_19
3326 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3327 * @arg @ref LL_ADC_CHANNEL_VREFINT
3328 * @arg @ref LL_ADC_CHANNEL_VBAT
3329 * @arg @ref LL_ADC_CHANNEL_DACCH1
3330 * @retval None
3331 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3332 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3333 {
3334 /* Parameter "Channel" is used with masks because containing */
3335 /* other bits reserved for other purpose. */
3336 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3337 }
3338
3339 /**
3340 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3341 * channel number.
3342 * @note This function performs:
3343 * - Channels ordering into each rank of scan sequence:
3344 * rank of each channel is fixed by channel HW number
3345 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3346 * - Set channels selected by removing them to the current sequencer
3347 * configuration.
3348 * @note On this STM32 series, ADC group regular sequencer both modes
3349 * "fully configurable" or "not fully configurable"
3350 * are available, they can be chosen using
3351 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3352 * This function can be used with setting "not fully configurable".
3353 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3354 * and @ref LL_ADC_REG_SetSequencerLength().
3355 * @note On this STM32 series, after modifying sequencer (functions
3356 * @ref LL_ADC_REG_SetSequencerLength()
3357 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3358 * it is mandatory to wait for the assertion of CCRDY flag
3359 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3360 * Otherwise, some actions may be ignored.
3361 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3362 * for more details.
3363 * @note Depending on devices and packages, some channels may not be available.
3364 * Refer to device datasheet for channels availability.
3365 * @note On this STM32 series, to measure internal channels (VrefInt,
3366 * TempSensor, ...), measurement paths to internal channels must be
3367 * enabled separately.
3368 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3369 * @note On this STM32 series, setting of this feature is conditioned to
3370 * ADC state:
3371 * ADC must be disabled or enabled without conversion on going
3372 * on group regular.
3373 * @note One or several values can be selected.
3374 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3375 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3376 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3377 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3378 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3379 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3380 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3381 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3382 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3383 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3384 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3385 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3386 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3387 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3388 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3389 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3390 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3391 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3392 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3393 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3394 * @param ADCx ADC instance
3395 * @param Channel This parameter can be a combination of the following values:
3396 * @arg @ref LL_ADC_CHANNEL_0
3397 * @arg @ref LL_ADC_CHANNEL_1
3398 * @arg @ref LL_ADC_CHANNEL_2
3399 * @arg @ref LL_ADC_CHANNEL_3
3400 * @arg @ref LL_ADC_CHANNEL_4
3401 * @arg @ref LL_ADC_CHANNEL_5
3402 * @arg @ref LL_ADC_CHANNEL_6
3403 * @arg @ref LL_ADC_CHANNEL_7
3404 * @arg @ref LL_ADC_CHANNEL_8
3405 * @arg @ref LL_ADC_CHANNEL_9
3406 * @arg @ref LL_ADC_CHANNEL_10
3407 * @arg @ref LL_ADC_CHANNEL_11
3408 * @arg @ref LL_ADC_CHANNEL_12
3409 * @arg @ref LL_ADC_CHANNEL_13
3410 * @arg @ref LL_ADC_CHANNEL_14
3411 * @arg @ref LL_ADC_CHANNEL_15
3412 * @arg @ref LL_ADC_CHANNEL_16
3413 * @arg @ref LL_ADC_CHANNEL_17
3414 * @arg @ref LL_ADC_CHANNEL_18
3415 * @arg @ref LL_ADC_CHANNEL_19
3416 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3417 * @arg @ref LL_ADC_CHANNEL_VREFINT
3418 * @arg @ref LL_ADC_CHANNEL_VBAT
3419 * @arg @ref LL_ADC_CHANNEL_DACCH1
3420 * @retval None
3421 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3422 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3423 {
3424 /* Parameter "Channel" is used with masks because containing */
3425 /* other bits reserved for other purpose. */
3426 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3427 }
3428
3429 /**
3430 * @brief Get ADC group regular sequence: channel on rank corresponding to
3431 * channel number.
3432 * @note This function performs:
3433 * - Channels order reading into each rank of scan sequence:
3434 * rank of each channel is fixed by channel HW number
3435 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3436 * @note On this STM32 series, ADC group regular sequencer both modes
3437 * "fully configurable" or "not fully configurable"
3438 * are available, they can be chosen using
3439 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3440 * This function can be used with setting "not fully configurable".
3441 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3442 * and @ref LL_ADC_REG_SetSequencerLength().
3443 * @note Depending on devices and packages, some channels may not be available.
3444 * Refer to device datasheet for channels availability.
3445 * @note On this STM32 series, to measure internal channels (VrefInt,
3446 * TempSensor, ...), measurement paths to internal channels must be
3447 * enabled separately.
3448 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3449 * @note On this STM32 series, setting of this feature is conditioned to
3450 * ADC state:
3451 * ADC must be disabled or enabled without conversion on going
3452 * on group regular.
3453 * @note One or several values can be retrieved.
3454 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3455 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3456 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3457 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3458 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3459 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3460 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3461 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3462 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3463 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3464 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3465 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3466 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3467 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3468 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3469 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3470 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3471 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3472 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3473 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3474 * @param ADCx ADC instance
3475 * @retval Returned value can be a combination of the following values:
3476 * @arg @ref LL_ADC_CHANNEL_0
3477 * @arg @ref LL_ADC_CHANNEL_1
3478 * @arg @ref LL_ADC_CHANNEL_2
3479 * @arg @ref LL_ADC_CHANNEL_3
3480 * @arg @ref LL_ADC_CHANNEL_4
3481 * @arg @ref LL_ADC_CHANNEL_5
3482 * @arg @ref LL_ADC_CHANNEL_6
3483 * @arg @ref LL_ADC_CHANNEL_7
3484 * @arg @ref LL_ADC_CHANNEL_8
3485 * @arg @ref LL_ADC_CHANNEL_9
3486 * @arg @ref LL_ADC_CHANNEL_10
3487 * @arg @ref LL_ADC_CHANNEL_11
3488 * @arg @ref LL_ADC_CHANNEL_12
3489 * @arg @ref LL_ADC_CHANNEL_13
3490 * @arg @ref LL_ADC_CHANNEL_14
3491 * @arg @ref LL_ADC_CHANNEL_15
3492 * @arg @ref LL_ADC_CHANNEL_16
3493 * @arg @ref LL_ADC_CHANNEL_17
3494 * @arg @ref LL_ADC_CHANNEL_18
3495 * @arg @ref LL_ADC_CHANNEL_19
3496 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3497 * @arg @ref LL_ADC_CHANNEL_VREFINT
3498 * @arg @ref LL_ADC_CHANNEL_VBAT
3499 * @arg @ref LL_ADC_CHANNEL_DACCH1
3500 */
LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef * ADCx)3501 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
3502 {
3503 uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3504
3505 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3506 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3507 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3508 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3509 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3510 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3511 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3512 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3513 | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
3514 | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
3515 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3516 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3517 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3518 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3519 | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
3520 | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
3521 | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
3522 | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
3523 | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
3524 | (((channels_bitfield & ADC_CHSELR_CHSEL19) >> ADC_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
3525 );
3526 }
3527
3528 /**
3529 * @brief Set ADC continuous conversion mode on ADC group regular.
3530 * @note Description of ADC continuous conversion mode:
3531 * - single mode: one conversion per trigger
3532 * - continuous mode: after the first trigger, following
3533 * conversions launched successively automatically.
3534 * @note It is not possible to enable both ADC group regular
3535 * continuous mode and sequencer discontinuous mode.
3536 * @note On this STM32 series, setting of this feature is conditioned to
3537 * ADC state:
3538 * ADC must be disabled.
3539 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3540 * @param ADCx ADC instance
3541 * @param Continuous This parameter can be one of the following values:
3542 * @arg @ref LL_ADC_REG_CONV_SINGLE
3543 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3544 * @retval None
3545 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3546 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3547 {
3548 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3549 }
3550
3551 /**
3552 * @brief Get ADC continuous conversion mode on ADC group regular.
3553 * @note Description of ADC continuous conversion mode:
3554 * - single mode: one conversion per trigger
3555 * - continuous mode: after the first trigger, following
3556 * conversions launched successively automatically.
3557 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3558 * @param ADCx ADC instance
3559 * @retval Returned value can be one of the following values:
3560 * @arg @ref LL_ADC_REG_CONV_SINGLE
3561 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3562 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)3563 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
3564 {
3565 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3566 }
3567
3568 /**
3569 * @brief Set ADC group regular conversion data transfer: no transfer or
3570 * transfer by DMA, and DMA requests mode.
3571 * @note If transfer by DMA selected, specifies the DMA requests
3572 * mode:
3573 * - Limited mode (One shot mode): DMA transfer requests are stopped
3574 * when number of DMA data transfers (number of
3575 * ADC conversions) is reached.
3576 * This ADC mode is intended to be used with DMA mode non-circular.
3577 * - Unlimited mode: DMA transfer requests are unlimited,
3578 * whatever number of DMA data transfers (number of
3579 * ADC conversions).
3580 * This ADC mode is intended to be used with DMA mode circular.
3581 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3582 * mode non-circular:
3583 * when DMA transfers size will be reached, DMA will stop transfers of
3584 * ADC conversions data ADC will raise an overrun error
3585 * (overrun flag and interruption if enabled).
3586 * @note To configure DMA source address (peripheral address),
3587 * use function @ref LL_ADC_DMA_GetRegAddr().
3588 * @note On this STM32 series, setting of this feature is conditioned to
3589 * ADC state:
3590 * ADC must be disabled.
3591 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3592 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3593 * @param ADCx ADC instance
3594 * @param DMATransfer This parameter can be one of the following values:
3595 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3596 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3597 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3598 * @retval None
3599 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3600 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3601 {
3602 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3603 }
3604
3605 /**
3606 * @brief Get ADC group regular conversion data transfer: no transfer or
3607 * transfer by DMA, and DMA requests mode.
3608 * @note If transfer by DMA selected, specifies the DMA requests
3609 * mode:
3610 * - Limited mode (One shot mode): DMA transfer requests are stopped
3611 * when number of DMA data transfers (number of
3612 * ADC conversions) is reached.
3613 * This ADC mode is intended to be used with DMA mode non-circular.
3614 * - Unlimited mode: DMA transfer requests are unlimited,
3615 * whatever number of DMA data transfers (number of
3616 * ADC conversions).
3617 * This ADC mode is intended to be used with DMA mode circular.
3618 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3619 * mode non-circular:
3620 * when DMA transfers size will be reached, DMA will stop transfers of
3621 * ADC conversions data ADC will raise an overrun error
3622 * (overrun flag and interruption if enabled).
3623 * @note To configure DMA source address (peripheral address),
3624 * use function @ref LL_ADC_DMA_GetRegAddr().
3625 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3626 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3627 * @param ADCx ADC instance
3628 * @retval Returned value can be one of the following values:
3629 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3630 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3631 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3632 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)3633 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
3634 {
3635 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3636 }
3637
3638 /**
3639 * @brief Set ADC group regular behavior in case of overrun:
3640 * data preserved or overwritten.
3641 * @note Compatibility with devices without feature overrun:
3642 * other devices without this feature have a behavior
3643 * equivalent to data overwritten.
3644 * The default setting of overrun is data preserved.
3645 * Therefore, for compatibility with all devices, parameter
3646 * overrun should be set to data overwritten.
3647 * @note On this STM32 series, setting of this feature is conditioned to
3648 * ADC state:
3649 * ADC must be disabled.
3650 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3651 * @param ADCx ADC instance
3652 * @param Overrun This parameter can be one of the following values:
3653 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3654 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3655 * @retval None
3656 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3657 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3658 {
3659 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3660 }
3661
3662 /**
3663 * @brief Get ADC group regular behavior in case of overrun:
3664 * data preserved or overwritten.
3665 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3666 * @param ADCx ADC instance
3667 * @retval Returned value can be one of the following values:
3668 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3669 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3670 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)3671 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
3672 {
3673 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3674 }
3675
3676 /**
3677 * @}
3678 */
3679
3680 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3681 * @{
3682 */
3683
3684 /**
3685 * @brief Set sampling time of the selected ADC channel
3686 * Unit: ADC clock cycles.
3687 * @note On this device, sampling time is on channel scope: independently
3688 * of channel mapped on ADC group regular or injected.
3689 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3690 * converted:
3691 * sampling time constraints must be respected (sampling time can be
3692 * adjusted in function of ADC clock frequency and sampling time
3693 * setting).
3694 * Refer to device datasheet for timings values (parameters TS_vrefint,
3695 * TS_temp, ...).
3696 * @note Conversion time is the addition of sampling time and processing time.
3697 * Refer to reference manual for ADC processing time of
3698 * this STM32 series.
3699 * @note In case of ADC conversion of internal channel (VrefInt,
3700 * temperature sensor, ...), a sampling time minimum value
3701 * is required.
3702 * Refer to device datasheet.
3703 * @note On this STM32 series, setting of this feature is conditioned to
3704 * ADC state:
3705 * ADC must be disabled or enabled without conversion on going
3706 * on group regular.
3707 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3708 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3709 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3710 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3711 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3712 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3713 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3714 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3715 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3716 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3717 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3718 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3719 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3720 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3721 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3722 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3723 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3724 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3725 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3726 * @param ADCx ADC instance
3727 * @param Channel This parameter can be a combination of the following values:
3728 * @arg @ref LL_ADC_CHANNEL_0
3729 * @arg @ref LL_ADC_CHANNEL_1
3730 * @arg @ref LL_ADC_CHANNEL_2
3731 * @arg @ref LL_ADC_CHANNEL_3
3732 * @arg @ref LL_ADC_CHANNEL_4
3733 * @arg @ref LL_ADC_CHANNEL_5
3734 * @arg @ref LL_ADC_CHANNEL_6
3735 * @arg @ref LL_ADC_CHANNEL_7
3736 * @arg @ref LL_ADC_CHANNEL_8
3737 * @arg @ref LL_ADC_CHANNEL_9
3738 * @arg @ref LL_ADC_CHANNEL_10
3739 * @arg @ref LL_ADC_CHANNEL_11
3740 * @arg @ref LL_ADC_CHANNEL_12
3741 * @arg @ref LL_ADC_CHANNEL_13
3742 * @arg @ref LL_ADC_CHANNEL_14
3743 * @arg @ref LL_ADC_CHANNEL_15
3744 * @arg @ref LL_ADC_CHANNEL_16
3745 * @arg @ref LL_ADC_CHANNEL_17
3746 * @arg @ref LL_ADC_CHANNEL_18
3747 * @arg @ref LL_ADC_CHANNEL_19
3748 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3749 * @arg @ref LL_ADC_CHANNEL_VREFINT
3750 * @arg @ref LL_ADC_CHANNEL_VBAT
3751 * @arg @ref LL_ADC_CHANNEL_DACCH1
3752 * @param SamplingTimeY This parameter can be one of the following values:
3753 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3754 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3755 * @retval None
3756 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3757 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3758 {
3759 /* Parameter "Channel" is used with masks because containing */
3760 /* other bits reserved for other purpose. */
3761 MODIFY_REG(ADCx->SMPR,
3762 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3763 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3764 );
3765 }
3766
3767 /**
3768 * @brief Get sampling time of the selected ADC channel
3769 * Unit: ADC clock cycles.
3770 * @note On this device, sampling time is on channel scope: independently
3771 * of channel mapped on ADC group regular or injected.
3772 * @note Conversion time is the addition of sampling time and processing time.
3773 * Refer to reference manual for ADC processing time of
3774 * this STM32 series.
3775 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3776 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3777 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3778 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3779 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3780 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3781 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3782 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3783 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3784 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3785 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3786 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3787 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3788 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3789 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3790 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3791 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3792 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3793 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3794 * @param ADCx ADC instance
3795 * @param Channel This parameter can be one of the following values:
3796 * @arg @ref LL_ADC_CHANNEL_0
3797 * @arg @ref LL_ADC_CHANNEL_1
3798 * @arg @ref LL_ADC_CHANNEL_2
3799 * @arg @ref LL_ADC_CHANNEL_3
3800 * @arg @ref LL_ADC_CHANNEL_4
3801 * @arg @ref LL_ADC_CHANNEL_5
3802 * @arg @ref LL_ADC_CHANNEL_6
3803 * @arg @ref LL_ADC_CHANNEL_7
3804 * @arg @ref LL_ADC_CHANNEL_8
3805 * @arg @ref LL_ADC_CHANNEL_9
3806 * @arg @ref LL_ADC_CHANNEL_10
3807 * @arg @ref LL_ADC_CHANNEL_11
3808 * @arg @ref LL_ADC_CHANNEL_12
3809 * @arg @ref LL_ADC_CHANNEL_13
3810 * @arg @ref LL_ADC_CHANNEL_14
3811 * @arg @ref LL_ADC_CHANNEL_15
3812 * @arg @ref LL_ADC_CHANNEL_16
3813 * @arg @ref LL_ADC_CHANNEL_17
3814 * @arg @ref LL_ADC_CHANNEL_18
3815 * @arg @ref LL_ADC_CHANNEL_19
3816 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3817 * @arg @ref LL_ADC_CHANNEL_VREFINT
3818 * @arg @ref LL_ADC_CHANNEL_VBAT
3819 * @arg @ref LL_ADC_CHANNEL_DACCH1
3820 * @retval Returned value can be one of the following values:
3821 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3822 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3823 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)3824 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
3825 {
3826 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3827
3828 /* Retrieve sampling time bit corresponding to the selected channel */
3829 /* and shift it to position 0. */
3830 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3831 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3832 + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
3833 & 0x1FUL));
3834
3835 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3836 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3837 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3838 }
3839
3840 /**
3841 * @}
3842 */
3843
3844 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3845 * @{
3846 */
3847
3848 /**
3849 * @brief Set ADC analog watchdog monitored channels:
3850 * a single channel, multiple channels or all channels,
3851 * on ADC group regular.
3852 * @note Once monitored channels are selected, analog watchdog
3853 * is enabled.
3854 * @note In case of need to define a single channel to monitor
3855 * with analog watchdog from sequencer channel definition,
3856 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3857 * @note On this STM32 series, there are 2 kinds of analog watchdog
3858 * instance:
3859 * - AWD standard (instance AWD1):
3860 * - channels monitored: can monitor 1 channel or all channels.
3861 * - groups monitored: ADC group regular.
3862 * - resolution: resolution is not limited (corresponds to
3863 * ADC resolution configured).
3864 * - AWD flexible (instances AWD2, AWD3):
3865 * - channels monitored: flexible on channels monitored, selection is
3866 * channel wise, from from 1 to all channels.
3867 * Specificity of this analog watchdog: Multiple channels can
3868 * be selected. For example:
3869 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3870 * - groups monitored: not selection possible (monitoring on both
3871 * groups regular and injected).
3872 * Channels selected are monitored on groups regular and injected:
3873 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3874 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3875 * - resolution: resolution is not limited (corresponds to
3876 * ADC resolution configured).
3877 * @note On this STM32 series, setting of this feature is conditioned to
3878 * ADC state:
3879 * ADC must be disabled.
3880 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3881 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3882 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3883 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3884 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3885 * @param ADCx ADC instance
3886 * @param AWDy This parameter can be one of the following values:
3887 * @arg @ref LL_ADC_AWD1
3888 * @arg @ref LL_ADC_AWD2
3889 * @arg @ref LL_ADC_AWD3
3890 * @param AWDChannelGroup This parameter can be one of the following values:
3891 * @arg @ref LL_ADC_AWD_DISABLE
3892 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3893 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3894 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3895 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3896 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3897 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3898 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3899 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3900 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3901 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3902 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3903 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3904 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3905 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3906 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3907 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3908 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3909 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3910 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3911 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3912 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG
3913 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3914 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3915 * @arg @ref LL_ADC_AWD_CH_VBAT_REG
3916 * @arg @ref LL_ADC_AWD_CH_DACCH1_REG
3917 * @retval None
3918 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)3919 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
3920 {
3921 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
3922 /* in register and register position depending on parameter "AWDy". */
3923 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
3924 /* containing other bits reserved for other purpose. */
3925 __IO uint32_t *preg;
3926
3927 if (AWDy == LL_ADC_AWD1)
3928 {
3929 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
3930 }
3931 else
3932 {
3933 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
3934 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
3935 }
3936
3937 MODIFY_REG(*preg,
3938 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
3939 AWDChannelGroup & AWDy);
3940 }
3941
3942 /**
3943 * @brief Get ADC analog watchdog monitored channel.
3944 * @note Usage of the returned channel number:
3945 * - To reinject this channel into another function LL_ADC_xxx:
3946 * the returned channel number is only partly formatted on definition
3947 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3948 * with parts of literals LL_ADC_CHANNEL_x or using
3949 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3950 * Then the selected literal LL_ADC_CHANNEL_x can be used
3951 * as parameter for another function.
3952 * - To get the channel number in decimal format:
3953 * process the returned value with the helper macro
3954 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3955 * Applicable only when the analog watchdog is set to monitor
3956 * one channel.
3957 * @note On this STM32 series, there are 2 kinds of analog watchdog
3958 * instance:
3959 * - AWD standard (instance AWD1):
3960 * - channels monitored: can monitor 1 channel or all channels.
3961 * - groups monitored: ADC group regular.
3962 * - resolution: resolution is not limited (corresponds to
3963 * ADC resolution configured).
3964 * - AWD flexible (instances AWD2, AWD3):
3965 * - channels monitored: flexible on channels monitored, selection is
3966 * channel wise, from from 1 to all channels.
3967 * Specificity of this analog watchdog: Multiple channels can
3968 * be selected. For example:
3969 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3970 * - groups monitored: not selection possible (monitoring on both
3971 * groups regular and injected).
3972 * Channels selected are monitored on groups regular and injected:
3973 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3974 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3975 * - resolution: resolution is not limited (corresponds to
3976 * ADC resolution configured).
3977 * @note On this STM32 series, setting of this feature is conditioned to
3978 * ADC state:
3979 * ADC must be disabled or enabled without conversion on going
3980 * on group regular.
3981 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3982 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3983 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
3984 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
3985 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
3986 * @param ADCx ADC instance
3987 * @param AWDy This parameter can be one of the following values:
3988 * @arg @ref LL_ADC_AWD1
3989 * @arg @ref LL_ADC_AWD2 (1)
3990 * @arg @ref LL_ADC_AWD3 (1)
3991 *
3992 * (1) On this AWD number, monitored channel can be retrieved
3993 * if only 1 channel is programmed (or none or all channels).
3994 * This function cannot retrieve monitored channel if
3995 * multiple channels are programmed simultaneously
3996 * by bitfield.
3997 * @retval Returned value can be one of the following values:
3998 * @arg @ref LL_ADC_AWD_DISABLE
3999 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
4000 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
4001 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
4002 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
4003 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
4004 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
4005 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
4006 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
4007 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
4008 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
4009 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
4010 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
4011 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
4012 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
4013 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
4014 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
4015 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
4016 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
4017 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
4018 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
4019 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG
4020 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)4021 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
4022 {
4023 __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
4024 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
4025 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
4026 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
4027
4028 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
4029
4030 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
4031 /* (parameter value LL_ADC_AWD_DISABLE). */
4032 /* Else, the selected AWD is enabled and is monitoring a group of channels */
4033 /* or a single channel. */
4034 if (analog_wd_monit_channels != 0UL)
4035 {
4036 if (AWDy == LL_ADC_AWD1)
4037 {
4038 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
4039 {
4040 /* AWD monitoring a group of channels */
4041 analog_wd_monit_channels = ((analog_wd_monit_channels
4042 | (ADC_AWD_CR23_CHANNEL_MASK)
4043 )
4044 & (~(ADC_CFGR1_AWD1CH))
4045 );
4046 }
4047 else
4048 {
4049 /* AWD monitoring a single channel */
4050 analog_wd_monit_channels = (analog_wd_monit_channels
4051 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
4052 );
4053 }
4054 }
4055 else
4056 {
4057 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
4058 {
4059 /* AWD monitoring a group of channels */
4060 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
4061 | (ADC_CFGR1_AWD1EN)
4062 );
4063 }
4064 else
4065 {
4066 /* AWD monitoring a single channel */
4067 /* AWD monitoring a group of channels */
4068 analog_wd_monit_channels = (analog_wd_monit_channels
4069 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
4070 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos)
4071 );
4072 }
4073 }
4074 }
4075
4076 return analog_wd_monit_channels;
4077 }
4078
4079 /**
4080 * @brief Set ADC analog watchdog thresholds value of both thresholds
4081 * high and low.
4082 * @note If value of only one threshold high or low must be set,
4083 * use function @ref LL_ADC_SetAnalogWDThresholds().
4084 * @note In case of ADC resolution different of 12 bits,
4085 * analog watchdog thresholds data require a specific shift.
4086 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4087 * @note On this STM32 series, there are 2 kinds of analog watchdog
4088 * instance:
4089 * - AWD standard (instance AWD1):
4090 * - channels monitored: can monitor 1 channel or all channels.
4091 * - groups monitored: ADC group regular.
4092 * - resolution: resolution is not limited (corresponds to
4093 * ADC resolution configured).
4094 * - AWD flexible (instances AWD2, AWD3):
4095 * - channels monitored: flexible on channels monitored, selection is
4096 * channel wise, from from 1 to all channels.
4097 * Specificity of this analog watchdog: Multiple channels can
4098 * be selected. For example:
4099 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4100 * - groups monitored: not selection possible (monitoring on both
4101 * groups regular and injected).
4102 * Channels selected are monitored on groups regular and injected:
4103 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4104 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4105 * - resolution: resolution is not limited (corresponds to
4106 * ADC resolution configured).
4107 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
4108 * impacted: the comparison of analog watchdog thresholds is done on
4109 * oversampling final computation (after ratio and shift application):
4110 * ADC data register bitfield [15:4] (12 most significant bits).
4111 * Examples:
4112 * - Oversampling ratio and shift selected to have ADC conversion data
4113 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
4114 * ADC analog watchdog thresholds must be divided by 16.
4115 * - Oversampling ratio and shift selected to have ADC conversion data
4116 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
4117 * ADC analog watchdog thresholds must be divided by 4.
4118 * - Oversampling ratio and shift selected to have ADC conversion data
4119 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
4120 * ADC analog watchdog thresholds match directly to ADC data register.
4121 * @note On this STM32 series, setting of this feature is conditioned to
4122 * ADC state:
4123 * ADC must be disabled or enabled without conversion on going
4124 * on group regular.
4125 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
4126 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
4127 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
4128 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
4129 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
4130 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
4131 * @param ADCx ADC instance
4132 * @param AWDy This parameter can be one of the following values:
4133 * @arg @ref LL_ADC_AWD1
4134 * @arg @ref LL_ADC_AWD2
4135 * @arg @ref LL_ADC_AWD3
4136 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
4137 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
4138 * @retval None
4139 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)4140 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
4141 uint32_t AWDThresholdLowValue)
4142 {
4143 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
4144 /* position in register and register position depending on parameter */
4145 /* "AWDy". */
4146 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
4147 /* containing other bits reserved for other purpose. */
4148 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4149 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4150 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4151 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4152 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
4153 );
4154
4155 MODIFY_REG(*preg,
4156 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
4157 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
4158 }
4159
4160 /**
4161 * @brief Set ADC analog watchdog threshold value of threshold
4162 * high or low.
4163 * @note If values of both thresholds high or low must be set,
4164 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
4165 * @note In case of ADC resolution different of 12 bits,
4166 * analog watchdog thresholds data require a specific shift.
4167 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4168 * @note On this STM32 series, there are 2 kinds of analog watchdog
4169 * instance:
4170 * - AWD standard (instance AWD1):
4171 * - channels monitored: can monitor 1 channel or all channels.
4172 * - groups monitored: ADC group regular.
4173 * - resolution: resolution is not limited (corresponds to
4174 * ADC resolution configured).
4175 * - AWD flexible (instances AWD2, AWD3):
4176 * - channels monitored: flexible on channels monitored, selection is
4177 * channel wise, from from 1 to all channels.
4178 * Specificity of this analog watchdog: Multiple channels can
4179 * be selected. For example:
4180 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4181 * - groups monitored: not selection possible (monitoring on both
4182 * groups regular and injected).
4183 * Channels selected are monitored on groups regular and injected:
4184 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4185 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4186 * - resolution: resolution is not limited (corresponds to
4187 * ADC resolution configured).
4188 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
4189 * impacted: the comparison of analog watchdog thresholds is done on
4190 * oversampling final computation (after ratio and shift application):
4191 * ADC data register bitfield [15:4] (12 most significant bits).
4192 * Examples:
4193 * - Oversampling ratio and shift selected to have ADC conversion data
4194 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
4195 * ADC analog watchdog thresholds must be divided by 16.
4196 * - Oversampling ratio and shift selected to have ADC conversion data
4197 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
4198 * ADC analog watchdog thresholds must be divided by 4.
4199 * - Oversampling ratio and shift selected to have ADC conversion data
4200 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
4201 * ADC analog watchdog thresholds match directly to ADC data register.
4202 * @note On this STM32 series, setting of this feature is not conditioned to
4203 * ADC state:
4204 * ADC can be disabled, enabled with or without conversion on going
4205 * on ADC group regular.
4206 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
4207 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
4208 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
4209 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
4210 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
4211 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
4212 * @param ADCx ADC instance
4213 * @param AWDy This parameter can be one of the following values:
4214 * @arg @ref LL_ADC_AWD1
4215 * @arg @ref LL_ADC_AWD2
4216 * @arg @ref LL_ADC_AWD3
4217 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4218 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4219 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4220 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
4221 * @retval None
4222 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)4223 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
4224 uint32_t AWDThresholdValue)
4225 {
4226 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4227 /* position in register and register position depending on parameters */
4228 /* "AWDThresholdsHighLow" and "AWDy". */
4229 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4230 /* containing other bits reserved for other purpose. */
4231 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4232 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4233 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4234 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4235 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4236
4237 MODIFY_REG(*preg,
4238 AWDThresholdsHighLow,
4239 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
4240 }
4241
4242 /**
4243 * @brief Get ADC analog watchdog threshold value of threshold high,
4244 * threshold low or raw data with ADC thresholds high and low
4245 * concatenated.
4246 * @note If raw data with ADC thresholds high and low is retrieved,
4247 * the data of each threshold high or low can be isolated
4248 * using helper macro:
4249 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
4250 * @note In case of ADC resolution different of 12 bits,
4251 * analog watchdog thresholds data require a specific shift.
4252 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
4253 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
4254 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
4255 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
4256 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
4257 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
4258 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
4259 * @param ADCx ADC instance
4260 * @param AWDy This parameter can be one of the following values:
4261 * @arg @ref LL_ADC_AWD1
4262 * @arg @ref LL_ADC_AWD2
4263 * @arg @ref LL_ADC_AWD3
4264 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4265 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4266 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4267 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
4268 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4269 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)4270 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
4271 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
4272 {
4273 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4274 /* position in register and register position depending on parameters */
4275 /* "AWDThresholdsHighLow" and "AWDy". */
4276 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4277 /* containing other bits reserved for other purpose. */
4278 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4279 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4280 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4281 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4282 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4283
4284 return (uint32_t)(READ_BIT(*preg,
4285 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
4286 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
4287 & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
4288 }
4289
4290 /**
4291 * @}
4292 */
4293
4294 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
4295 * @{
4296 */
4297
4298 /**
4299 * @brief Set ADC oversampling scope.
4300 * @note On this STM32 series, setting of this feature is conditioned to
4301 * ADC state:
4302 * ADC must be disabled.
4303 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
4304 * @param ADCx ADC instance
4305 * @param OvsScope This parameter can be one of the following values:
4306 * @arg @ref LL_ADC_OVS_DISABLE
4307 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4308 * @retval None
4309 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)4310 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
4311 {
4312 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
4313 }
4314
4315 /**
4316 * @brief Get ADC oversampling scope.
4317 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
4318 * @param ADCx ADC instance
4319 * @retval Returned value can be one of the following values:
4320 * @arg @ref LL_ADC_OVS_DISABLE
4321 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4322 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)4323 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
4324 {
4325 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
4326 }
4327
4328 /**
4329 * @brief Set ADC oversampling discontinuous mode (triggered mode)
4330 * on the selected ADC group.
4331 * @note Number of oversampled conversions are done either in:
4332 * - continuous mode (all conversions of oversampling ratio
4333 * are done from 1 trigger)
4334 * - discontinuous mode (each conversion of oversampling ratio
4335 * needs a trigger)
4336 * @note On this STM32 series, setting of this feature is conditioned to
4337 * ADC state:
4338 * ADC must be disabled.
4339 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
4340 * @param ADCx ADC instance
4341 * @param OverSamplingDiscont This parameter can be one of the following values:
4342 * @arg @ref LL_ADC_OVS_REG_CONT
4343 * @arg @ref LL_ADC_OVS_REG_DISCONT
4344 * @retval None
4345 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)4346 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
4347 {
4348 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
4349 }
4350
4351 /**
4352 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4353 * on the selected ADC group.
4354 * @note Number of oversampled conversions are done either in:
4355 * - continuous mode (all conversions of oversampling ratio
4356 * are done from 1 trigger)
4357 * - discontinuous mode (each conversion of oversampling ratio
4358 * needs a trigger)
4359 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4360 * @param ADCx ADC instance
4361 * @retval Returned value can be one of the following values:
4362 * @arg @ref LL_ADC_OVS_REG_CONT
4363 * @arg @ref LL_ADC_OVS_REG_DISCONT
4364 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)4365 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
4366 {
4367 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4368 }
4369
4370 /**
4371 * @brief Set ADC oversampling
4372 * @note This function set the 2 items of oversampling configuration:
4373 * - ratio
4374 * - shift
4375 * @note On this STM32 series, setting of this feature is conditioned to
4376 * ADC state:
4377 * ADC must be disabled.
4378 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4379 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4380 * @param ADCx ADC instance
4381 * @param Ratio This parameter can be one of the following values:
4382 * @arg @ref LL_ADC_OVS_RATIO_2
4383 * @arg @ref LL_ADC_OVS_RATIO_4
4384 * @arg @ref LL_ADC_OVS_RATIO_8
4385 * @arg @ref LL_ADC_OVS_RATIO_16
4386 * @arg @ref LL_ADC_OVS_RATIO_32
4387 * @arg @ref LL_ADC_OVS_RATIO_64
4388 * @arg @ref LL_ADC_OVS_RATIO_128
4389 * @arg @ref LL_ADC_OVS_RATIO_256
4390 * @param Shift This parameter can be one of the following values:
4391 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4392 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4393 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4394 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4395 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4396 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4397 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4398 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4399 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4400 * @retval None
4401 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4402 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4403 {
4404 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4405 }
4406
4407 /**
4408 * @brief Get ADC oversampling ratio
4409 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4410 * @param ADCx ADC instance
4411 * @retval Ratio This parameter can be one of the following values:
4412 * @arg @ref LL_ADC_OVS_RATIO_2
4413 * @arg @ref LL_ADC_OVS_RATIO_4
4414 * @arg @ref LL_ADC_OVS_RATIO_8
4415 * @arg @ref LL_ADC_OVS_RATIO_16
4416 * @arg @ref LL_ADC_OVS_RATIO_32
4417 * @arg @ref LL_ADC_OVS_RATIO_64
4418 * @arg @ref LL_ADC_OVS_RATIO_128
4419 * @arg @ref LL_ADC_OVS_RATIO_256
4420 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)4421 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
4422 {
4423 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4424 }
4425
4426 /**
4427 * @brief Get ADC oversampling shift
4428 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4429 * @param ADCx ADC instance
4430 * @retval Shift This parameter can be one of the following values:
4431 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4432 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4433 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4434 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4435 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4436 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4437 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4438 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4439 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4440 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)4441 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
4442 {
4443 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4444 }
4445
4446 /**
4447 * @}
4448 */
4449
4450 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4451 * @{
4452 */
4453
4454 /**
4455 * @brief Enable ADC instance internal voltage regulator.
4456 * @note On this STM32 series, there are three possibilities to enable
4457 * the voltage regulator:
4458 * - by enabling it manually
4459 * using function @ref LL_ADC_EnableInternalRegulator().
4460 * - by launching a calibration
4461 * using function @ref LL_ADC_StartCalibration().
4462 * - by enabling the ADC
4463 * using function @ref LL_ADC_Enable().
4464 * @note On this STM32 series, after ADC internal voltage regulator enable,
4465 * a delay for ADC internal voltage regulator stabilization
4466 * is required before performing a ADC calibration or ADC enable.
4467 * Refer to device datasheet, parameter "tADCVREG_STUP".
4468 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4469 * @note On this STM32 series, setting of this feature is conditioned to
4470 * ADC state:
4471 * ADC must be ADC disabled.
4472 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4473 * @param ADCx ADC instance
4474 * @retval None
4475 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4476 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4477 {
4478 /* Note: Write register with some additional bits forced to state reset */
4479 /* instead of modifying only the selected bit for this function, */
4480 /* to not interfere with bits with HW property "rs". */
4481 MODIFY_REG(ADCx->CR,
4482 ADC_CR_BITS_PROPERTY_RS,
4483 ADC_CR_ADVREGEN);
4484 }
4485
4486 /**
4487 * @brief Disable ADC internal voltage regulator.
4488 * @note On this STM32 series, setting of this feature is conditioned to
4489 * ADC state:
4490 * ADC must be ADC disabled.
4491 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4492 * @param ADCx ADC instance
4493 * @retval None
4494 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4495 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4496 {
4497 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4498 }
4499
4500 /**
4501 * @brief Get the selected ADC instance internal voltage regulator state.
4502 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4503 * @param ADCx ADC instance
4504 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4505 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)4506 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
4507 {
4508 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4509 }
4510
4511 /**
4512 * @brief Enable the selected ADC instance.
4513 * @note On this STM32 series, after ADC enable, a delay for
4514 * ADC internal analog stabilization is required before performing a
4515 * ADC conversion start.
4516 * Refer to device datasheet, parameter tSTAB.
4517 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4518 * is enabled and when conversion clock is active.
4519 * (not only core clock: this ADC has a dual clock domain)
4520 * @note On this STM32 series, setting of this feature is conditioned to
4521 * ADC state:
4522 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4523 * @rmtoll CR ADEN LL_ADC_Enable
4524 * @param ADCx ADC instance
4525 * @retval None
4526 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4527 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4528 {
4529 /* Note: Write register with some additional bits forced to state reset */
4530 /* instead of modifying only the selected bit for this function, */
4531 /* to not interfere with bits with HW property "rs". */
4532 MODIFY_REG(ADCx->CR,
4533 ADC_CR_BITS_PROPERTY_RS,
4534 ADC_CR_ADEN);
4535 }
4536
4537 /**
4538 * @brief Disable the selected ADC instance.
4539 * @note On this STM32 series, setting of this feature is conditioned to
4540 * ADC state:
4541 * ADC must be not disabled. Must be enabled without conversion on going
4542 * on group regular.
4543 * @rmtoll CR ADDIS LL_ADC_Disable
4544 * @param ADCx ADC instance
4545 * @retval None
4546 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4547 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4548 {
4549 /* Note: Write register with some additional bits forced to state reset */
4550 /* instead of modifying only the selected bit for this function, */
4551 /* to not interfere with bits with HW property "rs". */
4552 MODIFY_REG(ADCx->CR,
4553 ADC_CR_BITS_PROPERTY_RS,
4554 ADC_CR_ADDIS);
4555 }
4556
4557 /**
4558 * @brief Get the selected ADC instance enable state.
4559 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4560 * is enabled and when conversion clock is active.
4561 * (not only core clock: this ADC has a dual clock domain)
4562 * @rmtoll CR ADEN LL_ADC_IsEnabled
4563 * @param ADCx ADC instance
4564 * @retval 0: ADC is disabled, 1: ADC is enabled.
4565 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)4566 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
4567 {
4568 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4569 }
4570
4571 /**
4572 * @brief Get the selected ADC instance disable state.
4573 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4574 * @param ADCx ADC instance
4575 * @retval 0: no ADC disable command on going.
4576 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)4577 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
4578 {
4579 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4580 }
4581
4582 /**
4583 * @brief Start ADC calibration in the mode single-ended
4584 * or differential (for devices with differential mode available).
4585 * @note On this STM32 series, a minimum number of ADC clock cycles
4586 * are required between ADC end of calibration and ADC enable.
4587 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4588 * @note In case of usage of ADC with DMA transfer:
4589 * On this STM32 series, ADC DMA transfer request should be disabled
4590 * during calibration:
4591 * Calibration factor is available in data register
4592 * and also transferred by DMA.
4593 * To not insert ADC calibration factor among ADC conversion data
4594 * in array variable, DMA transfer must be disabled during
4595 * calibration.
4596 * (DMA transfer setting backup and disable before calibration,
4597 * DMA transfer setting restore after calibration.
4598 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4599 * @ref LL_ADC_REG_SetDMATransfer() ).
4600 * @note In case of usage of feature auto power-off:
4601 * This mode must be disabled during calibration
4602 * Refer to function @ref LL_ADC_SetLowPowerMode().
4603 * @note On this STM32 series, setting of this feature is conditioned to
4604 * ADC state:
4605 * ADC must be ADC disabled.
4606 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4607 * @param ADCx ADC instance
4608 * @retval None
4609 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4610 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4611 {
4612 /* Note: Write register with some additional bits forced to state reset */
4613 /* instead of modifying only the selected bit for this function, */
4614 /* to not interfere with bits with HW property "rs". */
4615 MODIFY_REG(ADCx->CR,
4616 ADC_CR_BITS_PROPERTY_RS,
4617 ADC_CR_ADCAL);
4618 }
4619
4620 /**
4621 * @brief Get ADC calibration state.
4622 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4623 * @param ADCx ADC instance
4624 * @retval 0: calibration complete, 1: calibration in progress.
4625 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)4626 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
4627 {
4628 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4629 }
4630
4631 /**
4632 * @}
4633 */
4634
4635 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4636 * @{
4637 */
4638
4639 /**
4640 * @brief Start ADC group regular conversion.
4641 * @note On this STM32 series, this function is relevant for both
4642 * internal trigger (SW start) and external trigger:
4643 * - If ADC trigger has been set to software start, ADC conversion
4644 * starts immediately.
4645 * - If ADC trigger has been set to external trigger, ADC conversion
4646 * will start at next trigger event (on the selected trigger edge)
4647 * following the ADC start conversion command.
4648 * @note On this STM32 series, setting of this feature is conditioned to
4649 * ADC state:
4650 * ADC must be enabled without conversion on going on group regular,
4651 * without conversion stop command on going on group regular,
4652 * without ADC disable command on going.
4653 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4654 * @param ADCx ADC instance
4655 * @retval None
4656 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4657 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4658 {
4659 /* Note: Write register with some additional bits forced to state reset */
4660 /* instead of modifying only the selected bit for this function, */
4661 /* to not interfere with bits with HW property "rs". */
4662 MODIFY_REG(ADCx->CR,
4663 ADC_CR_BITS_PROPERTY_RS,
4664 ADC_CR_ADSTART);
4665 }
4666
4667 /**
4668 * @brief Stop ADC group regular conversion.
4669 * @note On this STM32 series, setting of this feature is conditioned to
4670 * ADC state:
4671 * ADC must be enabled (potentially with conversion on going on group regular),
4672 * without ADC disable command on going.
4673 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4674 * @param ADCx ADC instance
4675 * @retval None
4676 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4677 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4678 {
4679 /* Note: Write register with some additional bits forced to state reset */
4680 /* instead of modifying only the selected bit for this function, */
4681 /* to not interfere with bits with HW property "rs". */
4682 MODIFY_REG(ADCx->CR,
4683 ADC_CR_BITS_PROPERTY_RS,
4684 ADC_CR_ADSTP);
4685 }
4686
4687 /**
4688 * @brief Get ADC group regular conversion state.
4689 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4690 * @param ADCx ADC instance
4691 * @retval 0: no conversion is on going on ADC group regular.
4692 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)4693 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
4694 {
4695 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4696 }
4697
4698 /**
4699 * @brief Get ADC group regular command of conversion stop state
4700 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4701 * @param ADCx ADC instance
4702 * @retval 0: no command of conversion stop is on going on ADC group regular.
4703 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)4704 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
4705 {
4706 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4707 }
4708
4709 /**
4710 * @brief Get ADC group regular conversion data, range fit for
4711 * all ADC configurations: all ADC resolutions and
4712 * all oversampling increased data width (for devices
4713 * with feature oversampling).
4714 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4715 * @param ADCx ADC instance
4716 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4717 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)4718 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
4719 {
4720 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4721 }
4722
4723 /**
4724 * @brief Get ADC group regular conversion data, range fit for
4725 * ADC resolution 12 bits.
4726 * @note For devices with feature oversampling: Oversampling
4727 * can increase data width, function for extended range
4728 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4729 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4730 * @param ADCx ADC instance
4731 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4732 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)4733 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
4734 {
4735 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL);
4736 }
4737
4738 /**
4739 * @brief Get ADC group regular conversion data, range fit for
4740 * ADC resolution 10 bits.
4741 * @note For devices with feature oversampling: Oversampling
4742 * can increase data width, function for extended range
4743 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4744 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4745 * @param ADCx ADC instance
4746 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4747 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)4748 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
4749 {
4750 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL);
4751 }
4752
4753 /**
4754 * @brief Get ADC group regular conversion data, range fit for
4755 * ADC resolution 8 bits.
4756 * @note For devices with feature oversampling: Oversampling
4757 * can increase data width, function for extended range
4758 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4759 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4760 * @param ADCx ADC instance
4761 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4762 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)4763 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
4764 {
4765 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
4766 }
4767
4768 /**
4769 * @brief Get ADC group regular conversion data, range fit for
4770 * ADC resolution 6 bits.
4771 * @note For devices with feature oversampling: Oversampling
4772 * can increase data width, function for extended range
4773 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4774 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4775 * @param ADCx ADC instance
4776 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4777 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)4778 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
4779 {
4780 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL);
4781 }
4782
4783 /**
4784 * @}
4785 */
4786
4787 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4788 * @{
4789 */
4790
4791 /**
4792 * @brief Get flag ADC ready.
4793 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4794 * is enabled and when conversion clock is active.
4795 * (not only core clock: this ADC has a dual clock domain)
4796 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4797 * @param ADCx ADC instance
4798 * @retval State of bit (1 or 0).
4799 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)4800 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
4801 {
4802 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4803 }
4804
4805 /**
4806 * @brief Get flag ADC channel configuration ready.
4807 * @note On this STM32 series, after modifying sequencer
4808 * it is mandatory to wait for the assertion of CCRDY flag
4809 * using @ref LL_ADC_IsActiveFlag_CCRDY().
4810 * Otherwise, performing some actions (configuration update,
4811 * ADC conversion start, ... ) will be ignored.
4812 * Functions requiring wait for CCRDY flag are:
4813 * @ref LL_ADC_REG_SetSequencerLength()
4814 * @ref LL_ADC_REG_SetSequencerRanks()
4815 * @ref LL_ADC_REG_SetSequencerChannels()
4816 * @ref LL_ADC_REG_SetSequencerChAdd()
4817 * @ref LL_ADC_REG_SetSequencerChRem()
4818 * @ref LL_ADC_REG_SetSequencerScanDirection()
4819 * @ref LL_ADC_REG_SetSequencerConfigurable()
4820 * @note Duration of ADC channel configuration ready: CCRDY handshake
4821 * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
4822 * has been changed.
4823 * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
4824 * @param ADCx ADC instance
4825 * @retval State of bit (1 or 0).
4826 */
LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef * ADCx)4827 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx)
4828 {
4829 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
4830 }
4831
4832 /**
4833 * @brief Get flag ADC group regular end of unitary conversion.
4834 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4835 * @param ADCx ADC instance
4836 * @retval State of bit (1 or 0).
4837 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)4838 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
4839 {
4840 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4841 }
4842
4843 /**
4844 * @brief Get flag ADC group regular end of sequence conversions.
4845 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4846 * @param ADCx ADC instance
4847 * @retval State of bit (1 or 0).
4848 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)4849 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
4850 {
4851 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4852 }
4853
4854 /**
4855 * @brief Get flag ADC group regular overrun.
4856 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4857 * @param ADCx ADC instance
4858 * @retval State of bit (1 or 0).
4859 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)4860 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
4861 {
4862 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4863 }
4864
4865 /**
4866 * @brief Get flag ADC group regular end of sampling phase.
4867 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4868 * @param ADCx ADC instance
4869 * @retval State of bit (1 or 0).
4870 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)4871 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
4872 {
4873 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4874 }
4875
4876 /**
4877 * @brief Get flag ADC analog watchdog 1 flag
4878 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4879 * @param ADCx ADC instance
4880 * @retval State of bit (1 or 0).
4881 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)4882 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
4883 {
4884 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4885 }
4886
4887 /**
4888 * @brief Get flag ADC analog watchdog 2.
4889 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4890 * @param ADCx ADC instance
4891 * @retval State of bit (1 or 0).
4892 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)4893 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
4894 {
4895 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4896 }
4897
4898 /**
4899 * @brief Get flag ADC analog watchdog 3.
4900 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4901 * @param ADCx ADC instance
4902 * @retval State of bit (1 or 0).
4903 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)4904 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
4905 {
4906 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4907 }
4908
4909 /**
4910 * @brief Get flag ADC end of calibration.
4911 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
4912 * @param ADCx ADC instance
4913 * @retval State of bit (1 or 0).
4914 */
LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef * ADCx)4915 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
4916 {
4917 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
4918 }
4919
4920 /**
4921 * @brief Clear flag ADC ready.
4922 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4923 * is enabled and when conversion clock is active.
4924 * (not only core clock: this ADC has a dual clock domain)
4925 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
4926 * @param ADCx ADC instance
4927 * @retval None
4928 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)4929 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
4930 {
4931 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
4932 }
4933
4934 /**
4935 * @brief Clear flag ADC channel configuration ready.
4936 * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
4937 * @param ADCx ADC instance
4938 * @retval State of bit (1 or 0).
4939 */
LL_ADC_ClearFlag_CCRDY(ADC_TypeDef * ADCx)4940 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
4941 {
4942 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
4943 }
4944
4945 /**
4946 * @brief Clear flag ADC group regular end of unitary conversion.
4947 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
4948 * @param ADCx ADC instance
4949 * @retval None
4950 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)4951 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
4952 {
4953 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
4954 }
4955
4956 /**
4957 * @brief Clear flag ADC group regular end of sequence conversions.
4958 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
4959 * @param ADCx ADC instance
4960 * @retval None
4961 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)4962 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
4963 {
4964 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
4965 }
4966
4967 /**
4968 * @brief Clear flag ADC group regular overrun.
4969 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
4970 * @param ADCx ADC instance
4971 * @retval None
4972 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4973 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4974 {
4975 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
4976 }
4977
4978 /**
4979 * @brief Clear flag ADC group regular end of sampling phase.
4980 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
4981 * @param ADCx ADC instance
4982 * @retval None
4983 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)4984 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
4985 {
4986 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
4987 }
4988
4989 /**
4990 * @brief Clear flag ADC analog watchdog 1.
4991 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
4992 * @param ADCx ADC instance
4993 * @retval None
4994 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4995 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4996 {
4997 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
4998 }
4999
5000 /**
5001 * @brief Clear flag ADC analog watchdog 2.
5002 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
5003 * @param ADCx ADC instance
5004 * @retval None
5005 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)5006 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
5007 {
5008 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
5009 }
5010
5011 /**
5012 * @brief Clear flag ADC analog watchdog 3.
5013 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
5014 * @param ADCx ADC instance
5015 * @retval None
5016 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)5017 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
5018 {
5019 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
5020 }
5021
5022 /**
5023 * @brief Clear flag ADC end of calibration.
5024 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
5025 * @param ADCx ADC instance
5026 * @retval None
5027 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)5028 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
5029 {
5030 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
5031 }
5032
5033 /**
5034 * @}
5035 */
5036
5037 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
5038 * @{
5039 */
5040
5041 /**
5042 * @brief Enable ADC ready.
5043 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
5044 * @param ADCx ADC instance
5045 * @retval None
5046 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)5047 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
5048 {
5049 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
5050 }
5051
5052 /**
5053 * @brief Enable interruption ADC channel configuration ready.
5054 * @rmtoll IER CCRDYIE LL_ADC_EnableIT_CCRDY
5055 * @param ADCx ADC instance
5056 * @retval State of bit (1 or 0).
5057 */
LL_ADC_EnableIT_CCRDY(ADC_TypeDef * ADCx)5058 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
5059 {
5060 SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
5061 }
5062
5063 /**
5064 * @brief Enable interruption ADC group regular end of unitary conversion.
5065 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
5066 * @param ADCx ADC instance
5067 * @retval None
5068 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)5069 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
5070 {
5071 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
5072 }
5073
5074 /**
5075 * @brief Enable interruption ADC group regular end of sequence conversions.
5076 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
5077 * @param ADCx ADC instance
5078 * @retval None
5079 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)5080 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
5081 {
5082 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
5083 }
5084
5085 /**
5086 * @brief Enable ADC group regular interruption overrun.
5087 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
5088 * @param ADCx ADC instance
5089 * @retval None
5090 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)5091 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
5092 {
5093 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
5094 }
5095
5096 /**
5097 * @brief Enable interruption ADC group regular end of sampling.
5098 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
5099 * @param ADCx ADC instance
5100 * @retval None
5101 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)5102 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
5103 {
5104 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
5105 }
5106
5107 /**
5108 * @brief Enable interruption ADC analog watchdog 1.
5109 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
5110 * @param ADCx ADC instance
5111 * @retval None
5112 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)5113 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
5114 {
5115 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
5116 }
5117
5118 /**
5119 * @brief Enable interruption ADC analog watchdog 2.
5120 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
5121 * @param ADCx ADC instance
5122 * @retval None
5123 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)5124 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
5125 {
5126 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
5127 }
5128
5129 /**
5130 * @brief Enable interruption ADC analog watchdog 3.
5131 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
5132 * @param ADCx ADC instance
5133 * @retval None
5134 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)5135 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
5136 {
5137 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
5138 }
5139
5140 /**
5141 * @brief Enable interruption ADC end of calibration.
5142 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
5143 * @param ADCx ADC instance
5144 * @retval None
5145 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)5146 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
5147 {
5148 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5149 }
5150
5151 /**
5152 * @brief Disable interruption ADC ready.
5153 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
5154 * @param ADCx ADC instance
5155 * @retval None
5156 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)5157 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
5158 {
5159 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
5160 }
5161
5162 /**
5163 * @brief Disable interruption ADC channel configuration ready.
5164 * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY
5165 * @param ADCx ADC instance
5166 * @retval State of bit (1 or 0).
5167 */
LL_ADC_DisableIT_CCRDY(ADC_TypeDef * ADCx)5168 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
5169 {
5170 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
5171 }
5172
5173 /**
5174 * @brief Disable interruption ADC group regular end of unitary conversion.
5175 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
5176 * @param ADCx ADC instance
5177 * @retval None
5178 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)5179 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
5180 {
5181 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
5182 }
5183
5184 /**
5185 * @brief Disable interruption ADC group regular end of sequence conversions.
5186 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
5187 * @param ADCx ADC instance
5188 * @retval None
5189 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)5190 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
5191 {
5192 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
5193 }
5194
5195 /**
5196 * @brief Disable interruption ADC group regular overrun.
5197 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
5198 * @param ADCx ADC instance
5199 * @retval None
5200 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)5201 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
5202 {
5203 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
5204 }
5205
5206 /**
5207 * @brief Disable interruption ADC group regular end of sampling.
5208 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
5209 * @param ADCx ADC instance
5210 * @retval None
5211 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)5212 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
5213 {
5214 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
5215 }
5216
5217 /**
5218 * @brief Disable interruption ADC analog watchdog 1.
5219 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
5220 * @param ADCx ADC instance
5221 * @retval None
5222 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)5223 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
5224 {
5225 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
5226 }
5227
5228 /**
5229 * @brief Disable interruption ADC analog watchdog 2.
5230 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
5231 * @param ADCx ADC instance
5232 * @retval None
5233 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)5234 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
5235 {
5236 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
5237 }
5238
5239 /**
5240 * @brief Disable interruption ADC analog watchdog 3.
5241 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
5242 * @param ADCx ADC instance
5243 * @retval None
5244 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)5245 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
5246 {
5247 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
5248 }
5249
5250 /**
5251 * @brief Disable interruption ADC end of calibration.
5252 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
5253 * @param ADCx ADC instance
5254 * @retval None
5255 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)5256 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
5257 {
5258 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5259 }
5260
5261 /**
5262 * @brief Get state of interruption ADC ready
5263 * (0: interrupt disabled, 1: interrupt enabled).
5264 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
5265 * @param ADCx ADC instance
5266 * @retval State of bit (1 or 0).
5267 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)5268 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
5269 {
5270 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
5271 }
5272
5273 /**
5274 * @brief Get state of interruption ADC channel configuration ready.
5275 * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY
5276 * @param ADCx ADC instance
5277 * @retval State of bit (1 or 0).
5278 */
LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef * ADCx)5279 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx)
5280 {
5281 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
5282 }
5283
5284 /**
5285 * @brief Get state of interruption ADC group regular end of unitary conversion
5286 * (0: interrupt disabled, 1: interrupt enabled).
5287 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
5288 * @param ADCx ADC instance
5289 * @retval State of bit (1 or 0).
5290 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)5291 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
5292 {
5293 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
5294 }
5295
5296 /**
5297 * @brief Get state of interruption ADC group regular end of sequence conversions
5298 * (0: interrupt disabled, 1: interrupt enabled).
5299 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
5300 * @param ADCx ADC instance
5301 * @retval State of bit (1 or 0).
5302 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)5303 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
5304 {
5305 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
5306 }
5307
5308 /**
5309 * @brief Get state of interruption ADC group regular overrun
5310 * (0: interrupt disabled, 1: interrupt enabled).
5311 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
5312 * @param ADCx ADC instance
5313 * @retval State of bit (1 or 0).
5314 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)5315 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
5316 {
5317 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
5318 }
5319
5320 /**
5321 * @brief Get state of interruption ADC group regular end of sampling
5322 * (0: interrupt disabled, 1: interrupt enabled).
5323 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
5324 * @param ADCx ADC instance
5325 * @retval State of bit (1 or 0).
5326 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)5327 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
5328 {
5329 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
5330 }
5331
5332 /**
5333 * @brief Get state of interruption ADC analog watchdog 1
5334 * (0: interrupt disabled, 1: interrupt enabled).
5335 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
5336 * @param ADCx ADC instance
5337 * @retval State of bit (1 or 0).
5338 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)5339 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
5340 {
5341 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
5342 }
5343
5344 /**
5345 * @brief Get state of interruption Get ADC analog watchdog 2
5346 * (0: interrupt disabled, 1: interrupt enabled).
5347 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
5348 * @param ADCx ADC instance
5349 * @retval State of bit (1 or 0).
5350 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)5351 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
5352 {
5353 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
5354 }
5355
5356 /**
5357 * @brief Get state of interruption Get ADC analog watchdog 3
5358 * (0: interrupt disabled, 1: interrupt enabled).
5359 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
5360 * @param ADCx ADC instance
5361 * @retval State of bit (1 or 0).
5362 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)5363 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
5364 {
5365 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
5366 }
5367
5368 /**
5369 * @brief Get state of interruption ADC end of calibration
5370 * (0: interrupt disabled, 1: interrupt enabled).
5371 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5372 * @param ADCx ADC instance
5373 * @retval State of bit (1 or 0).
5374 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)5375 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
5376 {
5377 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5378 }
5379
5380 /**
5381 * @}
5382 */
5383
5384 #if defined(USE_FULL_LL_DRIVER)
5385 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5386 * @{
5387 */
5388
5389 /* Initialization of some features of ADC common parameters and multimode */
5390 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
5391 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5392 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5393
5394 /* De-initialization of ADC instance */
5395 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5396
5397 /* Initialization of some features of ADC instance */
5398 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
5399 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
5400
5401 /* Initialization of some features of ADC instance and ADC group regular */
5402 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5403 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5404
5405 /**
5406 * @}
5407 */
5408 #endif /* USE_FULL_LL_DRIVER */
5409
5410 /**
5411 * @}
5412 */
5413
5414 /**
5415 * @}
5416 */
5417
5418 #endif /* ADC1 */
5419
5420 /**
5421 * @}
5422 */
5423
5424 #ifdef __cplusplus
5425 }
5426 #endif
5427
5428 #endif /* STM32U0xx_LL_ADC_H */
5429
