1 /** 2 ****************************************************************************** 3 * @file stm32u0xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U0xx_HAL_TSC_H 21 #define STM32U0xx_HAL_TSC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u0xx_hal_def.h" 29 30 31 /** @addtogroup STM32U0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TSC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TSC_Exported_Types TSC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TSC state structure definition 46 */ 47 typedef enum 48 { 49 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 50 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 51 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 52 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 53 } HAL_TSC_StateTypeDef; 54 55 /** 56 * @brief TSC group status structure definition 57 */ 58 typedef enum 59 { 60 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 61 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 62 } TSC_GroupStatusTypeDef; 63 64 /** 65 * @brief TSC init structure definition 66 */ 67 typedef struct 68 { 69 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 70 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 71 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 72 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 73 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 74 This parameter can be set to ENABLE or DISABLE. */ 75 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 76 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 77 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 78 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 79 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 80 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 81 uint32_t MaxCountValue; /*!< Max count value 82 This parameter can be a value of @ref TSC_MaxCount_Value */ 83 uint32_t IODefaultMode; /*!< IO default mode 84 This parameter can be a value of @ref TSC_IO_Default_Mode */ 85 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 86 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 87 uint32_t AcquisitionMode; /*!< Acquisition mode 88 This parameter can be a value of @ref TSC_Acquisition_Mode */ 89 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 90 This parameter can be set to ENABLE or DISABLE. */ 91 uint32_t ChannelIOs; /*!< Channel IOs mask */ 92 uint32_t ShieldIOs; /*!< Shield IOs mask */ 93 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 94 } TSC_InitTypeDef; 95 96 /** 97 * @brief TSC IOs configuration structure definition 98 */ 99 typedef struct 100 { 101 uint32_t ChannelIOs; /*!< Channel IOs mask */ 102 uint32_t ShieldIOs; /*!< Shield IOs mask */ 103 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 104 } TSC_IOConfigTypeDef; 105 106 /** 107 * @brief TSC handle Structure definition 108 */ 109 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 110 typedef struct __TSC_HandleTypeDef 111 #else 112 typedef struct 113 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 114 { 115 TSC_TypeDef *Instance; /*!< Register base address */ 116 TSC_InitTypeDef Init; /*!< Initialization parameters */ 117 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 118 HAL_LockTypeDef Lock; /*!< Lock feature */ 119 __IO uint32_t ErrorCode; /*!< TSC Error code */ 120 121 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 122 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 123 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 124 125 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 126 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 127 128 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 129 } TSC_HandleTypeDef; 130 131 enum 132 { 133 TSC_GROUP1_IDX = 0x00UL, 134 TSC_GROUP2_IDX, 135 TSC_GROUP3_IDX, 136 TSC_GROUP4_IDX, 137 TSC_GROUP5_IDX, 138 TSC_GROUP6_IDX, 139 TSC_GROUP7_IDX, 140 TSC_NB_OF_GROUPS 141 }; 142 143 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 144 /** 145 * @brief HAL TSC Callback ID enumeration definition 146 */ 147 typedef enum 148 { 149 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 150 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 151 152 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 153 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 154 155 } HAL_TSC_CallbackIDTypeDef; 156 157 /** 158 * @brief HAL TSC Callback pointer definition 159 */ 160 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 161 162 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 163 164 /** 165 * @} 166 */ 167 168 /* Exported constants --------------------------------------------------------*/ 169 /** @defgroup TSC_Exported_Constants TSC Exported Constants 170 * @{ 171 */ 172 173 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 174 * @brief TSC Error Code definition 175 * @{ 176 */ 177 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 178 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 179 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 180 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 181 /** 182 * @} 183 */ 184 185 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 186 * @{ 187 */ 188 #define TSC_CTPH_1CYCLE 0x00000000UL 189 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 190 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 191 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 192 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 193 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 194 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 195 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 196 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 197 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 198 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 199 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 200 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 201 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 202 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 203 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 204 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 205 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 206 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 207 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 208 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 209 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 210 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 211 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 212 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 213 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 214 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 215 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 216 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 217 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 218 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 219 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 220 /** 221 * @} 222 */ 223 224 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 225 * @{ 226 */ 227 #define TSC_CTPL_1CYCLE 0x00000000UL 228 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 229 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 230 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 231 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 232 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 233 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 234 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 235 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 236 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 237 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 238 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 239 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 240 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 241 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 242 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 243 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 244 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 245 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 246 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 247 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 248 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 249 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 250 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 251 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 252 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 253 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 254 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 255 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 256 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 257 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 258 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 264 * @{ 265 */ 266 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 267 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 268 /** 269 * @} 270 */ 271 272 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 273 * @{ 274 */ 275 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 276 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 277 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 278 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 279 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 280 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 281 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 282 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup TSC_MaxCount_Value Max Count Value 288 * @{ 289 */ 290 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 291 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 292 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 293 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 294 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 295 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 296 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup TSC_IO_Default_Mode IO Default Mode 302 * @{ 303 */ 304 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 305 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 311 * @{ 312 */ 313 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 314 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 320 * @{ 321 */ 322 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 323 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 324 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 325 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 326 when the selected signal is detected on the SYNC input pin) */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup TSC_interrupts_definition Interrupts definition 332 * @{ 333 */ 334 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 335 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup TSC_flags_definition Flags definition 341 * @{ 342 */ 343 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 344 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup TSC_Group_definition Group definition 350 * @{ 351 */ 352 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 353 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 354 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 355 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 356 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 357 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 358 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 359 360 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 361 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 362 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 363 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 364 365 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 366 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 367 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 368 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 369 370 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 371 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 372 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 373 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 374 375 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 376 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 377 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 378 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 379 380 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 381 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 382 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 383 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 384 385 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 386 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 387 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 388 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 389 390 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 391 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 392 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 393 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 394 /** 395 * @} 396 */ 397 398 /** 399 * @} 400 */ 401 402 /* Exported macros -----------------------------------------------------------*/ 403 404 /** @defgroup TSC_Exported_Macros TSC Exported Macros 405 * @{ 406 */ 407 408 /** @brief Reset TSC handle state. 409 * @param __HANDLE__ TSC handle 410 * @retval None 411 */ 412 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 413 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 414 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 415 (__HANDLE__)->MspInitCallback = NULL; \ 416 (__HANDLE__)->MspDeInitCallback = NULL; \ 417 } while(0) 418 #else 419 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 420 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 421 422 /** 423 * @brief Enable the TSC peripheral. 424 * @param __HANDLE__ TSC handle 425 * @retval None 426 */ 427 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 428 429 /** 430 * @brief Disable the TSC peripheral. 431 * @param __HANDLE__ TSC handle 432 * @retval None 433 */ 434 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 435 436 /** 437 * @brief Start acquisition. 438 * @param __HANDLE__ TSC handle 439 * @retval None 440 */ 441 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 442 443 /** 444 * @brief Stop acquisition. 445 * @param __HANDLE__ TSC handle 446 * @retval None 447 */ 448 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 449 450 /** 451 * @brief Set IO default mode to output push-pull low. 452 * @param __HANDLE__ TSC handle 453 * @retval None 454 */ 455 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 456 457 /** 458 * @brief Set IO default mode to input floating. 459 * @param __HANDLE__ TSC handle 460 * @retval None 461 */ 462 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 463 464 /** 465 * @brief Set synchronization polarity to falling edge. 466 * @param __HANDLE__ TSC handle 467 * @retval None 468 */ 469 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 470 471 /** 472 * @brief Set synchronization polarity to rising edge and high level. 473 * @param __HANDLE__ TSC handle 474 * @retval None 475 */ 476 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 477 478 /** 479 * @brief Enable TSC interrupt. 480 * @param __HANDLE__ TSC handle 481 * @param __INTERRUPT__ TSC interrupt 482 * @retval None 483 */ 484 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 485 486 /** 487 * @brief Disable TSC interrupt. 488 * @param __HANDLE__ TSC handle 489 * @param __INTERRUPT__ TSC interrupt 490 * @retval None 491 */ 492 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 493 494 /** @brief Check whether the specified TSC interrupt source is enabled or not. 495 * @param __HANDLE__ TSC Handle 496 * @param __INTERRUPT__ TSC interrupt 497 * @retval SET or RESET 498 */ 499 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 500 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 501 RESET) 502 503 /** 504 * @brief Check whether the specified TSC flag is set or not. 505 * @param __HANDLE__ TSC handle 506 * @param __FLAG__ TSC flag 507 * @retval SET or RESET 508 */ 509 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 510 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 511 512 /** 513 * @brief Clear the TSC's pending flag. 514 * @param __HANDLE__ TSC handle 515 * @param __FLAG__ TSC flag 516 * @retval None 517 */ 518 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 519 520 /** 521 * @brief Enable schmitt trigger hysteresis on a group of IOs. 522 * @param __HANDLE__ TSC handle 523 * @param __GX_IOY_MASK__ IOs mask 524 * @retval None 525 */ 526 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 527 528 /** 529 * @brief Disable schmitt trigger hysteresis on a group of IOs. 530 * @param __HANDLE__ TSC handle 531 * @param __GX_IOY_MASK__ IOs mask 532 * @retval None 533 */ 534 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 535 &= (~(__GX_IOY_MASK__))) 536 537 /** 538 * @brief Open analog switch on a group of IOs. 539 * @param __HANDLE__ TSC handle 540 * @param __GX_IOY_MASK__ IOs mask 541 * @retval None 542 */ 543 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 544 &= (~(__GX_IOY_MASK__))) 545 546 /** 547 * @brief Close analog switch on a group of IOs. 548 * @param __HANDLE__ TSC handle 549 * @param __GX_IOY_MASK__ IOs mask 550 * @retval None 551 */ 552 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 553 554 /** 555 * @brief Enable a group of IOs in channel mode. 556 * @param __HANDLE__ TSC handle 557 * @param __GX_IOY_MASK__ IOs mask 558 * @retval None 559 */ 560 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 561 562 /** 563 * @brief Disable a group of channel IOs. 564 * @param __HANDLE__ TSC handle 565 * @param __GX_IOY_MASK__ IOs mask 566 * @retval None 567 */ 568 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 569 &= (~(__GX_IOY_MASK__))) 570 571 /** 572 * @brief Enable a group of IOs in sampling mode. 573 * @param __HANDLE__ TSC handle 574 * @param __GX_IOY_MASK__ IOs mask 575 * @retval None 576 */ 577 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 578 579 /** 580 * @brief Disable a group of sampling IOs. 581 * @param __HANDLE__ TSC handle 582 * @param __GX_IOY_MASK__ IOs mask 583 * @retval None 584 */ 585 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 586 587 /** 588 * @brief Enable acquisition groups. 589 * @param __HANDLE__ TSC handle 590 * @param __GX_MASK__ Groups mask 591 * @retval None 592 */ 593 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 594 595 /** 596 * @brief Disable acquisition groups. 597 * @param __HANDLE__ TSC handle 598 * @param __GX_MASK__ Groups mask 599 * @retval None 600 */ 601 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 602 603 /** @brief Gets acquisition group status. 604 * @param __HANDLE__ TSC Handle 605 * @param __GX_INDEX__ Group index 606 * @retval SET or RESET 607 */ 608 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 609 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 610 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 611 612 /** 613 * @} 614 */ 615 616 /* Private macros ------------------------------------------------------------*/ 617 618 /** @defgroup TSC_Private_Macros TSC Private Macros 619 * @{ 620 */ 621 622 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 623 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 624 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 625 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 626 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 627 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 628 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 629 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 630 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 631 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 632 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 633 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 634 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 635 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 636 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 637 ((__VALUE__) == TSC_CTPH_16CYCLES)) 638 639 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 640 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 641 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 642 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 643 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 644 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 645 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 646 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 647 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 648 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 649 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 650 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 651 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 652 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 653 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 654 ((__VALUE__) == TSC_CTPL_16CYCLES)) 655 656 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 657 || ((FunctionalState)(__VALUE__) == ENABLE)) 658 659 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 660 661 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 662 663 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 664 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 665 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 666 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 667 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 668 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 669 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 670 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 671 672 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 673 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 674 ((__CTPL__) > TSC_CTPL_2CYCLES))) || \ 675 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 676 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 677 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 678 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 679 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 680 681 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 682 ((__VALUE__) == TSC_MCV_511) || \ 683 ((__VALUE__) == TSC_MCV_1023) || \ 684 ((__VALUE__) == TSC_MCV_2047) || \ 685 ((__VALUE__) == TSC_MCV_4095) || \ 686 ((__VALUE__) == TSC_MCV_8191) || \ 687 ((__VALUE__) == TSC_MCV_16383)) 688 689 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 690 691 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 692 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 693 694 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 695 696 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 697 || ((FunctionalState)(__VALUE__) == ENABLE)) 698 699 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 700 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 701 702 #define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ 703 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 704 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 705 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 706 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 707 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 708 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 709 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 710 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 711 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 712 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 713 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 714 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 715 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 716 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 717 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 718 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 719 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 720 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 721 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 722 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 723 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 724 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 725 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 726 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 727 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 728 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 729 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 730 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4)) 731 /** 732 * @} 733 */ 734 735 /* Exported functions --------------------------------------------------------*/ 736 /** @addtogroup TSC_Exported_Functions 737 * @{ 738 */ 739 740 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 741 * @{ 742 */ 743 /* Initialization and de-initialization functions *****************************/ 744 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 745 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 746 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 747 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 748 749 /* Callbacks Register/UnRegister functions ***********************************/ 750 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 751 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 752 pTSC_CallbackTypeDef pCallback); 753 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 754 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 755 /** 756 * @} 757 */ 758 759 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 760 * @{ 761 */ 762 /* IO operation functions *****************************************************/ 763 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 764 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 765 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 766 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 767 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 768 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 769 uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 770 /** 771 * @} 772 */ 773 774 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 775 * @{ 776 */ 777 /* Peripheral Control functions ***********************************************/ 778 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); 779 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 780 /** 781 * @} 782 */ 783 784 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 785 * @{ 786 */ 787 /* Peripheral State and Error functions ***************************************/ 788 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 789 /** 790 * @} 791 */ 792 793 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 794 * @{ 795 */ 796 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 797 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 798 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 799 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 800 /** 801 * @} 802 */ 803 804 /** 805 * @} 806 */ 807 808 /** 809 * @} 810 */ 811 812 /** 813 * @} 814 */ 815 816 #ifdef __cplusplus 817 } 818 #endif 819 820 #endif /* STM32U0xx_HAL_TSC_H */ 821
