1 /** 2 ****************************************************************************** 3 * @file stm32u0xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U0xx_HAL_PWR_EX_H 21 #define STM32U0xx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u0xx_hal_def.h" 29 30 /** @addtogroup STM32U0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWREx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PWR PVM configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 50 This parameter can be a value of @ref PWREx_PVM_Type. 51 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring USB enable: VDDUSB versus 1.2 V 52 (applicable when USB feature is supported). 53 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring ADC enable: VDDA versus 1.62 V. 54 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring DAC enable: VDDA versus 2.2 V. */ 55 56 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 57 This parameter can be a value of @ref PWREx_PVM_Mode. */ 58 } PWR_PVMTypeDef; 59 /** 60 * @} 61 */ 62 63 /* Exported constants --------------------------------------------------------*/ 64 65 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 66 * @{ 67 */ 68 69 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 70 * @{ 71 */ 72 #define PWR_WUP_POLARITY_SHIFT 0x07U /*!< Internal constant used to retrieve wakeup pin polarity */ 73 /** 74 * @} 75 */ 76 77 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 78 * @{ 79 */ 80 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 81 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 82 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 83 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 84 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 85 #define PWR_WAKEUP_PIN7 PWR_CR3_EWUP7 /*!< Wakeup pin 7 (with high level polarity) */ 86 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 87 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 88 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 89 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 90 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 91 #define PWR_WAKEUP_PIN7_HIGH PWR_CR3_EWUP7 /*!< Wakeup pin 7 (with high level polarity) */ 92 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 93 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 94 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 95 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 96 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 97 #define PWR_WAKEUP_PIN7_LOW (uint32_t)((PWR_CR4_WP7<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP7) /*!< Wakeup pin 7 (with low level polarity) */ 98 /** 99 * @} 100 */ 101 102 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 103 * @{ 104 */ 105 #if defined(USB_DRD_FS) 106 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 107 #endif /* USB_DRD_FS */ 108 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 109 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ 110 /** 111 * @} 112 */ 113 114 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 115 * @{ 116 */ 117 #define PWR_PVM_MODE_NORMAL 0x00000000U /*!< basic mode is used */ 118 #define PWR_PVM_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ 119 #define PWR_PVM_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ 120 #define PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 121 #define PWR_PVM_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ 122 #define PWR_PVM_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ 123 #define PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ 124 /** 125 * @} 126 */ 127 128 /** @defgroup PWREx_Flash_PowerDown Flash Power Down modes 129 * @{ 130 */ 131 #define PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN /*!< Enable Flash power down in low power run mode */ 132 #define PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP /*!< Enable Flash power down in low power sleep mode */ 133 #define PWR_FLASHPD_STOP PWR_CR1_FPD_STOP /*!< Enable Flash power down in stop mode */ 134 /** 135 * @} 136 */ 137 138 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 139 * @{ 140 */ 141 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ 142 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 143 /** 144 * @} 145 */ 146 147 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 148 * @{ 149 */ 150 #define PWR_BATTERY_CHARGING_RESISTOR_5 0U /*!< VBAT charging through a 5 kOhms resistor */ 151 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 152 /** 153 * @} 154 */ 155 156 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 157 * @{ 158 */ 159 #define PWR_BATTERY_CHARGING_DISABLE 0U /*!< VBAT charging disable */ 160 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE /*!< VBAT charging enable */ 161 /** 162 * @} 163 */ 164 165 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 166 * @{ 167 */ 168 #define PWR_GPIO_BIT_0 PWR_PUCRA_PU0 /*!< GPIO port I/O pin 0 */ 169 #define PWR_GPIO_BIT_1 PWR_PUCRA_PU1 /*!< GPIO port I/O pin 1 */ 170 #define PWR_GPIO_BIT_2 PWR_PUCRA_PU2 /*!< GPIO port I/O pin 2 */ 171 #define PWR_GPIO_BIT_3 PWR_PUCRA_PU3 /*!< GPIO port I/O pin 3 */ 172 #define PWR_GPIO_BIT_4 PWR_PUCRA_PU4 /*!< GPIO port I/O pin 4 */ 173 #define PWR_GPIO_BIT_5 PWR_PUCRA_PU5 /*!< GPIO port I/O pin 5 */ 174 #define PWR_GPIO_BIT_6 PWR_PUCRA_PU6 /*!< GPIO port I/O pin 6 */ 175 #define PWR_GPIO_BIT_7 PWR_PUCRA_PU7 /*!< GPIO port I/O pin 7 */ 176 #define PWR_GPIO_BIT_8 PWR_PUCRA_PU8 /*!< GPIO port I/O pin 8 */ 177 #define PWR_GPIO_BIT_9 PWR_PUCRA_PU9 /*!< GPIO port I/O pin 9 */ 178 #define PWR_GPIO_BIT_10 PWR_PUCRA_PU10 /*!< GPIO port I/O pin 10 */ 179 #define PWR_GPIO_BIT_11 PWR_PUCRA_PU11 /*!< GPIO port I/O pin 11 */ 180 #define PWR_GPIO_BIT_12 PWR_PUCRA_PU12 /*!< GPIO port I/O pin 12 */ 181 #define PWR_GPIO_BIT_13 PWR_PUCRA_PU13 /*!< GPIO port I/O pin 13 */ 182 #define PWR_GPIO_BIT_14 PWR_PUCRA_PU14 /*!< GPIO port I/O pin 14 */ 183 #define PWR_GPIO_BIT_15 PWR_PUCRA_PU15 /*!< GPIO port I/O pin 15 */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup PWREx_GPIO GPIO port 189 * @{ 190 */ 191 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 192 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 193 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 194 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 195 #if defined (GPIOE) 196 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 197 #endif /* GPIOE */ 198 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 199 /** 200 * @} 201 */ 202 203 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 204 * @{ 205 */ 206 #if defined(USB_DRD_FS) 207 #define PWR_EXTI_LINE_PVM1 0x00100000U /*!< External interrupt line 19 Connected to the PVM USB EXTI Line */ 208 #endif /* USB_DRD_FS */ 209 #define PWR_EXTI_LINE_PVM3 0x00200000U /*!< External interrupt line 20 Connected to the PVM ADC EXTI Line */ 210 #define PWR_EXTI_LINE_PVM4 0x00400000U /*!< External interrupt line 21 Connected to the PVM DAC EXTI Line */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 216 * @{ 217 */ 218 #if defined(USB_DRD_FS) 219 #define PWR_EVENT_LINE_PVM1 0x00100000U /*!< Event line 19 Connected to the PVM USB EXTI Line */ 220 #endif /* USB_DRD_FS */ 221 #define PWR_EVENT_LINE_PVM3 0x00200000U /*!< Event line 20 Connected to the PVM ADC EXTI Line */ 222 #define PWR_EVENT_LINE_PVM4 0x00400000U /*!< Event line 21 Connected to the PVM DAC EXTI Line */ 223 /** 224 * @} 225 */ 226 227 /** @defgroup PWREx_Flag PWR Status Flags 228 * Elements values convention: 0000 0000 0XXY YYYYb 229 * - Y YYYY : Flag position in the XX register (5 bits) 230 * - XX : Status register (2 bits) 231 * - 01: SR1 register 232 * - 10: SR2 register 233 * The only exception is PWR_FLAG_WU, encompassing all 234 * wake-up flags and set to PWR_SR1_WUF. 235 * @{ 236 */ 237 #define PWR_FLAG_WUF1 0x0100U /*!< Wakeup event on wakeup pin 1 */ 238 #define PWR_FLAG_WUF2 0x0101U /*!< Wakeup event on wakeup pin 2 */ 239 #define PWR_FLAG_WUF3 0x0102U /*!< Wakeup event on wakeup pin 3 */ 240 #define PWR_FLAG_WUF4 0x0103U /*!< Wakeup event on wakeup pin 4 */ 241 #define PWR_FLAG_WUF5 0x0104U /*!< Wakeup event on wakeup pin 5 */ 242 #define PWR_FLAG_WUF7 0x0106U /*!< Wakeup event on wakeup pin 7 */ 243 #define PWR_FLAG_WU 0x5FUL /*!< Encompass wakeup event on all wakeup pins */ 244 #define PWR_FLAG_SB 0x0108U /*!< Standby flag */ 245 #define PWR_FLAG_STOP0 0x010BU /*!< Stop0 flag */ 246 #define PWR_FLAG_STOP1 0x0109U /*!< Stop1 flag */ 247 #define PWR_FLAG_STOP2 0x010AU /*!< Stop2 flag */ 248 #define PWR_FLAG_WUFI 0x010FU /*!< Wakeup on internal wakeup line */ 249 #define PWR_FLAG_FLASHRDY 0x0207U /*!< flash ready flag */ 250 #define PWR_FLAG_REGLPS 0x0208U /*!< Low-power regulator start flag */ 251 #define PWR_FLAG_REGLPF 0x0209U /*!< Low-power regulator flag */ 252 #define PWR_FLAG_VOSF 0x020AU /*!< Voltage scaling flag */ 253 #define PWR_FLAG_PVDO 0x020BU /*!< Power Voltage Detector output flag */ 254 #define PWR_FLAG_PVMO_USB 0x020CU /*!< Power Voltage Monitoring 1 output flag */ 255 #define PWR_FLAG_PVMO_ADC 0x020EU /*!< Power Voltage Monitoring 3 output flag */ 256 #define PWR_FLAG_PVMO_DAC 0x020FU /*!< Power Voltage Monitoring 4 output flag */ 257 #define PWR_SCR_CWUF 0x002FU /*!< Clear Wake-up Flags */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup PWREx_SRAM_Retention PWR SRAM Retention in Standby mode 263 * @{ 264 */ 265 #define PWR_NO_SRAM_RETENTION 0U /*!< SRAM is powered off in Standby mode (SRAM content is lost) */ 266 #define PWR_FULL_SRAM_RETENTION PWR_CR3_RRS /*!< Full SRAM is powered by the low-power regulator in Standby mode */ 267 268 /** 269 * @} 270 */ 271 272 /** 273 * @} 274 */ 275 276 /* Exported macros -----------------------------------------------------------*/ 277 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 278 * @{ 279 */ 280 #if defined(USB_DRD_FS) 281 /** 282 * @brief Enable the PVM USB Extended Interrupt Line. 283 * @retval None 284 */ 285 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVM1) 286 287 /** 288 * @brief Disable the PVM USB Extended Interrupt Line. 289 * @retval None 290 */ 291 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVM1) 292 293 /** 294 * @brief Enable the PVM USB Event Line. 295 * @retval None 296 */ 297 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVM1) 298 299 /** 300 * @brief Disable the PVM USB Event Line. 301 * @retval None 302 */ 303 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVM1) 304 305 /** 306 * @brief Enable the PVM1 USB Extended Interrupt Rising Trigger. 307 * @retval None 308 */ 309 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVM1) 310 311 /** 312 * @brief Disable the PVM USB Extended Interrupt Rising Trigger. 313 * @retval None 314 */ 315 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVM1) 316 317 /** 318 * @brief Enable the PVM USB Extended Interrupt Falling Trigger. 319 * @retval None 320 */ 321 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVM1) 322 323 /** 324 * @brief Disable the PVM USB Extended Interrupt Falling Trigger. 325 * @retval None 326 */ 327 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVM1) 328 329 /** 330 * @brief PVM USB EXTI line configuration: set rising & falling edge trigger. 331 * @retval None 332 */ 333 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 334 do { \ 335 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 336 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 337 } while(0) 338 339 /** 340 * @brief Disable the PVM USB Extended Interrupt Rising & Falling Trigger. 341 * @retval None 342 */ 343 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 344 do { \ 345 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 346 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 347 } while(0) 348 349 /** 350 * @brief Generate a Software interrupt on selected EXTI line. 351 * @retval None 352 */ 353 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVM1) 354 355 /** 356 * @brief Check whether the specified PVM USB EXTI Rising interrupt flag is set or not. 357 * @retval EXTI PVM_USB Line Status. 358 */ 359 360 #define __HAL_PWR_PVM1_EXTI_GET_RISING_FLAG() ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVM1)\ 361 == PWR_EXTI_LINE_PVM1) ? 1UL : 0UL) 362 363 /** 364 * @brief Check whether the specified PVM USB Falling EXTI interrupt flag is set or not. 365 * @retval EXTI PVM USB Line Status. 366 */ 367 #define __HAL_PWR_PVM1_EXTI_GET_FALLING_FLAG() ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVM1)\ 368 == PWR_EXTI_LINE_PVM1) ? 1UL : 0UL) 369 370 /** 371 * @brief Clear the PVM USB EXTI flag. 372 * @retval None 373 */ 374 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() \ 375 do \ 376 { \ 377 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVM1); \ 378 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVM1); \ 379 } while(0) 380 #endif /* USB_DRD_FS */ 381 382 /** 383 * @brief Enable the PVM ADC Extended Interrupt Line. 384 * @retval None 385 */ 386 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVM3) 387 388 /** 389 * @brief Disable the PVM ADC Extended Interrupt Line. 390 * @retval None 391 */ 392 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVM3) 393 394 /** 395 * @brief Enable the PVM ADC Event Line. 396 * @retval None 397 */ 398 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVM3) 399 400 /** 401 * @brief Disable the PVM ADC Event Line. 402 * @retval None 403 */ 404 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVM3) 405 406 /** 407 * @brief Enable the PVM ADC Extended Interrupt Rising Trigger. 408 * @retval None 409 */ 410 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVM3) 411 412 /** 413 * @brief Disable the PVM ADC Extended Interrupt Rising Trigger. 414 * @retval None 415 */ 416 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVM3) 417 418 /** 419 * @brief Enable the PVM ADC Extended Interrupt Falling Trigger. 420 * @retval None 421 */ 422 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVM3) 423 424 /** 425 * @brief Disable the PVM ADC Extended Interrupt Falling Trigger. 426 * @retval None 427 */ 428 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVM3) 429 430 /** 431 * @brief PVM ADC EXTI line configuration: set rising & falling edge trigger. 432 * @retval None 433 */ 434 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 435 do { \ 436 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 437 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 438 } while(0) 439 440 /** 441 * @brief Disable the PVM ADC Extended Interrupt Rising & Falling Trigger. 442 * @retval None 443 */ 444 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 445 do { \ 446 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 447 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 448 } while(0) 449 450 /** 451 * @brief Generate a Software interrupt on selected EXTI line. 452 * @retval None 453 */ 454 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVM3) 455 456 /** 457 * @brief Check whether the specified PVM ADC EXTI Rising interrupt flag is set or not. 458 * @retval EXTI PVM ADC Line Status. 459 */ 460 461 #define __HAL_PWR_PVM3_EXTI_GET_RISING_FLAG() ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVM3)\ 462 == PWR_EXTI_LINE_PVM3) ? 1UL : 0UL) 463 464 /** 465 * @brief Check whether the specified PVM ADC EXTI Falling interrupt flag is set or not. 466 * @retval EXTI PVM ADC Line Status. 467 */ 468 469 #define __HAL_PWR_PVM3_EXTI_GET_FALLING_FLAG() ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVM3)\ 470 == PWR_EXTI_LINE_PVM3) ? 1UL : 0UL) 471 472 /** 473 * @brief Clear the PVM_ADC EXTI flag. 474 * @retval None 475 */ 476 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() \ 477 do \ 478 { \ 479 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVM3); \ 480 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVM3); \ 481 } while(0) 482 483 /** 484 * @brief Enable the PVM DAC Extended Interrupt Line. 485 * @retval None 486 */ 487 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVM4) 488 489 /** 490 * @brief Disable the PVM DAC Extended Interrupt Line. 491 * @retval None 492 */ 493 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVM4) 494 495 /** 496 * @brief Enable the PVM DAC Event Line. 497 * @retval None 498 */ 499 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVM4) 500 501 /** 502 * @brief Disable the PVM DAC Event Line. 503 * @retval None 504 */ 505 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVM4) 506 507 /** 508 * @brief Enable the PVM DAC Extended Interrupt Rising Trigger. 509 * @retval None 510 */ 511 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVM4) 512 513 /** 514 * @brief Disable the PVM DAC Extended Interrupt Rising Trigger. 515 * @retval None 516 */ 517 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVM4) 518 519 /** 520 * @brief Enable the PVM DAC Extended Interrupt Falling Trigger. 521 * @retval None 522 */ 523 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVM4) 524 525 /** 526 * @brief Disable the PVM DAC Extended Interrupt Falling Trigger. 527 * @retval None 528 */ 529 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVM4) 530 531 /** 532 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 533 * @retval None 534 */ 535 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 536 do { \ 537 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 538 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 539 } while(0) 540 541 /** 542 * @brief Disable the PVM_DAC Extended Interrupt Rising & Falling Trigger. 543 * @retval None 544 */ 545 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 546 do { \ 547 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 548 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 549 } while(0) 550 551 /** 552 * @brief Generate a Software interrupt on selected EXTI line. 553 * @retval None 554 */ 555 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVM4) 556 557 /** 558 * @brief Check whether the specified PVM DAC EXTI Rising interrupt flag is set or not. 559 * @retval EXTI PVM DAC Line Status. 560 */ 561 562 #define __HAL_PWR_PVM4_EXTI_GET_RISING_FLAG() ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVM4)\ 563 == PWR_EXTI_LINE_PVM4) ? 1UL : 0UL) 564 565 /** 566 * @brief Check whether the specified PVM DAC EXTI Falling interrupt flag is set or not. 567 * @retval EXTI PVM DAC Line Status. 568 */ 569 570 #define __HAL_PWR_PVM4_EXTI_GET_FALLING_FLAG() ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVM4)\ 571 == PWR_EXTI_LINE_PVM4) ? 1UL : 0UL) 572 573 /** 574 * @brief Clear the PVM DAC EXTI flag. 575 * @retval None. 576 */ 577 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() \ 578 do \ 579 { \ 580 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVM4); \ 581 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVM4); \ 582 } while(0) 583 584 /** 585 * @brief Configure the main internal regulator output voltage. 586 * @param __REGULATOR__ specifies the regulator output voltage to achieve 587 * a tradeoff between performance and power consumption. 588 * This parameter can be one of the following values: 589 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 590 * typical output voltage at 1.2 V, 591 * system frequency up to 80 MHz. 592 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 593 * typical output voltage at 1.0 V, 594 * system frequency up to 26 MHz. 595 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 596 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 597 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 598 * @retval None 599 */ 600 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 601 __IO uint32_t tmpreg; \ 602 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 603 /* Delay after an RCC peripheral clock enabling */ \ 604 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 605 UNUSED(tmpreg); \ 606 } while(0) 607 608 /** 609 * @} 610 */ 611 612 /* Private macros --------------------------------------------------------*/ 613 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 614 * @{ 615 */ 616 617 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 618 ((PIN) == PWR_WAKEUP_PIN2) || \ 619 ((PIN) == PWR_WAKEUP_PIN3) || \ 620 ((PIN) == PWR_WAKEUP_PIN4) || \ 621 ((PIN) == PWR_WAKEUP_PIN5) || \ 622 ((PIN) == PWR_WAKEUP_PIN7) || \ 623 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 624 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 625 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 626 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 627 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 628 ((PIN) == PWR_WAKEUP_PIN7_HIGH) || \ 629 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 630 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 631 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 632 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 633 ((PIN) == PWR_WAKEUP_PIN5_LOW) || \ 634 ((PIN) == PWR_WAKEUP_PIN7_LOW)) 635 #if defined(USB_DRD_FS) 636 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 637 ((TYPE) == PWR_PVM_3) ||\ 638 ((TYPE) == PWR_PVM_4)) 639 #else 640 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ 641 ((TYPE) == PWR_PVM_4)) 642 #endif /* USB_DRD_FS */ 643 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 644 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 645 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 646 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 647 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 648 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 649 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 650 651 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 652 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 653 654 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 655 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 656 657 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 658 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 659 660 #if defined (GPIOE) 661 #define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ 662 ((GPIO_PORT) == PWR_GPIO_B) ||\ 663 ((GPIO_PORT) == PWR_GPIO_C) ||\ 664 ((GPIO_PORT) == PWR_GPIO_D) ||\ 665 ((GPIO_PORT) == PWR_GPIO_E) ||\ 666 ((GPIO_PORT) == PWR_GPIO_F)) 667 #else 668 #define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ 669 ((GPIO_PORT) == PWR_GPIO_B) ||\ 670 ((GPIO_PORT) == PWR_GPIO_C) ||\ 671 ((GPIO_PORT) == PWR_GPIO_D) ||\ 672 ((GPIO_PORT) == PWR_GPIO_F)) 673 #endif /* GPIOE */ 674 675 #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK)) 676 677 #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | \ 678 PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0U) && \ 679 (((__MODE__) & ~(PWR_FLASHPD_LPRUN | \ 680 PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0U)) 681 /** 682 * @} 683 */ 684 685 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 686 * @{ 687 */ 688 689 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 690 * @{ 691 */ 692 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 693 uint32_t HAL_PWREx_GetVoltageRange(void); 694 /** 695 * @} 696 */ 697 698 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 699 * @{ 700 */ 701 void HAL_PWREx_EnableLowPowerRunMode(void); 702 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 703 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 704 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 705 /** 706 * @} 707 */ 708 709 /** @addtogroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions 710 * @{ 711 */ 712 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 713 void HAL_PWREx_DisableBatteryCharging(void); 714 #if defined(USB_DRD_FS) 715 void HAL_PWREx_EnablePVM1(void); 716 void HAL_PWREx_DisablePVM1(void); 717 #endif /* USB_DRD_FS */ 718 void HAL_PWREx_EnablePVM3(void); 719 void HAL_PWREx_DisablePVM3(void); 720 void HAL_PWREx_EnablePVM4(void); 721 void HAL_PWREx_DisablePVM4(void); 722 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM); 723 #if defined(USB_DRD_FS) 724 void HAL_PWREx_EnableVddUSB(void); 725 void HAL_PWREx_DisableVddUSB(void); 726 #endif /* USB_DRD_FS */ 727 void HAL_PWREx_PVD_PVM_IRQHandler(void); 728 #if defined(USB_DRD_FS) 729 void HAL_PWREx_PVM1_Callback(void); 730 #endif /* USB_DRD_FS */ 731 void HAL_PWREx_PVM3_Callback(void); 732 void HAL_PWREx_PVM4_Callback(void); 733 void HAL_PWREx_EnableInternalWakeUpLine(void); 734 void HAL_PWREx_DisableInternalWakeUpLine(void); 735 /** 736 * @} 737 */ 738 739 /** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions 740 * @{ 741 */ 742 void HAL_PWREx_EnableSRAMContentRetention(void); 743 void HAL_PWREx_DisableSRAMContentRetention(void); 744 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); 745 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); 746 void HAL_PWREx_EnableUltraLowPowerMode(void); 747 void HAL_PWREx_DisableUltraLowPowerMode(void); 748 /** 749 * @} 750 */ 751 752 /** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions 753 * @{ 754 */ 755 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); 756 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); 757 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); 758 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); 759 void HAL_PWREx_EnablePullUpPullDownConfig(void); 760 void HAL_PWREx_DisablePullUpPullDownConfig(void); 761 /** 762 * @} 763 */ 764 765 /** 766 * @} 767 */ 768 769 /** 770 * @} 771 */ 772 773 /** 774 * @} 775 */ 776 777 #ifdef __cplusplus 778 } 779 #endif 780 781 #endif /* STM32U0xx_HAL_PWR_EX_H */ 782
