1 /** 2 ****************************************************************************** 3 * @file stm32u0xx_hal_dma.h 4 * @author GPM Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U0xx_HAL_DMA_H 21 #define STM32U0xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u0xx_hal_def.h" 29 #include "stm32u0xx_ll_dma.h" 30 31 /** @addtogroup STM32U0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 } HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 } HAL_DMA_LevelCompleteTypeDef; 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 107 108 } HAL_DMA_CallbackIDTypeDef; 109 110 /** 111 * @brief DMA handle Structure definition 112 */ 113 typedef struct __DMA_HandleTypeDef 114 { 115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 116 117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 118 119 HAL_LockTypeDef Lock; /*!< DMA locking object */ 120 121 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 122 123 void *Parent; /*!< Parent object state */ 124 125 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 126 127 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 128 129 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 130 131 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 132 133 __IO uint32_t ErrorCode; /*!< DMA Error code */ 134 135 #if defined(DMA2) 136 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 137 138 #endif /* DMA2 */ 139 uint32_t ChannelIndex; /*!< DMA Channel Index */ 140 141 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 142 143 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 144 145 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 146 147 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 148 149 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 150 151 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 152 } DMA_HandleTypeDef; 153 /** 154 * @} 155 */ 156 157 /* Exported constants --------------------------------------------------------*/ 158 159 /** @defgroup DMA_Exported_Constants DMA Exported Constants 160 * @{ 161 */ 162 163 /** @defgroup DMA_Error_Code DMA Error Code 164 * @{ 165 */ 166 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 167 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 168 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 169 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 170 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 171 #define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ 172 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 173 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 174 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup DMA_request DMA request 181 * @{ 182 */ 183 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 184 #define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ 185 #define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ 186 #define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ 187 #define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ 188 #define DMA_REQUEST_ADC LL_DMAMUX_REQ_ADC /*!< DMAMUX ADC1 request */ 189 #if defined(AES) 190 #define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ 191 #define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ 192 #endif /* AES */ 193 #define DMA_REQUEST_DAC_CH1 LL_DMAMUX_REQ_DAC_CH1 /*!< DMAMUX DAC_CH1 request */ 194 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 195 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 196 #define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ 197 #define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ 198 #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ 199 #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ 200 #if defined(I2C4) 201 #define DMA_REQUEST_I2C4_RX LL_DMAMUX_REQ_I2C4_RX /*!< DMAMUX I2C4 RX request */ 202 #define DMA_REQUEST_I2C4_TX LL_DMAMUX_REQ_I2C4_TX /*!< DMAMUX I2C4 TX request */ 203 #endif /* I2C4 */ 204 #define DMA_REQUEST_LPTIM1_IC1 LL_DMAMUX_REQ_LPTIM1_IC1 /*!< DMAMUX LPTIM1 IC1 request */ 205 #define DMA_REQUEST_LPTIM1_IC2 LL_DMAMUX_REQ_LPTIM1_IC2 /*!< DMAMUX LPTIM1 IC2 request */ 206 #define DMA_REQUEST_LPTIM1_IC3 LL_DMAMUX_REQ_LPTIM1_IC3 /*!< DMAMUX LPTIM1 IC3 request */ 207 #define DMA_REQUEST_LPTIM1_IC4 LL_DMAMUX_REQ_LPTIM1_IC4 /*!< DMAMUX LPTIM1 IC4 request */ 208 #define DMA_REQUEST_LPTIM1_UE LL_DMAMUX_REQ_LPTIM1_UE /*!< DMAMUX LPTIM1 UE request */ 209 #define DMA_REQUEST_LPTIM2_IC1 LL_DMAMUX_REQ_LPTIM2_IC1 /*!< DMAMUX LPTIM2 IC1 request */ 210 #define DMA_REQUEST_LPTIM2_IC2 LL_DMAMUX_REQ_LPTIM2_IC2 /*!< DMAMUX LPTIM2 IC2 request */ 211 #define DMA_REQUEST_LPTIM2_UE LL_DMAMUX_REQ_LPTIM2_UE /*!< DMAMUX LPTIM2 UE request */ 212 #if defined(LPTIM3) 213 #define DMA_REQUEST_LPTIM3_IC1 LL_DMAMUX_REQ_LPTIM3_IC1 /*!< DMAMUX LPTIM3 IC1 request */ 214 #define DMA_REQUEST_LPTIM3_IC2 LL_DMAMUX_REQ_LPTIM3_IC2 /*!< DMAMUX LPTIM3 IC2 request */ 215 #define DMA_REQUEST_LPTIM3_IC3 LL_DMAMUX_REQ_LPTIM3_IC3 /*!< DMAMUX LPTIM3 IC3 request */ 216 #define DMA_REQUEST_LPTIM3_IC4 LL_DMAMUX_REQ_LPTIM3_IC4 /*!< DMAMUX LPTIM3 IC4 request */ 217 #define DMA_REQUEST_LPTIM3_UE LL_DMAMUX_REQ_LPTIM3_UE /*!< DMAMUX LPTIM3 UE request */ 218 #endif /* LPTIM3 */ 219 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ 220 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ 221 #define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */ 222 #define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */ 223 #if defined(LPUART3) 224 #define DMA_REQUEST_LPUART3_RX LL_DMAMUX_REQ_LPUART3_RX /*!< DMAMUX LPUART3 RX request */ 225 #define DMA_REQUEST_LPUART3_TX LL_DMAMUX_REQ_LPUART3_TX /*!< DMAMUX LPUART3 TX request */ 226 #endif /* LPUART3 */ 227 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 228 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 229 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 230 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 231 #if defined(SPI3) 232 #define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ 233 #define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ 234 #endif /* SPI3 */ 235 #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ 236 #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ 237 #define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ 238 #define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ 239 #define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM /*!< DMAMUX TIM1 TRIG COM request */ 240 #define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ 241 #define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 242 #define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ 243 #define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 244 #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 245 #define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */ 246 #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 247 #define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */ 248 #define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */ 249 #define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */ 250 #define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4 /*!< DMAMUX TIM3 CH4 request */ 251 #define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG /*!< DMAMUX TIM3 TRIG request */ 252 #define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */ 253 #define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */ 254 #define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */ 255 #define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */ 256 #define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */ 257 #define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */ 258 #define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */ 259 #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 260 #define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */ 261 #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 262 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 263 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 264 #define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ 265 #define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ 266 #define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */ 267 #define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */ 268 #define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */ 269 #define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */ 270 271 #define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ 272 /** 273 * @} 274 */ 275 276 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 277 * @{ 278 */ 279 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 280 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 281 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 282 283 /** 284 * @} 285 */ 286 287 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 288 * @{ 289 */ 290 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 291 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 292 /** 293 * @} 294 */ 295 296 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 297 * @{ 298 */ 299 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 300 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 301 /** 302 * @} 303 */ 304 305 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 306 * @{ 307 */ 308 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 309 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 310 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 311 /** 312 * @} 313 */ 314 315 /** @defgroup DMA_Memory_data_size DMA Memory data size 316 * @{ 317 */ 318 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 319 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 320 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 321 /** 322 * @} 323 */ 324 325 /** @defgroup DMA_mode DMA mode 326 * @{ 327 */ 328 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 329 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup DMA_Priority_level DMA Priority level 335 * @{ 336 */ 337 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 338 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 339 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 340 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 346 * @{ 347 */ 348 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ 349 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ 350 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup DMA_flag_definitions DMA flag definitions 356 * @{ 357 */ 358 359 #define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ 360 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ 361 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ 362 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ 363 #define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ 364 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ 365 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ 366 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ 367 #define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ 368 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ 369 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ 370 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ 371 #define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ 372 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ 373 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ 374 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ 375 #define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ 376 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ 377 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ 378 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ 379 #define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ 380 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ 381 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ 382 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ 383 #define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ 384 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ 385 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ 386 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ 387 /** 388 * @} 389 */ 390 391 /** 392 * @} 393 */ 394 395 /* Exported macros -----------------------------------------------------------*/ 396 /** @defgroup DMA_Exported_Macros DMA Exported Macros 397 * @{ 398 */ 399 400 /** @brief Reset DMA handle state 401 * @param __HANDLE__ DMA handle 402 * @retval None 403 */ 404 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 405 406 /** 407 * @brief Enable the specified DMA Channel. 408 * @param __HANDLE__ DMA handle 409 * @retval None 410 */ 411 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 412 413 /** 414 * @brief Disable the specified DMA Channel. 415 * @param __HANDLE__ DMA handle 416 * @retval None 417 */ 418 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 419 420 /** 421 * @brief Return the current DMA Channel transfer complete flag. 422 * @param __HANDLE__ DMA handle 423 * @retval The specified transfer complete flag index. 424 */ 425 #if defined(DMA2) 426 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 427 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 438 DMA_FLAG_TC7) 439 #else /* DMA1 */ 440 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 441 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 447 DMA_FLAG_TC7) 448 #endif /* DMA2 */ 449 450 /** 451 * @brief Return the current DMA Channel half transfer complete flag. 452 * @param __HANDLE__ DMA handle 453 * @retval The specified half transfer complete flag index. 454 */ 455 #if defined(DMA2) 456 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 457 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 468 DMA_FLAG_HT7) 469 #else /* DMA1 */ 470 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 477 DMA_FLAG_HT7) 478 #endif /* DMA2 */ 479 480 /** 481 * @brief Return the current DMA Channel transfer error flag. 482 * @param __HANDLE__ DMA handle 483 * @retval The specified transfer error flag index. 484 */ 485 #if defined(DMA2) 486 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 487 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 498 DMA_FLAG_TE7) 499 #else /* DMA1 */ 500 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 501 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 507 DMA_FLAG_TE7) 508 #endif /* DMA2 */ 509 510 /** 511 * @brief Return the current DMA Channel Global interrupt flag. 512 * @param __HANDLE__ DMA handle 513 * @retval The specified transfer error flag index. 514 */ 515 #if defined(DMA2) 516 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 517 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 528 DMA_FLAG_GI7) 529 #else /* DMA1 */ 530 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 531 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 537 DMA_FLAG_GI7) 538 #endif /* DMA2 */ 539 540 /** 541 * @brief Get the DMA Channel pending flags. 542 * @param __HANDLE__ DMA handle 543 * @param __FLAG__ Get the specified flag. 544 * This parameter can be any combination of the following values: 545 * @arg DMA_FLAG_TCx: Transfer complete flag 546 * @arg DMA_FLAG_HTx: Half transfer complete flag 547 * @arg DMA_FLAG_TEx: Transfer error flag 548 * @arg DMA_FLAG_GIx: Global interrupt flag 549 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 550 * @retval The state of FLAG (SET or RESET). 551 */ 552 #if defined(DMA2) 553 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 554 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 555 #else /* DMA1 */ 556 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 557 #endif /* DMA2 */ 558 559 /** 560 * @brief Clear the DMA Channel pending flags. 561 * @param __HANDLE__ DMA handle 562 * @param __FLAG__ specifies the flag to clear. 563 * This parameter can be any combination of the following values: 564 * @arg DMA_FLAG_TCx: Transfer complete flag 565 * @arg DMA_FLAG_HTx: Half transfer complete flag 566 * @arg DMA_FLAG_TEx: Transfer error flag 567 * @arg DMA_FLAG_GIx: Global interrupt flag 568 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 569 * @retval None 570 */ 571 #if defined(DMA2) 572 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 573 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 574 #else /* DMA1 */ 575 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) 576 #endif /* DMA2 */ 577 578 /** 579 * @brief Enable the specified DMA Channel interrupts. 580 * @param __HANDLE__ DMA handle 581 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 582 * This parameter can be any combination of the following values: 583 * @arg DMA_IT_TC: Transfer complete interrupt mask 584 * @arg DMA_IT_HT: Half transfer complete interrupt mask 585 * @arg DMA_IT_TE: Transfer error interrupt mask 586 * @retval None 587 */ 588 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 589 590 /** 591 * @brief Disable the specified DMA Channel interrupts. 592 * @param __HANDLE__ DMA handle 593 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 594 * This parameter can be any combination of the following values: 595 * @arg DMA_IT_TC: Transfer complete interrupt mask 596 * @arg DMA_IT_HT: Half transfer complete interrupt mask 597 * @arg DMA_IT_TE: Transfer error interrupt mask 598 * @retval None 599 */ 600 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 601 602 /** 603 * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. 604 * @param __HANDLE__ DMA handle 605 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 606 * This parameter can be one of the following values: 607 * @arg DMA_IT_TC: Transfer complete interrupt mask 608 * @arg DMA_IT_HT: Half transfer complete interrupt mask 609 * @arg DMA_IT_TE: Transfer error interrupt mask 610 * @retval The state of DMA_IT (SET or RESET). 611 */ 612 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 613 614 /** 615 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 616 * @param __HANDLE__ DMA handle 617 * @retval The number of remaining data units in the current DMA Channel transfer. 618 */ 619 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 620 621 /** 622 * @} 623 */ 624 625 /* Include DMA HAL Extension module */ 626 #include "stm32u0xx_hal_dma_ex.h" 627 628 /* Exported functions --------------------------------------------------------*/ 629 630 /** @addtogroup DMA_Exported_Functions 631 * @{ 632 */ 633 634 /** @addtogroup DMA_Exported_Functions_Group1 635 * @{ 636 */ 637 /* Initialization and de-initialization functions *****************************/ 638 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 639 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 640 /** 641 * @} 642 */ 643 644 /** @addtogroup DMA_Exported_Functions_Group2 645 * @{ 646 */ 647 /* IO operation functions *****************************************************/ 648 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 649 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 650 uint32_t DataLength); 651 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 652 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 653 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, 654 uint32_t Timeout); 655 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 656 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, 657 void (* pCallback)(DMA_HandleTypeDef *_hdma)); 658 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 659 660 /** 661 * @} 662 */ 663 664 /** @addtogroup DMA_Exported_Functions_Group3 665 * @{ 666 */ 667 /* Peripheral State and Error functions ***************************************/ 668 HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); 669 uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); 670 /** 671 * @} 672 */ 673 674 /** 675 * @} 676 */ 677 678 /* Private macros ------------------------------------------------------------*/ 679 /** @defgroup DMA_Private_Macros DMA Private Macros 680 * @{ 681 */ 682 683 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 684 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 685 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 686 687 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) 688 689 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 690 ((STATE) == DMA_PINC_DISABLE)) 691 692 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 693 ((STATE) == DMA_MINC_DISABLE)) 694 695 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) 696 697 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 698 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 699 ((SIZE) == DMA_PDATAALIGN_WORD)) 700 701 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 702 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 703 ((SIZE) == DMA_MDATAALIGN_WORD )) 704 705 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 706 ((MODE) == DMA_CIRCULAR)) 707 708 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 709 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 710 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 711 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 712 713 /** 714 * @} 715 */ 716 717 /* Private functions ---------------------------------------------------------*/ 718 719 /** 720 * @} 721 */ 722 723 /** 724 * @} 725 */ 726 727 #ifdef __cplusplus 728 } 729 #endif 730 731 #endif /* STM32U0xx_HAL_DMA_H */ 732
