1 /**
2 ******************************************************************************
3 * @file stm32u0xx_hal_cortex.c
4 * @author GPM Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 *** How to configure Interrupts using CORTEX HAL driver ***
17 ===========================================================
18 [..]
19 This section provides functions allowing to configure the NVIC interrupts (IRQ).
20 The Cortex M0+ exceptions are managed by CMSIS functions.
21 (#) Enable and Configure the priority of the selected IRQ Channels.
22 The priority can be 0..3.
23
24 -@- Lower priority values gives higher priority.
25 -@- Priority Order:
26 (#@) Lowest priority.
27 (#@) Lowest hardware priority (IRQn position).
28
29 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
30
31 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
32
33 -@- Negative value of IRQn_Type are not allowed.
34
35 *** How to configure Systick using CORTEX HAL driver ***
36 ========================================================
37 [..]
38 Setup SysTick Timer for time base.
39
40 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
41 is a CMSIS function that:
42 (++) Configures the SysTick Reload register with value passed as function parameter.
43 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
44 (++) Resets the SysTick Counter register.
45 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
46 (++) Enables the SysTick Interrupt.
47 (++) Starts the SysTick Counter.
48
49 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
50 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
51 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
52 inside the stm32u0xx_hal_cortex.h file.
53
54 (+) You can change the SysTick IRQ priority by calling the
55 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
56 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
57
58 (+) To adjust the SysTick time base, use the following formula:
59
60 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
61 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
62 (++) Reload Value should not exceed 0xFFFFFF
63
64 @endverbatim
65 ******************************************************************************
66 * @attention
67 *
68 * Copyright (c) 2023 STMicroelectronics.
69 * All rights reserved.
70 *
71 * This software is licensed under terms that can be found in the LICENSE file
72 * in the root directory of this software component.
73 * If no LICENSE file comes with this software, it is provided AS-IS.
74 *
75 ******************************************************************************
76 */
77
78 /* Includes ------------------------------------------------------------------*/
79 #include "stm32u0xx_hal.h"
80
81 /** @addtogroup STM32U0xx_HAL_Driver
82 * @{
83 */
84
85 /** @addtogroup CORTEX
86 * @{
87 */
88
89 #ifdef HAL_CORTEX_MODULE_ENABLED
90
91 /* Private types -------------------------------------------------------------*/
92 /* Private variables ---------------------------------------------------------*/
93 /* Private constants ---------------------------------------------------------*/
94 /* Private macros ------------------------------------------------------------*/
95 /* Private function prototypes -----------------------------------------------*/
96 /* Exported functions --------------------------------------------------------*/
97
98 /** @addtogroup CORTEX_Exported_Functions
99 * @{
100 */
101
102 /** @addtogroup CORTEX_Exported_Functions_Group1
103 * @brief Initialization and Configuration functions
104 *
105 @verbatim
106 ==============================================================================
107 ##### Initialization and Configuration functions #####
108 ==============================================================================
109 [..]
110 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
111 Systick functionalities
112
113 @endverbatim
114 * @{
115 */
116
117 /**
118 * @brief Sets the priority of an interrupt.
119 * @param IRQn External interrupt number .
120 * This parameter can be an enumerator of IRQn_Type enumeration
121 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32u0xx.h file)
122 * @param PreemptPriority The preemption priority for the IRQn channel.
123 * This parameter can be a value between 0 and 3.
124 * A lower priority value indicates a higher priority
125 * @param SubPriority the subpriority level for the IRQ channel.
126 * with stm32u0xx devices, this parameter is a dummy value and it is ignored, because
127 * no subpriority supported in Cortex M0+ based products.
128 * @retval None
129 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)130 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
131 {
132 /* Prevent unused argument(s) compilation warning */
133 (void)(SubPriority);
134 /* Check the parameters */
135 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
136 NVIC_SetPriority(IRQn, PreemptPriority);
137 }
138
139 /**
140 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
141 * @param IRQn External interrupt number.
142 * This parameter can be an enumerator of IRQn_Type enumeration
143 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
144 * CMSIS device file (stm32u0xxxx.h))
145 * @retval None
146 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)147 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
148 {
149 /* Check the parameters */
150 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
151
152 /* Enable interrupt */
153 NVIC_EnableIRQ(IRQn);
154 }
155
156 /**
157 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
158 * @param IRQn External interrupt number.
159 * This parameter can be an enumerator of IRQn_Type enumeration
160 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
161 * CMSIS device file (stm32u0xxxx.h))
162 * @retval None
163 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)164 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
165 {
166 /* Check the parameters */
167 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
168
169 /* Disable interrupt */
170 NVIC_DisableIRQ(IRQn);
171 }
172
173 /**
174 * @brief Initiate a system reset request to reset the MCU.
175 * @retval None
176 */
HAL_NVIC_SystemReset(void)177 void HAL_NVIC_SystemReset(void)
178 {
179 /* System Reset */
180 NVIC_SystemReset();
181 }
182
183 /**
184 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
185 * Counter is in free running mode to generate periodic interrupts.
186 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
187 * @retval status: - 0 Function succeeded.
188 * - 1 Function failed.
189 */
HAL_SYSTICK_Config(uint32_t TicksNumb)190 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
191 {
192 return SysTick_Config(TicksNumb);
193 }
194 /**
195 * @}
196 */
197
198 /** @addtogroup CORTEX_Exported_Functions_Group2
199 * @brief Cortex control functions
200 *
201 @verbatim
202 ==============================================================================
203 ##### Peripheral Control functions #####
204 ==============================================================================
205 [..]
206 This subsection provides a set of functions allowing to control the CORTEX
207 (NVIC, SYSTICK, MPU) functionalities.
208
209
210 @endverbatim
211 * @{
212 */
213
214 /**
215 * @brief Get the priority of an interrupt.
216 * @param IRQn External interrupt number.
217 * This parameter can be an enumerator of IRQn_Type enumeration
218 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
219 * CMSIS device file (stm32u0xxxx.h))
220 * @retval None
221 */
HAL_NVIC_GetPriority(IRQn_Type IRQn)222 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
223 {
224 /* Get priority for Cortex-M system or device specific interrupts */
225 return NVIC_GetPriority(IRQn);
226 }
227
228 /**
229 * @brief Set Pending bit of an external interrupt.
230 * @param IRQn External interrupt number
231 * This parameter can be an enumerator of IRQn_Type enumeration
232 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
233 * CMSIS device file (stm32u0xxxx.h))
234 * @retval None
235 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)236 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
237 {
238 /* Check the parameters */
239 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
240
241 /* Set interrupt pending */
242 NVIC_SetPendingIRQ(IRQn);
243 }
244
245 /**
246 * @brief Get Pending Interrupt (read the pending register in the NVIC
247 * and return the pending bit for the specified interrupt).
248 * @param IRQn External interrupt number.
249 * This parameter can be an enumerator of IRQn_Type enumeration
250 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
251 * CMSIS device file (stm32u0xxxx.h))
252 * @retval status: - 0 Interrupt status is not pending.
253 * - 1 Interrupt status is pending.
254 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)255 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
256 {
257 /* Check the parameters */
258 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
259
260 /* Return 1 if pending else 0 */
261 return NVIC_GetPendingIRQ(IRQn);
262 }
263
264 /**
265 * @brief Clear the pending bit of an external interrupt.
266 * @param IRQn External interrupt number.
267 * This parameter can be an enumerator of IRQn_Type enumeration
268 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
269 * CMSIS device file (stm32u0xxxx.h))
270 * @retval None
271 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)272 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
273 {
274 /* Check the parameters */
275 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
276
277 /* Clear pending interrupt */
278 NVIC_ClearPendingIRQ(IRQn);
279 }
280
281 /**
282 * @brief Configure the SysTick clock source.
283 * @param CLKSource specifies the SysTick clock source.
284 * This parameter can be one of the following values:
285 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
286 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
287 * @retval None
288 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)289 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
290 {
291 /* Check the parameters */
292 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
293 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
294 {
295 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
296 }
297 else
298 {
299 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
300 }
301 }
302
303 /**
304 * @brief Handle SYSTICK interrupt request.
305 * @retval None
306 */
HAL_SYSTICK_IRQHandler(void)307 void HAL_SYSTICK_IRQHandler(void)
308 {
309 HAL_SYSTICK_Callback();
310 }
311
312 /**
313 * @brief SYSTICK callback.
314 * @retval None
315 */
HAL_SYSTICK_Callback(void)316 __weak void HAL_SYSTICK_Callback(void)
317 {
318 /* NOTE : This function should not be modified, when the callback is needed,
319 the HAL_SYSTICK_Callback could be implemented in the user file
320 */
321 }
322
323 #if (__MPU_PRESENT == 1U)
324 /**
325 * @brief Enable the MPU.
326 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
327 * NMI, FAULTMASK and privileged access to the default memory
328 * This parameter can be one of the following values:
329 * @arg MPU_HFNMI_PRIVDEF_NONE
330 * @arg MPU_HARDFAULT_NMI
331 * @arg MPU_PRIVILEGED_DEFAULT
332 * @arg MPU_HFNMI_PRIVDEF
333 * @retval None
334 */
HAL_MPU_Enable(uint32_t MPU_Control)335 void HAL_MPU_Enable(uint32_t MPU_Control)
336 {
337 /* Enable the MPU */
338 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
339
340 /* Ensure MPU setting take effects */
341 __DSB();
342 __ISB();
343 }
344
345 /**
346 * @brief Disable the MPU.
347 * @retval None
348 */
HAL_MPU_Disable(void)349 void HAL_MPU_Disable(void)
350 {
351 /* Make sure outstanding transfers are done */
352 __DMB();
353
354 /* Disable the MPU and clear the control register*/
355 MPU->CTRL = 0;
356 }
357
358 /**
359 * @brief Enable the MPU Region.
360 * @retval None
361 */
HAL_MPU_EnableRegion(uint32_t RegionNumber)362 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
363 {
364 /* Check the parameters */
365 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
366
367 /* Set the Region number */
368 MPU->RNR = RegionNumber;
369
370 /* Enable the Region */
371 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
372 }
373
374 /**
375 * @brief Disable the MPU Region.
376 * @retval None
377 */
HAL_MPU_DisableRegion(uint32_t RegionNumber)378 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
379 {
380 /* Check the parameters */
381 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
382
383 /* Set the Region number */
384 MPU->RNR = RegionNumber;
385
386 /* Disable the Region */
387 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
388 }
389
390 /**
391 * @brief Initialize and configure the Region and the memory to be protected.
392 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
393 * the initialization and configuration information.
394 * @retval None
395 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * const MPU_Init)396 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const MPU_Init)
397 {
398 /* Check the parameters */
399 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
400 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
401 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
402 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
403 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
404 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
405 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
406 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
407 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
408 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
409
410 /* Set the Region number */
411 MPU->RNR = MPU_Init->Number;
412
413 /* Disable the Region */
414 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
415
416 /* Apply configuration */
417 MPU->RBAR = MPU_Init->BaseAddress;
418 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
419 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
420 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
421 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
422 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
423 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
424 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
425 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
426 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
427 }
428 #endif /* __MPU_PRESENT */
429
430 /**
431 * @}
432 */
433
434 /**
435 * @}
436 */
437
438 #endif /* HAL_CORTEX_MODULE_ENABLED */
439 /**
440 * @}
441 */
442
443 /**
444 * @}
445 */
446
