1 /** 2 ****************************************************************************** 3 * @file stm32u0xx_hal.h 4 * @author GPM Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file in 14 * the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U0xx_HAL_H 21 #define STM32U0xx_HAL_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u0xx_hal_conf.h" 29 30 /** @addtogroup STM32U0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup HAL HAL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /* Exported constants --------------------------------------------------------*/ 40 41 /** @defgroup HAL_Exported_Constants HAL Exported Constants 42 * @{ 43 */ 44 45 /** @defgroup HAL_TICK_FREQ Tick Frequency 46 * @{ 47 */ 48 #define HAL_TICK_FREQ_10HZ 100U 49 #define HAL_TICK_FREQ_100HZ 10U 50 #define HAL_TICK_FREQ_1KHZ 1U 51 #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ 52 53 /** 54 * @} 55 */ 56 57 /** 58 * @} 59 */ 60 61 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 62 * @{ 63 */ 64 65 /** @defgroup SYSCFG_BootMode Boot Mode 66 * @{ 67 */ 68 #define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ 69 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ 70 #define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ 71 72 /** 73 * @} 74 */ 75 76 /** @defgroup SYSCFG_Break Break 77 * @{ 78 */ 79 #define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16 */ 80 #if defined(SYSCFG_CFGR2_PVDL) 81 #define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 82 #endif /* SYSCFG_CFGR2_PVDL */ 83 #define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CCL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16 */ 84 #define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16 */ 85 /** 86 * @} 87 */ 88 89 /** @defgroup HAL_Pin_remapping Pin remapping 90 * @{ 91 */ 92 /* Only available on cut2.0 */ 93 #define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ 94 #define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ 95 /** 96 * @} 97 */ 98 99 /** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection 100 * @{ 101 */ 102 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ 103 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ 104 #define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup HAL_IR_POL_SEL IR output polarity selection 111 * @{ 112 */ 113 #define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 0: IR output polarity not inverted */ 114 #define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 1: IR output polarity inverted */ 115 116 /** 117 * @} 118 */ 119 120 #if defined(VREFBUF) 121 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 122 * @{ 123 */ 124 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V. 125 This requires VDDA equal to or higher than 2.4 V. */ 126 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V. 127 This requires VDDA equal to or higher than 2.8 V. */ 128 129 /** 130 * @} 131 */ 132 133 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 134 * @{ 135 */ 136 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 137 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 138 139 /** 140 * @} 141 */ 142 #endif /* VREFBUF */ 143 144 /** @defgroup SYSCFG_flags_definition Flags 145 * @{ 146 */ 147 #define SYSCFG_FLAG_SRAM1_PE SYSCFG_CFGR2_SPF /*!< SRAM1 parity error */ 148 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_BKPF /*!< SRAM2 parity error */ 149 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 150 /** 151 * @} 152 */ 153 154 /** @defgroup SYSCFG_COMPMODE_GROUP SYSCFG TSC IO COMP MODE 155 * @{ 156 */ 157 #define SYSCFG_COMP_MODE_GRP2_IO1 SYSCFG_TSCCR_G2IO1 /*!< Enable comparator mode for group 2 on I/O 1 */ 158 #define SYSCFG_COMP_MODE_GRP2_IO3 SYSCFG_TSCCR_G2IO3 /*!< Enable comparator mode for group 2 on I/O 3 */ 159 #define SYSCFG_COMP_MODE_GRP4_IO1 SYSCFG_TSCCR_G4IO1 /*!< Enable comparator mode for group 4 on I/O 1 */ 160 #define SYSCFG_COMP_MODE_GRP6_IO1 SYSCFG_TSCCR_G6IO1 /*!< Enable comparator mode for group 6 on I/O 1 */ 161 #define SYSCFG_COMP_MODE_GRP7_IO2 SYSCFG_TSCCR_G7IO2 /*!< Enable comparator mode for group 7 on I/O 2 */ 162 /** 163 * @} 164 */ 165 166 /** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO 167 * @brief Fast mode Plus driving capability on a specific GPIO 168 * @{ 169 */ 170 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ 171 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ 172 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ 173 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ 174 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ 175 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ 176 /** 177 * @} 178 */ 179 180 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper 181 * @brief ISR Wrapper 182 * @{ 183 */ 184 #define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ 185 #define HAL_SYSCFG_ITLINE1 0x00000001U /*!< Internal define for macro handling */ 186 #define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ 187 #define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ 188 #define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ 189 #define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ 190 #define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ 191 #define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ 192 #define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ 193 #define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ 194 #define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ 195 #define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ 196 #define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ 197 #define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ 198 #define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ 199 #define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */ 200 #define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ 201 #define HAL_SYSCFG_ITLINE17 0x00000011U /*!< Internal define for macro handling */ 202 #define HAL_SYSCFG_ITLINE18 0x00000012U /*!< Internal define for macro handling */ 203 #define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ 204 #define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */ 205 #define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ 206 #define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ 207 #define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ 208 #define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */ 209 #define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ 210 #define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */ 211 #define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ 212 #define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ 213 #define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */ 214 #define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */ 215 #define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */ 216 217 #define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG has expired .... */ 218 #if defined (SYSCFG_ITLINE1_SR_PVDOUT) 219 #define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT) /*!< Power voltage detection Interrupt .... */ 220 #endif /* SYSCFG_ITLINE1_SR_PVDOUT */ 221 #if defined (SYSCFG_ITLINE1_SR_VDDUSB) 222 #define HAL_ITLINE_VDDUSB ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDUSB) /*!< VDDUSB supply monitoring Interrupt .... */ 223 #endif /* SYSCFG_ITLINE1_SR_VDDUSB */ 224 #if defined (SYSCFG_ITLINE1_SR_VDDADC) 225 #define HAL_ITLINE_VDDADC ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDADC) /*!< VDDADC supply monitoring Interrupt .... */ 226 #endif /* SYSCFG_ITLINE1_SR_VDDADC */ 227 #if defined (SYSCFG_ITLINE1_SR_VDDDAC) 228 #define HAL_ITLINE_VDDDAC ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDDAC) /*!< VDDDAC supply monitoring Interrupt .... */ 229 #endif /* SYSCFG_ITLINE1_SR_VDDDAC */ 230 #define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC -> exti[28] Interrupt */ 231 #define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER) /*!< TAMPER -> exti[29] interrupt .... */ 232 #define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC) /*!< Flash ECC Interrupt */ 233 #define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ 234 #define HAL_ITLINE_RCC ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_RCC) /*!< RCC Interrupt */ 235 #define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< RCC Interrupt */ 236 #define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ 237 #define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ 238 #define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ 239 #define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ 240 #define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ 241 #define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ 242 #define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ 243 #define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ 244 #define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ 245 #define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ 246 #define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ 247 #define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ 248 #define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ 249 #define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ 250 #define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ 251 #define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ 252 #if defined (SYSCFG_ITLINE8_SR_USBFS) 253 #define HAL_ITLINE_USBFS ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USBFS1) /*!< USBFS Interrupt */ 254 #endif /* SYSCFG_ITLINE8_SR_USBFS */ 255 #define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ 256 #define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ 257 #define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ 258 #define HAL_ITLINE_DMAMUX ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX) /*!< DMAMUX Interrupt */ 259 #define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */ 260 #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ 261 #define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */ 262 #define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */ 263 #define HAL_ITLINE_DMA1_CH8 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH8) /*!< DMA1 Channel 8 Interrupt */ 264 #define HAL_ITLINE_DMA1_CH9 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH9) /*!< DMA1 Channel 9 Interrupt */ 265 #define HAL_ITLINE_DMA1_CH10 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH10) /*!< DMA1 Channel 10 Interrupt */ 266 #define HAL_ITLINE_DMA1_CH11 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH11) /*!< DMA1 Channel 11 Interrupt */ 267 #define HAL_ITLINE_DMA1_CH12 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH12) /*!< DMA1 Channel 12 Interrupt */ 268 269 #define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ 270 #if defined (COMP1) 271 #define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1) /*!< COMP1 Interrupt -> exti[17] */ 272 #endif /* COMP1 */ 273 #if defined (COMP2) 274 #define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2) /*!< COMP2 Interrupt -> exti[18] */ 275 #endif /* COMP2 */ 276 #define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ 277 #define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ 278 #define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ 279 #define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ 280 #define HAL_ITLINE_TIM1_CC1 ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC1) /*!< TIM1 CC1 Interrupt */ 281 #define HAL_ITLINE_TIM1_CC2 ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC2) /*!< TIM1 CC2 Interrupt */ 282 #define HAL_ITLINE_TIM1_CC3 ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC3) /*!< TIM1 CC3 Interrupt */ 283 #define HAL_ITLINE_TIM1_CC4 ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC4) /*!< TIM1 CC4 Interrupt */ 284 #if defined (TIM2) 285 #define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB) /*!< TIM2 Interrupt */ 286 #endif /* TIM2 */ 287 #define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ 288 #if defined(TIM6) 289 #define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB) /*!< TIM6 Interrupt */ 290 #endif /* TIM6 */ 291 #if defined(DAC) 292 #define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC_GLB) /*!< DAC Interrupt */ 293 #endif /* DAC */ 294 #if defined(LPTIM1) 295 #define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB) /*!< LPTIM1 Interrupt -> exti[24] */ 296 #endif /* LPTIM1 */ 297 #if defined(TIM7) 298 #define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB) /*!< TIM7 Interrupt */ 299 #endif /* TIM7 */ 300 #if defined(LPTIM2) 301 #define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB) /*!< LPTIM2 Interrupt -> exti[25] */ 302 #endif /* LPTIM2 */ 303 #define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ 304 #if defined(TIM15) 305 #define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM15_GLB) /*!< TIM15 Interrupt */ 306 #endif /* TIM15 */ 307 #if defined(TIM16) 308 #define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM16_GLB) /*!< TIM16 Interrupt */ 309 #endif /* TIM16 */ 310 #if defined(LPTIM3) 311 #define HAL_ITLINE_LPTIM3 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM3_GLB) /*!< LPTIM3 Interrupt -> exti[26] */ 312 #endif /* LPTIM3 */ 313 314 #define HAL_ITLINE_TSC_MCE ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TSC_MCE) /*!< TSC MCE Interrupt */ 315 #define HAL_ITLINE_TSC_EOA ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TSC_EOA) /*!< TSC EOA Interrupt */ 316 317 #define HAL_ITLINE_LCD ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE21_SR_LCD) /*!< LCD Interrupt */ 318 319 #define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt -> exti[33] */ 320 #define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C2 Interrupt */ 321 322 #define HAL_ITLINE_I2C4 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C4_GLB) /*!< I2C4 Interrupt */ 323 #define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C4_GLB) /*!< I2C3 Interrupt */ 324 325 #define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ 326 #define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2) /*!< SPI2 Interrupt */ 327 #define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt -> exti[25] */ 328 #define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt -> exti[26] */ 329 #define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB) /*!< LPUART2 GLB Interrupt -> exti[31] */ 330 #if defined(USART3) 331 #define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 Interrupt .... */ 332 #endif /* USART3 */ 333 #if defined (LPUART1) 334 #define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/ 335 #endif /* LPUART1 */ 336 #if defined(USART4) 337 #define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_USART4_GLB) /*!< USART4 Interrupt .... */ 338 #endif /* USART4 */ 339 #if defined (LPUART3) 340 #define HAL_ITLINE_LPUART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART3_GLB) /*!< LPUART3 Interrupt -> exti[32]*/ 341 #endif /* LPUART3 */ 342 343 #if defined (RNG) 344 #define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG) /*!< RNG Interrupt */ 345 #endif /* RNG */ 346 #if defined (AES) 347 #define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES) /*!< AES Interrupt */ 348 #endif /* AES */ 349 /** 350 * @} 351 */ 352 353 /** 354 * @} 355 */ 356 357 /* Exported macros -----------------------------------------------------------*/ 358 /** @defgroup HAL_Exported_Macros HAL Exported Macros 359 * @{ 360 */ 361 362 /** @defgroup DBG_Exported_Macros DBG Exported Macros 363 * @{ 364 */ 365 366 /** @brief Freeze and Unfreeze Peripherals in Debug mode 367 */ 368 #if defined(DBGMCU_APBFZ1_DBG_TIM2_STOP) 369 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM2_STOP) 370 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM2_STOP) 371 #endif /* DBGMCU_APBFZ1_DBG_TIM2_STOP */ 372 373 #if defined(DBGMCU_APBFZ1_DBG_TIM3_STOP) 374 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM3_STOP) 375 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM3_STOP) 376 #endif /* DBGMCU_APBFZ1_DBG_TIM3_STOP */ 377 378 #if defined(DBGMCU_APBFZ1_DBG_TIM4_STOP) 379 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM4_STOP) 380 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM4_STOP) 381 #endif /* DBGMCU_APBFZ1_DBG_TIM4_STOP */ 382 383 #if defined(DBGMCU_APBFZ1_DBG_TIM6_STOP) 384 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM6_STOP) 385 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM6_STOP) 386 #endif /* DBGMCU_APBFZ1_DBG_TIM6_STOP */ 387 388 #if defined(DBGMCU_APBFZ1_DBG_TIM7_STOP) 389 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM7_STOP) 390 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_TIM7_STOP) 391 #endif /* DBGMCU_APBFZ1_DBG_TIM7_STOP */ 392 393 #if defined(DBGMCU_APBFZ1_DBG_RTC_STOP) 394 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_RTC_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_RTC_STOP) 396 #endif /* DBGMCU_APBFZ1_DBG_RTC_STOP */ 397 398 #if defined(DBGMCU_APBFZ1_DBG_WWDG_STOP) 399 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_WWDG_STOP) 400 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_WWDG_STOP) 401 #endif /* DBGMCU_APBFZ1_DBG_WWDG_STOP */ 402 403 #if defined(DBGMCU_APBFZ1_DBG_IWDG_STOP) 404 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_IWDG_STOP) 405 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_IWDG_STOP) 406 #endif /* DBGMCU_APBFZ1_DBG_IWDG_STOP */ 407 408 #if defined(DBGMCU_APBFZ1_DBG_I2C3_STOP) 409 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_I2C3_STOP) 410 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_I2C3_STOP) 411 #endif /* DBGMCU_APBFZ1_DBG_I2C3_STOP */ 412 413 #if defined(DBGMCU_APBFZ1_DBG_I2C1_STOP) 414 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_I2C1_STOP) 415 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_I2C1_STOP) 416 #endif /* DBGMCU_APBFZ1_DBG_I2C1_STOP */ 417 418 #if defined(DBGMCU_APBFZ1_DBG_LPTIM2_STOP) 419 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_LPTIM2_STOP) 420 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_LPTIM2_STOP) 421 #endif /* DBGMCU_APBFZ1_DBG_LPTIM2_STOP */ 422 423 #if defined(DBGMCU_APBFZ1_DBG_LPTIM1_STOP) 424 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_LPTIM1_STOP) 425 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APBFZ1, DBGMCU_APBFZ1_DBG_LPTIM1_STOP) 426 #endif /* DBGMCU_APBFZ1_DBG_LPTIM1_STOP */ 427 428 #if defined(DBGMCU_APBFZ2_DBG_TIM1_STOP) 429 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM1_STOP) 430 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM1_STOP) 431 #endif /* DBGMCU_APBFZ2_DBG_TIM1_STOP */ 432 433 #if defined(DBGMCU_APBFZ2_DBG_TIM14_STOP) 434 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM14_STOP) 435 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM14_STOP) 436 #endif /* DBGMCU_APBFZ2_DBG_TIM14_STOP */ 437 438 #if defined(DBGMCU_APBFZ2_DBG_TIM15_STOP) 439 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM15_STOP) 440 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM15_STOP) 441 #endif /* DBGMCU_APBFZ2_DBG_TIM15_STOP */ 442 443 #if defined(DBGMCU_APBFZ2_DBG_TIM16_STOP) 444 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM16_STOP) 445 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_TIM16_STOP) 446 #endif /* DBGMCU_APBFZ2_DBG_TIM16_STOP */ 447 448 #if defined(DBGMCU_APBFZ2_DBG_LPTIM3_STOP) 449 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_LPTIM3_STOP) 450 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APBFZ2, DBGMCU_APBFZ2_DBG_LPTIM3_STOP) 451 #endif /* DBGMCU_APBFZ2_DBG_LPTIM3_STOP */ 452 453 /** 454 * @} 455 */ 456 457 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 458 * @{ 459 */ 460 461 /** @brief Main Flash memory mapped at 0x00000000 462 */ 463 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 464 465 /** @brief System Flash memory mapped at 0x00000000 466 */ 467 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 468 469 /** @brief Embedded SRAM mapped at 0x00000000 470 */ 471 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, \ 472 (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)) 473 474 /** 475 * @brief Return the boot mode as configured by user. 476 * @retval The boot mode as configured by user. The returned value can be one 477 * of the following values @ref SYSCFG_BootMode 478 */ 479 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 480 481 /** @brief SYSCFG Break ECC lock. 482 * Enable and lock the connection of Flash ECC error connection to TIM1 Break input. 483 * @note The selected configuration is locked and can be unlocked only by system reset. 484 */ 485 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 486 487 /** @brief SYSCFG Break Cortex-M0+ Lockup lock. 488 * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input 489 * @note The selected configuration is locked and can be unlocked only by system reset. 490 */ 491 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CCL) 492 493 #if defined(SYSCFG_CFGR2_PVDL) 494 /** @brief SYSCFG Break PVD lock. 495 * Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] 496 * in the PWR_CR register 497 * @note The selected configuration is locked and can be unlocked only by system reset 498 */ 499 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 500 #endif /* SYSCFG_CFGR2_PVDL */ 501 502 /** @brief SYSCFG Break SRAM PARITY lock 503 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17 504 * @note The selected configuration is locked and can only be unlocked by system reset 505 */ 506 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL) 507 508 /** @brief Check SYSCFG flag is set or not. 509 * @param __FLAG__ specifies the flag to check. 510 * This parameter can be one of the following values: 511 * @arg @ref SYSCFG_FLAG_SRAM1_PE SRAM1 Parity Error Flag 512 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 513 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 514 * @retval The new state of __FLAG__ (TRUE or FALSE). 515 */ 516 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) \ 517 ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__)) != 0U) ? 1U : 0U) 518 519 /** @brief Set the PEF bit to clear the SRAM Parity Error Flag. 520 * @param __FLAG__ specifies the flag to clear. 521 * This parameter can be one of the following values: 522 * @arg @ref SYSCFG_FLAG_SRAM1_PE SRAM1 Parity Error Flag 523 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 524 */ 525 #define __HAL_SYSCFG_CLEAR_FLAG(__FLAG__) \ 526 do{ \ 527 assert_param(IS_SYSCFG_PARITYFLAG((__FLAG__)));\ 528 SET_BIT(SYSCFG->CFGR2, (__FLAG__));\ 529 } while(0U) 530 531 /** @brief Fast-mode Plus driving capability enable/disable macros 532 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 533 */ 534 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 535 do { \ 536 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 537 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 538 } while(0U) 539 540 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 541 do { \ 542 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 543 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 544 } while(0U) 545 546 /** @brief ISR wrapper check 547 * @note Allow to determine interrupt source per line. 548 */ 549 #define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] &\ 550 ((__SOURCE__) & 0x00FFFFFFU)) 551 552 /** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register 553 * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL 554 */ 555 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ 556 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ 557 SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ 558 }while(0U) 559 560 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) 561 562 /** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register 563 * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL 564 */ 565 #define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ 566 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ 567 SET_BIT(SYSCFG->CFGR1,(__SEL__));\ 568 }while(0U) 569 570 /** 571 * @brief Return the IROut Polarity mode as configured by user. 572 * @retval The IROut polarity as configured by user. The returned value can be one 573 * of @ref HAL_IR_POL_SEL 574 */ 575 #define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) 576 577 /** @brief Break input to TIM1/15/16 capability enable/disable macros 578 * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break 579 */ 580 #define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 581 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ 582 }while(0U) 583 584 #define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 585 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ 586 }while(0U) 587 /** 588 * @} 589 */ 590 591 /** 592 * @} 593 */ 594 595 /* Private macros ------------------------------------------------------------*/ 596 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 597 * @{ 598 */ 599 #if defined (PWR_PVD_SUPPORT) 600 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ 601 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 602 ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 603 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 604 #else 605 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ 606 ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 607 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 608 #endif /* PWR_PVD_SUPPORT */ 609 610 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ 611 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ 612 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) 613 614 #define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ 615 ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) 616 617 #if defined(VREFBUF) 618 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 619 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 620 621 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 622 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 623 624 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 625 #endif /* VREFBUF */ 626 627 #define IS_SYSCFG_COMPMODE(__COMPMODEIO__) \ 628 ((((__COMPMODEIO__) & SYSCFG_COMP_MODE_GRP2_IO1) == SYSCFG_COMP_MODE_GRP2_IO1) || \ 629 (((__COMPMODEIO__) & SYSCFG_COMP_MODE_GRP2_IO3) == SYSCFG_COMP_MODE_GRP2_IO3) || \ 630 (((__COMPMODEIO__) & SYSCFG_COMP_MODE_GRP4_IO1) == SYSCFG_COMP_MODE_GRP4_IO1) || \ 631 (((__COMPMODEIO__) & SYSCFG_COMP_MODE_GRP6_IO1) == SYSCFG_COMP_MODE_GRP6_IO1) || \ 632 (((__COMPMODEIO__) & SYSCFG_COMP_MODE_GRP7_IO2) == SYSCFG_COMP_MODE_GRP7_IO2)) 633 634 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ 635 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ 636 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 637 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 638 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 639 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 640 641 #define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ 642 ((RMP) == SYSCFG_REMAP_PA12) || \ 643 ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) 644 645 #define IS_SYSCFG_PARITYFLAG(__FLAG__) (((__FLAG__) == SYSCFG_FLAG_SRAM1_PE) || \ 646 ((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)) 647 /** 648 * @} 649 */ 650 651 /** @defgroup HAL_Private_Macros HAL Private Macros 652 * @{ 653 */ 654 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 655 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 656 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 657 /** 658 * @} 659 */ 660 /* Exported functions --------------------------------------------------------*/ 661 662 /** @defgroup HAL_Exported_Functions HAL Exported Functions 663 * @{ 664 */ 665 666 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 667 * @{ 668 */ 669 670 /* Initialization and Configuration functions ******************************/ 671 HAL_StatusTypeDef HAL_Init(void); 672 HAL_StatusTypeDef HAL_DeInit(void); 673 void HAL_MspInit(void); 674 void HAL_MspDeInit(void); 675 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 676 677 /** 678 * @} 679 */ 680 681 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 682 * @{ 683 */ 684 685 /* Peripheral Control functions ************************************************/ 686 void HAL_IncTick(void); 687 void HAL_Delay(uint32_t Delay); 688 uint32_t HAL_GetTick(void); 689 uint32_t HAL_GetTickPrio(void); 690 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); 691 uint32_t HAL_GetTickFreq(void); 692 void HAL_SuspendTick(void); 693 void HAL_ResumeTick(void); 694 uint32_t HAL_GetHalVersion(void); 695 uint32_t HAL_GetREVID(void); 696 uint32_t HAL_GetDEVID(void); 697 uint32_t HAL_GetUIDw0(void); 698 uint32_t HAL_GetUIDw1(void); 699 uint32_t HAL_GetUIDw2(void); 700 701 /** 702 * @} 703 */ 704 705 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions 706 * @{ 707 */ 708 709 /* DBGMCU Peripheral Control functions *****************************************/ 710 void HAL_DBGMCU_EnableDBGStopMode(void); 711 void HAL_DBGMCU_DisableDBGStopMode(void); 712 void HAL_DBGMCU_EnableDBGStandbyMode(void); 713 void HAL_DBGMCU_DisableDBGStandbyMode(void); 714 715 /** 716 * @} 717 */ 718 719 /* Exported variables ---------------------------------------------------------*/ 720 /** @addtogroup HAL_Exported_Variables 721 * @{ 722 */ 723 extern __IO uint32_t uwTick; 724 extern uint32_t uwTickPrio; 725 extern uint32_t uwTickFreq; 726 /** 727 * @} 728 */ 729 730 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions 731 * @{ 732 */ 733 734 /* SYSCFG Control functions ****************************************************/ 735 736 #if defined(VREFBUF) 737 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 738 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 739 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 740 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 741 void HAL_SYSCFG_DisableVREFBUF(void); 742 #endif /* VREFBUF */ 743 744 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 745 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 746 void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); 747 void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); 748 void HAL_SYSCFG_EnableTSCComparatorMode(void); 749 void HAL_SYSCFG_DisableTSCComparatorMode(void); 750 void HAL_SYSCFG_SetTSCComparatorModeIO(uint32_t CompModeIOGRP); 751 uint32_t HAL_SYSCFG_GetTSCComparatorModeIO(uint32_t CompModeIOGRP); 752 void HAL_SYSCFG_ClearTSCComparatorModeIO(uint32_t CompModeIOGRP); 753 void HAL_SYSCFG_LockSRAM2(void); 754 void HAL_SYSCFG_UnlockSRAM2(void); 755 void HAL_SYSCFG_EraseSRAM2(void); 756 757 /** 758 * @} 759 */ 760 761 /** 762 * @} 763 */ 764 765 /** 766 * @} 767 */ 768 769 /** 770 * @} 771 */ 772 773 #ifdef __cplusplus 774 } 775 #endif 776 777 #endif /* STM32U0xx_HAL_H */ 778
