1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_LL_FMC_H 21 #define STM32N6xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK4)) 46 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 51 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 54 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 55 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 59 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 60 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 61 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 62 ((__MODE__) == FMC_ACCESS_MODE_D)) 63 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 64 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 65 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 66 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 67 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 68 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 69 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 70 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 71 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 72 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 73 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 74 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 75 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 76 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 77 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 78 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 79 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 80 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 81 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 82 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 83 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 84 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 85 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 86 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 87 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 88 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 89 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 90 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 91 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 92 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 93 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 94 95 96 #define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK1) || \ 97 ((__BANK__) == FMC_NAND_BANK2) || \ 98 ((__BANK__) == FMC_NAND_BANK3) || \ 99 ((__BANK__) == FMC_NAND_BANK4)) 100 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 101 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 102 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 103 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 104 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 105 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 106 107 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 108 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 109 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 110 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 113 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 114 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 115 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 116 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 117 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 118 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 120 121 122 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ 123 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ 124 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) 125 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ 126 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 127 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ 128 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ 129 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 130 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ 131 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 132 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ 133 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ 134 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 135 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ 136 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ 137 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ 138 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ 139 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ 140 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ 141 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 142 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ 143 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ 144 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 145 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 146 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 147 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 148 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 149 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 150 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 151 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 152 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) 153 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) 154 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) 155 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 156 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ 157 ((__BANK__) == FMC_SDRAM_BANK2)) 158 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ 159 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ 160 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ 161 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 162 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ 163 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ 164 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) 165 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ 166 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 167 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ 168 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ 169 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) 170 171 172 /** 173 * @} 174 */ 175 176 /* Exported typedef ----------------------------------------------------------*/ 177 178 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 179 * @{ 180 */ 181 182 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 183 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 184 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 185 #define FMC_COMMON_TypeDef FMC_Common_TypeDef 186 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 187 188 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 189 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 190 #define FMC_NAND_DEVICE FMC_Bank3_R 191 #define FMC_COMMON_DEVICE FMC_Common_R 192 #define FMC_SDRAM_DEVICE FMC_Bank5_6_R 193 194 /** 195 * @brief FMC NORSRAM Configuration Structure definition 196 */ 197 typedef struct 198 { 199 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 200 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 201 202 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 203 multiplexed on the data bus or not. 204 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ 205 206 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 207 the corresponding memory device. 208 This parameter can be a value of @ref FMC_Memory_Type */ 209 210 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 211 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 212 213 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 214 valid only with synchronous burst Flash memories. 215 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 216 217 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 218 the Flash memory in burst mode. 219 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 220 221 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 222 clock cycle before the wait state or during the wait state, 223 valid only when accessing memories in burst mode. 224 This parameter can be a value of @ref FMC_Wait_Timing */ 225 226 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device 227 by the FMC. 228 This parameter can be a value of @ref FMC_Write_Operation */ 229 230 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 231 signal, valid for Flash memory access in burst mode. 232 This parameter can be a value of @ref FMC_Wait_Signal */ 233 234 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 235 This parameter can be a value of @ref FMC_Extended_Mode */ 236 237 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 238 valid only with asynchronous Flash memories. 239 This parameter can be a value of @ref FMC_AsynchronousWait */ 240 241 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 242 This parameter can be a value of @ref FMC_Write_Burst */ 243 244 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 245 This parameter is only enabled through the FMC_BCR1 register, 246 and don't care through FMC_BCR2..4 registers. 247 This parameter can be a value of @ref FMC_Continous_Clock */ 248 249 uint32_t PageSize; /*!< Specifies the memory page size. 250 This parameter can be a value of @ref FMC_Page_Size */ 251 252 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 253 This parameter can be a value of @ref FMC_Byte_Lane */ 254 } FMC_NORSRAM_InitTypeDef; 255 256 /** 257 * @brief FMC NORSRAM Timing parameters structure definition 258 */ 259 typedef struct 260 { 261 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 262 the duration of the address setup time. 263 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 264 @note This parameter is not used with synchronous NOR Flash memories. */ 265 266 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 267 the duration of the address hold time. 268 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 269 @note This parameter is not used with synchronous NOR Flash memories. */ 270 271 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 272 the duration of the data setup time. 273 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 274 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 275 NOR Flash memories. */ 276 277 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 278 the duration of the data hold time. 279 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 280 @note This parameter is used for used in asynchronous accesses. */ 281 282 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 283 the duration of the bus turnaround. 284 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 285 @note This parameter is only used for multiplexed NOR Flash memories. */ 286 287 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 288 HCLK cycles. This parameter can be a value between Min_Data = 2 and 289 Max_Data = 16. 290 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 291 accesses. */ 292 293 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 294 to the memory before getting the first data. 295 The parameter value depends on the memory type as shown below: 296 - It must be set to 0 in case of a CRAM 297 - It is don't care in asynchronous NOR, SRAM or ROM accesses 298 - It may assume a value between Min_Data = 2 and Max_Data = 17 299 in NOR Flash memories with synchronous burst mode enable */ 300 301 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 302 This parameter can be a value of @ref FMC_Access_Mode */ 303 } FMC_NORSRAM_TimingTypeDef; 304 305 /** 306 * @brief FMC NAND Configuration Structure definition 307 */ 308 typedef struct 309 { 310 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 311 This parameter can be a value of @ref FMC_NAND_Bank */ 312 313 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 314 This parameter can be any value of @ref FMC_Wait_feature */ 315 316 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 317 This parameter can be any value of @ref FMC_NAND_Data_Width */ 318 319 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 320 This parameter can be any value of @ref FMC_ECC */ 321 322 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 323 This parameter can be any value of @ref FMC_ECC_Page_Size */ 324 325 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 326 delay between CLE low and RE low. 327 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 328 329 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 330 delay between ALE low and RE low. 331 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 332 } FMC_NAND_InitTypeDef; 333 334 /** 335 * @brief FMC NAND Timing parameters structure definition 336 */ 337 typedef struct 338 { 339 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 340 the command assertion for NAND-Flash read or write access 341 to common/Attribute or I/O memory space (depending on 342 the memory space timing to be configured). 343 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 344 345 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 346 command for NAND-Flash read or write access to 347 common/Attribute or I/O memory space (depending on the 348 memory space timing to be configured). 349 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 350 351 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 352 (and data for write access) after the command de-assertion 353 for NAND-Flash read or write access to common/Attribute 354 or I/O memory space (depending on the memory space timing 355 to be configured). 356 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 357 358 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 359 data bus is kept in HiZ after the start of a NAND-Flash 360 write access to common/Attribute or I/O memory space (depending 361 on the memory space timing to be configured). 362 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 363 } FMC_NAND_PCC_TimingTypeDef; 364 365 366 /** 367 * @brief FMC SDRAM Configuration Structure definition 368 */ 369 typedef struct 370 { 371 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. 372 This parameter can be a value of @ref FMC_SDRAM_Bank */ 373 374 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. 375 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ 376 377 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. 378 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ 379 380 uint32_t MemoryDataWidth; /*!< Defines the memory device width. 381 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ 382 383 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. 384 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ 385 386 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. 387 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ 388 389 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. 390 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ 391 392 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 393 to disable the clock before changing frequency. 394 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ 395 396 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. 397 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ 398 } FMC_SDRAM_InitTypeDef; 399 400 /** 401 * @brief FMC SDRAM Timing parameters structure definition 402 */ 403 typedef struct 404 { 405 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and 406 an active or Refresh command in number of memory clock cycles. 407 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 408 409 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to 410 issuing the Activate command in number of memory clock cycles. 411 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 412 413 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock 414 cycles. 415 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 416 417 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command 418 and the delay between two consecutive Refresh commands in number of 419 memory clock cycles. 420 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 421 422 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. 423 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 424 425 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command 426 in number of memory clock cycles. 427 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 428 429 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write 430 command in number of memory clock cycles. 431 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 432 } FMC_SDRAM_TimingTypeDef; 433 434 /** 435 * @brief SDRAM command parameters structure definition 436 */ 437 typedef struct 438 { 439 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. 440 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ 441 442 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. 443 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ 444 445 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued 446 in auto refresh mode. 447 This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ 448 449 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ 450 } FMC_SDRAM_CommandTypeDef; 451 /** 452 * @} 453 */ 454 455 /* Exported constants --------------------------------------------------------*/ 456 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 457 * @{ 458 */ 459 460 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 461 * @{ 462 */ 463 464 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 465 * @{ 466 */ 467 #define FMC_NORSRAM_BANK1 (0x00000000U) 468 #define FMC_NORSRAM_BANK2 (0x00000002U) 469 #define FMC_NORSRAM_BANK3 (0x00000004U) 470 #define FMC_NORSRAM_BANK4 (0x00000006U) 471 /** 472 * @} 473 */ 474 475 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 476 * @{ 477 */ 478 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 479 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 480 /** 481 * @} 482 */ 483 484 /** @defgroup FMC_Memory_Type FMC Memory Type 485 * @{ 486 */ 487 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 488 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 489 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 490 /** 491 * @} 492 */ 493 494 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 495 * @{ 496 */ 497 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 498 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 499 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 500 /** 501 * @} 502 */ 503 504 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 505 * @{ 506 */ 507 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 508 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 509 /** 510 * @} 511 */ 512 513 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 514 * @{ 515 */ 516 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 517 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 518 /** 519 * @} 520 */ 521 522 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 523 * @{ 524 */ 525 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 526 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 527 /** 528 * @} 529 */ 530 531 /** @defgroup FMC_Wait_Timing FMC Wait Timing 532 * @{ 533 */ 534 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 535 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 536 /** 537 * @} 538 */ 539 540 /** @defgroup FMC_Write_Operation FMC Write Operation 541 * @{ 542 */ 543 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 544 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 545 /** 546 * @} 547 */ 548 549 /** @defgroup FMC_Wait_Signal FMC Wait Signal 550 * @{ 551 */ 552 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 553 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 554 /** 555 * @} 556 */ 557 558 /** @defgroup FMC_Extended_Mode FMC Extended Mode 559 * @{ 560 */ 561 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 562 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 563 /** 564 * @} 565 */ 566 567 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 568 * @{ 569 */ 570 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 571 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 572 /** 573 * @} 574 */ 575 576 /** @defgroup FMC_Page_Size FMC Page Size 577 * @{ 578 */ 579 #define FMC_PAGE_SIZE_NONE (0x00000000U) 580 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 581 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 582 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 583 | FMC_BCRx_CPSIZE_1) 584 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 585 /** 586 * @} 587 */ 588 589 /** @defgroup FMC_Write_Burst FMC Write Burst 590 * @{ 591 */ 592 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 593 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 594 /** 595 * @} 596 */ 597 598 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 599 * @{ 600 */ 601 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 602 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 603 /** 604 * @} 605 */ 606 607 /** @defgroup FMC_Access_Mode FMC Access Mode 608 * @{ 609 */ 610 #define FMC_ACCESS_MODE_A (0x00000000U) 611 #define FMC_ACCESS_MODE_B (0x10000000U) 612 #define FMC_ACCESS_MODE_C (0x20000000U) 613 #define FMC_ACCESS_MODE_D (0x30000000U) 614 /** 615 * @} 616 */ 617 618 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 619 * @{ 620 */ 621 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 622 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 623 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 624 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 625 /** 626 * @} 627 */ 628 629 /** 630 * @} 631 */ 632 633 634 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 635 * @{ 636 */ 637 /** @defgroup FMC_NAND_Bank FMC NAND Bank 638 * @{ 639 */ 640 #define FMC_NAND_BANK1 (0x00000000U) 641 #define FMC_NAND_BANK2 (0x00000400U) 642 #define FMC_NAND_BANK3 (0x00000800U) 643 #define FMC_NAND_BANK4 (0x00000C00U) 644 /** 645 * @} 646 */ 647 648 /** @defgroup FMC_Wait_feature FMC Wait feature 649 * @{ 650 */ 651 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 652 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 653 /** 654 * @} 655 */ 656 657 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 658 * @{ 659 */ 660 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 661 /** 662 * @} 663 */ 664 665 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 666 * @{ 667 */ 668 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 669 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 670 /** 671 * @} 672 */ 673 674 /** @defgroup FMC_ECC FMC ECC 675 * @{ 676 */ 677 #define FMC_NAND_ECC_DISABLE (0x00000000U) 678 #define FMC_NAND_ECC_ENABLE (0x00000040U) 679 /** 680 * @} 681 */ 682 683 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 684 * @{ 685 */ 686 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 687 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 688 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 689 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 690 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 691 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 692 /** 693 * @} 694 */ 695 696 /** 697 * @} 698 */ 699 700 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 701 * @{ 702 */ 703 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank 704 * @{ 705 */ 706 #define FMC_SDRAM_BANK1 (0x00000000U) 707 #define FMC_SDRAM_BANK2 (0x00000001U) 708 /** 709 * @} 710 */ 711 712 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 713 * @{ 714 */ 715 #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) 716 #define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) 717 #define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) 718 #define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) 719 /** 720 * @} 721 */ 722 723 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number 724 * @{ 725 */ 726 #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) 727 #define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) 728 #define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) 729 /** 730 * @} 731 */ 732 733 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width 734 * @{ 735 */ 736 #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) 737 #define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) 738 #define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) 739 /** 740 * @} 741 */ 742 743 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number 744 * @{ 745 */ 746 #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) 747 #define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) 748 /** 749 * @} 750 */ 751 752 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency 753 * @{ 754 */ 755 #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) 756 #define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) 757 #define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) 758 /** 759 * @} 760 */ 761 762 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection 763 * @{ 764 */ 765 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) 766 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) 767 /** 768 * @} 769 */ 770 771 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period 772 * @{ 773 */ 774 #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) 775 #define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) 776 #define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) 777 /** 778 * @} 779 */ 780 781 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay 782 * @{ 783 */ 784 #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) 785 #define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) 786 #define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) 787 /** 788 * @} 789 */ 790 791 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode 792 * @{ 793 */ 794 #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) 795 #define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) 796 #define FMC_SDRAM_CMD_PALL (0x00000002U) 797 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) 798 #define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) 799 #define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) 800 #define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) 801 /** 802 * @} 803 */ 804 805 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target 806 * @{ 807 */ 808 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_DS2 809 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_DS1 810 #define FMC_SDRAM_CMD_TARGET_BANK1_2 (FMC_SDCMR_DS2|FMC_SDCMR_DS1) 811 /** 812 * @} 813 */ 814 815 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 816 * @{ 817 */ 818 #define FMC_SDRAM_NORMAL_MODE (0x00000000U) 819 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 820 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 821 /** 822 * @} 823 */ 824 825 /** 826 * @} 827 */ 828 829 830 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 831 * @{ 832 */ 833 #define FMC_IT_RISING_EDGE (0x00000001U) 834 #define FMC_IT_LEVEL (0x00000002U) 835 #define FMC_IT_FALLING_EDGE (0x00000004U) 836 #define FMC_IT_REFRESH_ERROR (0x00004000U) 837 /** 838 * @} 839 */ 840 841 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 842 * @{ 843 */ 844 #define FMC_FLAG_RISING_EDGE (0x00000001U) 845 #define FMC_FLAG_LEVEL (0x00000002U) 846 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 847 #define FMC_FLAG_FEMPT (0x00000040U) 848 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 849 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 850 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 851 /** 852 * @} 853 */ 854 855 /** 856 * @} 857 */ 858 859 /** 860 * @} 861 */ 862 863 /* Private macro -------------------------------------------------------------*/ 864 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 865 * @{ 866 */ 867 /** 868 * @brief Enable the FMC Peripheral. 869 * @retval None 870 */ 871 #define __FMC_ENABLE() (FMC_COMMON_DEVICE->CFGR |= FMC_CFGR_FMCEN) 872 873 /** 874 * @brief Disable the FMC Peripheral. 875 * @retval None 876 */ 877 #define __FMC_DISABLE() (FMC_COMMON_DEVICE->CFGR &= ~FMC_CFGR_FMCEN) 878 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 879 * @brief macros to handle NOR device enable/disable and read/write operations 880 * @{ 881 */ 882 883 /** 884 * @brief Enable the NORSRAM device access. 885 * @param __INSTANCE__ FMC_NORSRAM Instance 886 * @param __BANK__ FMC_NORSRAM Bank 887 * @retval None 888 */ 889 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 890 |= FMC_BCRx_MBKEN) 891 892 /** 893 * @brief Disable the NORSRAM device access. 894 * @param __INSTANCE__ FMC_NORSRAM Instance 895 * @param __BANK__ FMC_NORSRAM Bank 896 * @retval None 897 */ 898 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 899 &= ~FMC_BCRx_MBKEN) 900 901 /** 902 * @} 903 */ 904 905 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 906 * @brief macros to handle NAND device enable/disable 907 * @{ 908 */ 909 910 /** 911 * @brief Enable the NAND device access. 912 * @param __INSTANCE__ FMC_NAND Instance 913 * @retval None 914 */ 915 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 916 917 /** 918 * @brief Disable the NAND device access. 919 * @param __INSTANCE__ FMC_NAND Instance 920 * @param __BANK__ FMC_NAND Bank 921 * @retval None 922 */ 923 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 924 925 /** 926 * @} 927 */ 928 929 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 930 * @brief macros to handle NAND interrupts 931 * @{ 932 */ 933 934 /** 935 * @brief Enable the NAND device interrupt. 936 * @param __INSTANCE__ FMC_NAND instance 937 * @param __INTERRUPT__ FMC_NAND interrupt 938 * This parameter can be any combination of the following values: 939 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 940 * @arg FMC_IT_LEVEL: Interrupt level. 941 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 942 * @retval None 943 */ 944 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->IER |= (__INTERRUPT__)) 945 946 /** 947 * @brief Disable the NAND device interrupt. 948 * @param __INSTANCE__ FMC_NAND Instance 949 * @param __INTERRUPT__ FMC_NAND interrupt 950 * This parameter can be any combination of the following values: 951 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 952 * @arg FMC_IT_LEVEL: Interrupt level. 953 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 954 * @retval None 955 */ 956 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->IER &= ~(__INTERRUPT__)) 957 958 /** 959 * @brief Get flag status of the NAND device. 960 * @param __INSTANCE__ FMC_NAND Instance 961 * @param __BANK__ FMC_NAND Bank 962 * @param __FLAG__ FMC_NAND flag 963 * This parameter can be any combination of the following values: 964 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 965 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 966 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 967 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 968 * @retval The state of FLAG (SET or RESET). 969 */ 970 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->ISR &(__FLAG__)) == (__FLAG__)) 971 972 /** 973 * @brief Clear flag status of the NAND device. 974 * @param __INSTANCE__ FMC_NAND Instance 975 * @param __FLAG__ FMC_NAND flag 976 * This parameter can be any combination of the following values: 977 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 978 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 979 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 980 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 981 * @retval None 982 */ 983 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR |= (__FLAG__)) 984 985 /** 986 * @} 987 */ 988 989 990 /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt 991 * @brief macros to handle SDRAM interrupts 992 * @{ 993 */ 994 995 /** 996 * @brief Enable the SDRAM device interrupt. 997 * @param __INSTANCE__ FMC_SDRAM instance 998 * @param __INTERRUPT__ FMC_SDRAM interrupt 999 * This parameter can be any combination of the following values: 1000 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1001 * @retval None 1002 */ 1003 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 1004 1005 /** 1006 * @brief Disable the SDRAM device interrupt. 1007 * @param __INSTANCE__ FMC_SDRAM instance 1008 * @param __INTERRUPT__ FMC_SDRAM interrupt 1009 * This parameter can be any combination of the following values: 1010 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1011 * @retval None 1012 */ 1013 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 1014 1015 /** 1016 * @brief Get flag status of the SDRAM device. 1017 * @param __INSTANCE__ FMC_SDRAM instance 1018 * @param __FLAG__ FMC_SDRAM flag 1019 * This parameter can be any combination of the following values: 1020 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. 1021 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. 1022 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. 1023 * @retval The state of FLAG (SET or RESET). 1024 */ 1025 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 1026 1027 /** 1028 * @brief Clear flag status of the SDRAM device. 1029 * @param __INSTANCE__ FMC_SDRAM instance 1030 * @param __FLAG__ FMC_SDRAM flag 1031 * This parameter can be any combination of the following values: 1032 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR 1033 * @retval None 1034 */ 1035 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 1036 1037 /** 1038 * @} 1039 */ 1040 /** 1041 * @} 1042 */ 1043 1044 /** 1045 * @} 1046 */ 1047 1048 /* Private functions ---------------------------------------------------------*/ 1049 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 1050 * @{ 1051 */ 1052 1053 /** @defgroup FMC_LL_NORSRAM NOR SRAM 1054 * @{ 1055 */ 1056 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 1057 * @{ 1058 */ 1059 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 1060 const FMC_NORSRAM_InitTypeDef *Init); 1061 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 1062 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 1063 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 1064 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 1065 uint32_t ExtendedMode); 1066 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 1067 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 1068 /** 1069 * @} 1070 */ 1071 1072 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1073 * @{ 1074 */ 1075 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1076 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1077 /** 1078 * @} 1079 */ 1080 /** 1081 * @} 1082 */ 1083 1084 /** @defgroup FMC_LL_NAND NAND 1085 * @{ 1086 */ 1087 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1088 * @{ 1089 */ 1090 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); 1091 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1092 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1093 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1094 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1095 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 1096 /** 1097 * @} 1098 */ 1099 1100 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1101 * @{ 1102 */ 1103 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1104 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1105 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 1106 uint32_t Timeout); 1107 /** 1108 * @} 1109 */ 1110 /** 1111 * @} 1112 */ 1113 1114 1115 /** @defgroup FMC_LL_SDRAM SDRAM 1116 * @{ 1117 */ 1118 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 1119 * @{ 1120 */ 1121 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); 1122 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, 1123 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); 1124 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1125 /** 1126 * @} 1127 */ 1128 1129 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 1130 * @{ 1131 */ 1132 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1133 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1134 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, 1135 const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); 1136 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); 1137 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, 1138 uint32_t AutoRefreshNumber); 1139 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1140 /** 1141 * @} 1142 */ 1143 /** 1144 * @} 1145 */ 1146 1147 /** 1148 * @} 1149 */ 1150 1151 /** 1152 * @} 1153 */ 1154 1155 /** 1156 * @} 1157 */ 1158 1159 #ifdef __cplusplus 1160 } 1161 #endif 1162 1163 #endif /* STM32N6xx_LL_FMC_H */ 1164
