1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_nand.h 4 * @author MCD Application Team 5 * @brief Header file of NAND HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_NAND_H 21 #define STM32N6xx_HAL_NAND_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32n6xx_ll_fmc.h" 30 31 /** @addtogroup STM32N6xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup NAND 36 * @{ 37 */ 38 39 /* Exported typedef ----------------------------------------------------------*/ 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup NAND_Exported_Types NAND Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL NAND State structures definition 47 */ 48 typedef enum 49 { 50 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 51 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 52 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 53 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 54 } HAL_NAND_StateTypeDef; 55 56 /** 57 * @brief NAND Memory electronic signature Structure definition 58 */ 59 typedef struct 60 { 61 /*<! NAND memory electronic signature maker and device IDs */ 62 63 uint8_t Maker_Id; 64 65 uint8_t Device_Id; 66 67 uint8_t Third_Id; 68 69 uint8_t Fourth_Id; 70 } NAND_IDTypeDef; 71 72 /** 73 * @brief NAND Memory address Structure definition 74 */ 75 typedef struct 76 { 77 uint16_t Page; /*!< NAND memory Page address */ 78 79 uint16_t Plane; /*!< NAND memory Zone address */ 80 81 uint16_t Block; /*!< NAND memory Block address */ 82 83 } NAND_AddressTypeDef; 84 85 /** 86 * @brief NAND Memory info Structure definition 87 */ 88 typedef struct 89 { 90 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 91 for 8 bits addressing or words for 16 bits addressing */ 92 93 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 94 for 8 bits addressing or words for 16 bits addressing */ 95 96 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 97 98 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 99 100 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 101 102 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 103 104 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 105 parameter is mandatory for some NAND parts after the read 106 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 107 This parameter could be ENABLE or DISABLE 108 Please check the Read Mode sequence in the NAND device datasheet */ 109 } NAND_DeviceConfigTypeDef; 110 111 /** 112 * @brief NAND handle Structure definition 113 */ 114 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 115 typedef struct __NAND_HandleTypeDef 116 #else 117 typedef struct 118 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 119 { 120 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 121 122 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 123 124 HAL_LockTypeDef Lock; /*!< NAND locking object */ 125 126 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 127 128 NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */ 129 130 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 131 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 132 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 133 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 134 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 135 } NAND_HandleTypeDef; 136 137 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 138 /** 139 * @brief HAL NAND Callback ID enumeration definition 140 */ 141 typedef enum 142 { 143 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 144 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 145 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 146 } HAL_NAND_CallbackIDTypeDef; 147 148 /** 149 * @brief HAL NAND Callback pointer definition 150 */ 151 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 152 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 153 154 /** 155 * @} 156 */ 157 158 /* Exported constants --------------------------------------------------------*/ 159 /* Exported macro ------------------------------------------------------------*/ 160 /** @defgroup NAND_Exported_Macros NAND Exported Macros 161 * @{ 162 */ 163 164 /** @brief Reset NAND handle state 165 * @param __HANDLE__ specifies the NAND handle. 166 * @retval None 167 */ 168 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 169 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 170 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 171 (__HANDLE__)->MspInitCallback = NULL; \ 172 (__HANDLE__)->MspDeInitCallback = NULL; \ 173 } while(0) 174 #else 175 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 176 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 177 178 /** 179 * @} 180 */ 181 182 /* Exported functions --------------------------------------------------------*/ 183 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 184 * @{ 185 */ 186 187 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 188 * @{ 189 */ 190 191 /* Initialization/de-initialization functions ********************************/ 192 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 193 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 194 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 195 196 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); 197 198 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 199 200 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 201 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 202 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 203 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 204 205 /** 206 * @} 207 */ 208 209 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 210 * @{ 211 */ 212 213 /* IO operation functions ****************************************************/ 214 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 215 216 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 217 uint8_t *pBuffer, uint32_t NumPageToRead); 218 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 219 const uint8_t *pBuffer, uint32_t NumPageToWrite); 220 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 221 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 222 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 223 const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 224 225 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 226 uint16_t *pBuffer, uint32_t NumPageToRead); 227 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 228 const uint16_t *pBuffer, uint32_t NumPageToWrite); 229 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 230 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 231 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 232 const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 233 234 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); 235 236 uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 237 238 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 239 /* NAND callback registering/unregistering */ 240 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 241 pNAND_CallbackTypeDef pCallback); 242 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 243 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 244 245 /** 246 * @} 247 */ 248 249 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 250 * @{ 251 */ 252 253 /* NAND Control functions ****************************************************/ 254 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 255 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 256 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 257 258 /** 259 * @} 260 */ 261 262 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 263 * @{ 264 */ 265 /* NAND State functions *******************************************************/ 266 HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); 267 uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); 268 /** 269 * @} 270 */ 271 272 /** 273 * @} 274 */ 275 276 /* Private types -------------------------------------------------------------*/ 277 /* Private variables ---------------------------------------------------------*/ 278 /* Private constants ---------------------------------------------------------*/ 279 /** @defgroup NAND_Private_Constants NAND Private Constants 280 * @{ 281 */ 282 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 283 #define NAND_DEVICE 0x37EFF000UL 284 #else 285 #define NAND_DEVICE 0x27EFF000UL 286 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 287 #define NAND_WRITE_TIMEOUT 0x01000000UL 288 289 #define CMD_AREA (1UL<<4U) /* A16 = CLE high */ 290 #define ADDR_AREA (1UL<<5U) /* A17 = ALE high */ 291 292 #define NAND_CMD_AREA_A ((uint8_t)0x00) 293 #define NAND_CMD_AREA_B ((uint8_t)0x01) 294 #define NAND_CMD_AREA_C ((uint8_t)0x50) 295 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 296 297 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 298 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 299 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 300 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 301 #define NAND_CMD_READID ((uint8_t)0x90) 302 #define NAND_CMD_STATUS ((uint8_t)0x70) 303 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 304 #define NAND_CMD_RESET ((uint8_t)0xFF) 305 306 /* NAND memory status */ 307 #define NAND_VALID_ADDRESS 0x00000100UL 308 #define NAND_INVALID_ADDRESS 0x00000200UL 309 #define NAND_TIMEOUT_ERROR 0x00000400UL 310 #define NAND_BUSY 0x00000000UL 311 #define NAND_ERROR 0x00000001UL 312 #define NAND_READY 0x00000040UL 313 /** 314 * @} 315 */ 316 317 /* Private macros ------------------------------------------------------------*/ 318 /** @defgroup NAND_Private_Macros NAND Private Macros 319 * @{ 320 */ 321 322 /** 323 * @brief NAND memory address computation. 324 * @param __ADDRESS__ NAND memory address. 325 * @param __HANDLE__ NAND handle. 326 * @retval NAND Raw address value 327 */ 328 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 329 (((__ADDRESS__)->Block + \ 330 (((__ADDRESS__)->Plane) * \ 331 ((__HANDLE__)->Config.PlaneSize))) * \ 332 ((__HANDLE__)->Config.BlockSize))) 333 334 /** 335 * @brief NAND memory Column address computation. 336 * @param __HANDLE__ NAND handle. 337 * @retval NAND Raw address value 338 */ 339 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 340 341 /** 342 * @brief NAND memory address cycling. 343 * @param __ADDRESS__ NAND memory address. 344 * @retval NAND address cycling value. 345 */ 346 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 347 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 348 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 349 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 350 351 /** 352 * @brief NAND memory Columns cycling. 353 * @param __ADDRESS__ NAND memory address. 354 * @retval NAND Column address cycling value. 355 */ 356 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 357 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 358 359 /** 360 * @} 361 */ 362 363 /** 364 * @} 365 */ 366 367 /** 368 * @} 369 */ 370 371 /** 372 * @} 373 */ 374 375 376 #ifdef __cplusplus 377 } 378 #endif 379 380 #endif /* STM32N6xx_HAL_NAND_H */ 381
