1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_gpu2d.h 4 * @author MCD Application Team 5 * @brief Header file of GPU2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_GPU2D_H 21 #define STM32N6xx_HAL_GPU2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 #if defined (GPU2D) 31 32 /** @addtogroup STM32N6xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup GPU2D GPU2D 37 * @brief GPU2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup GPU2D_Exported_Types GPU2D Exported Types 43 * @{ 44 */ 45 /** 46 * @brief HAL GPU2D State enumeration definition 47 */ 48 typedef enum 49 { 50 HAL_GPU2D_STATE_RESET = 0x00U, /*!< GPU2D not yet initialized or disabled */ 51 HAL_GPU2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 52 HAL_GPU2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 53 HAL_GPU2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 54 HAL_GPU2D_STATE_ERROR = 0x04U 55 } HAL_GPU2D_StateTypeDef; 56 57 /** 58 * @brief GPU2D_TypeDef definition 59 */ 60 typedef uint32_t GPU2D_TypeDef; 61 62 /** 63 * @brief GPU2D handle Structure definition 64 */ 65 #if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) 66 typedef struct __GPU2D_HandleTypeDef 67 #else 68 typedef struct 69 #endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ 70 { 71 GPU2D_TypeDef Instance; /*!< GPU2D register base address. */ 72 73 HAL_LockTypeDef Lock; /*!< GPU2D lock. */ 74 75 __IO HAL_GPU2D_StateTypeDef State; /*!< GPU2D transfer state. */ 76 77 __IO uint32_t ErrorCode; /*!< GPU2D error code. */ 78 79 #if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) 80 void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback */ 81 82 void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp Init callback */ 83 84 void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp DeInit callback */ 85 #endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ 86 } GPU2D_HandleTypeDef; 87 88 #if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) 89 /** 90 * @brief HAL GPU2D Callback ID enumeration definition 91 */ 92 typedef enum 93 { 94 HAL_GPU2D_MSPINIT_CB_ID = 0x00U, /*!< GPU2D MspInit callback ID */ 95 HAL_GPU2D_MSPDEINIT_CB_ID = 0x01U, /*!< GPU2D MspDeInit callback ID */ 96 } HAL_GPU2D_CallbackIDTypeDef; 97 98 /** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition 99 * @brief HAL GPU2D Callback pointer definition 100 * @{ 101 */ 102 typedef void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d); /*!< pointer to an GPU2D Callback function */ 103 typedef void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */ 104 #endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ 105 /** 106 * @} 107 */ 108 109 /* Exported constants --------------------------------------------------------*/ 110 /** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants 111 * @{ 112 */ 113 114 /** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition 115 * @brief GPU2D Error Code definition 116 * @{ 117 */ 118 #define HAL_GPU2D_ERROR_NONE (0x00000000U) /*!< No error */ 119 #define HAL_GPU2D_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 120 #if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) 121 #define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U) /*!< Invalid callback error */ 122 #endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition 128 * @brief GPU2D Interrupt definition 129 * @{ 130 */ 131 #define GPU2D_IT_CLC 0x00000001U /*!< Command List Complete Interrupt */ 132 /** 133 * @} 134 */ 135 136 /** @defgroup GPU2D_Flag_definition GPU2D Flag definition 137 * @brief GPU2D Flags definition 138 * @{ 139 */ 140 #define GPU2D_FLAG_CLC 0x00000001U /*!< Command List Complete Interrupt Flag */ 141 /** 142 * @} 143 */ 144 145 /** 146 * @} 147 */ 148 149 /* Exported macros ------------------------------------------------------------*/ 150 /** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros 151 * @{ 152 */ 153 154 /** @brief Reset GPU2D handle state 155 * @param __HANDLE__: specifies the GPU2D handle. 156 * @retval None 157 */ 158 #if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) 159 #define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do { \ 160 (__HANDLE__)->State = HAL_GPU2D_STATE_RESET; \ 161 (__HANDLE__)->MspInitCallback = NULL; \ 162 (__HANDLE__)->MspDeInitCallback = NULL; \ 163 (__HANDLE__)->CommandListCpltCallback = NULL; \ 164 } while(0) 165 #else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ 166 #define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET) 167 #endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ 168 169 /* Interrupt & Flag management */ 170 /** 171 * @brief Get the GPU2D pending flags. 172 * @param __HANDLE__: GPU2D handle 173 * @param __FLAG__: flag to check. 174 * This parameter can be one of the following values: 175 * @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask 176 * @retval The state of FLAG. 177 */ 178 #define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\ 179 + GPU2D_ITCTRL)) & (__FLAG__)) 180 181 /** 182 * @brief Clear the GPU2D pending flags. 183 * @param __HANDLE__: GPU2D handle 184 * @param __FLAG__: specifies the flag to clear. 185 * This parameter can be one of the following values: 186 * @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask 187 * @retval None 188 */ 189 #define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \ 190 __IO uint32_t *tmpreg = \ 191 (__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\ 192 + GPU2D_ITCTRL); \ 193 CLEAR_BIT(*tmpreg, __FLAG__); \ 194 } while(0U) 195 196 /** 197 * @brief Check whether the specified GPU2D interrupt source is enabled or not. 198 * @param __HANDLE__: GPU2D handle 199 * @param __INTERRUPT__: specifies the GPU2D interrupt source to check. 200 * This parameter can be one of the following values: 201 * @arg GPU2D_IT_CLC: Command List Complete interrupt mask 202 * @retval The state of INTERRUPT source. 203 */ 204 #define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\ 205 ((uint32_t)(__HANDLE__)->Instance\ 206 + GPU2D_ITCTRL)) & (__INTERRUPT__)) 207 208 /** 209 * @} 210 */ 211 212 /* Exported functions --------------------------------------------------------*/ 213 /** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions 214 * @{ 215 */ 216 217 /** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions 218 * @{ 219 */ 220 221 /* Initialization and de-initialization functions *******************************/ 222 HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d); 223 HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d); 224 void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d); 225 void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d); 226 /* Callbacks Register/UnRegister functions ***********************************/ 227 #if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) 228 HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID, 229 pGPU2D_CallbackTypeDef pCallback); 230 HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID); 231 HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, 232 pGPU2D_CommandListCpltCallbackTypeDef pCallback); 233 HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d); 234 #endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ 235 236 /** 237 * @} 238 */ 239 240 241 /** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions 242 * @{ 243 */ 244 245 /* IO operation functions *******************************************************/ 246 uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset); 247 HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value); 248 void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d); 249 void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d); 250 void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); 251 void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d); 252 253 /** 254 * @} 255 */ 256 257 /** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions 258 * @{ 259 */ 260 261 /* Peripheral State functions ***************************************************/ 262 HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d); 263 uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d); 264 265 /** 266 * @} 267 */ 268 269 /* Private constants ---------------------------------------------------------*/ 270 271 /** @addtogroup GPU2D_Private_Constants GPU2D Private Constants 272 * @{ 273 */ 274 275 #define GPU2D_ITCTRL (0x0F8U) /*!< GPU2D Interrupt Control Register Offset */ 276 #define GPU2D_CLID (0x148U) /*!< GPU2D Last Command List Identifier Register Offset */ 277 #define GPU2D_BREAKPOINT (0x080U) /*!< GPU2D Breakpoint Register Offset */ 278 #define GPU2D_SYS_INTERRUPT (0xff8U) /*!< GPU2D System Interrupt Register Offset */ 279 280 /** @defgroup GPU2D_Offset GPU2D Last Register Offset 281 * @{ 282 */ 283 #define GPU2D_OFFSET 0x1000U /*!< Last GPU2D Register Offset */ 284 /** 285 * @} 286 */ 287 288 /** 289 * @} 290 */ 291 292 /* Private macros ------------------------------------------------------------*/ 293 /** @defgroup GPU2D_Private_Macros GPU2D Private Macros 294 * @{ 295 */ 296 #define IS_GPU2D_OFFSET(OFFSET) ((OFFSET) < GPU2D_OFFSET) 297 298 /** 299 * @} 300 */ 301 302 /** 303 * @} 304 */ 305 306 /** 307 * @} 308 */ 309 310 /** 311 * @} 312 */ 313 314 #endif /* defined (GPU2D) */ 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif /* STM32N6xx_HAL_GPU2D_H */ 321 322
