1 /** 2 ********************************************************************************************************************** 3 * @file stm32n6xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32N6xx_HAL_DMA_H 21 #define STM32N6xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 39 /* Exported types ----------------------------------------------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Transfer Configuration Structure definition. 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the DMA channel request. 52 This parameter can be a value of @ref DMA_Request_Selection */ 53 54 uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. 55 Block Hardware request feature can be used only with dedicated peripherals. 56 This parameter can be a value of @ref DMA_Block_Request */ 57 58 uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. 59 This parameter can be a value of @ref DMA_Transfer_Direction */ 60 61 uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. 62 This parameter can be a value of @ref DMA_Source_Increment_Mode */ 63 64 uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. 65 This parameter can be a value of @ref DMA_Destination_Increment_Mode */ 66 67 uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. 68 This parameter can be a value of @ref DMA_Source_Data_Width */ 69 70 uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. 71 This parameter can be a value of @ref DMA_Destination_Data_Width */ 72 73 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 74 This parameter can be a value of @ref DMA_Priority_Level */ 75 76 uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA 77 channel. 78 This parameter can be a value between 1 and 64 */ 79 80 uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the 81 DMA channel. 82 This parameter can be a value between 1 and 64 */ 83 84 uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. 85 This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ 86 87 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 88 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 89 90 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. 91 This parameter can be a value of @ref DMA_Transfer_Mode */ 92 93 } DMA_InitTypeDef; 94 95 /** 96 * @brief DMA Linked-List Configuration Structure Definition. 97 */ 98 typedef struct 99 { 100 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 101 This parameter can be a value of @ref DMA_Priority_Level */ 102 103 uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. 104 This parameter can be a value of @ref DMAEx_Link_Step_Mode */ 105 106 uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. 107 This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ 108 109 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 110 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 111 112 uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. 113 This parameter can be a value of @ref DMAEx_LinkedList_Mode */ 114 115 } DMA_InitLinkedListTypeDef; 116 117 /** 118 * @brief DMA CID filtering (isolation) configuration structure. 119 */ 120 typedef struct 121 { 122 uint32_t CidFiltering; /*!< Specified the CID filtering mode. 123 This parameter can be a value of @ref DMA_ISOLATION_MODE */ 124 uint32_t StaticCid; /*!< Specified the static CID. 125 This parameter can be a value of @ref DMA_Channel_CID_Filtering_Static */ 126 } DMA_IsolationConfigTypeDef; 127 128 /** 129 * @brief HAL DMA State Enumeration Definition. 130 */ 131 typedef enum 132 { 133 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 134 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 135 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 136 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 137 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 138 HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ 139 140 } HAL_DMA_StateTypeDef; 141 142 /** 143 * @brief HAL DMA Level Complete Enumeration Definition. 144 */ 145 typedef enum 146 { 147 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ 148 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ 149 150 } HAL_DMA_LevelCompleteTypeDef; 151 152 /** 153 * @brief HAL DMA Callbacks IDs Enumeration Definition. 154 */ 155 typedef enum 156 { 157 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ 158 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ 159 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ 160 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ 161 HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ 162 HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ 163 164 } HAL_DMA_CallbackIDTypeDef; 165 166 /** 167 * @brief DMA handle Structure definition 168 */ 169 typedef struct __DMA_HandleTypeDef 170 { 171 DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ 172 173 DMA_InitTypeDef Init; /*!< DMA channel init parameters */ 174 175 DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ 176 177 HAL_LockTypeDef Lock; /*!< DMA locking object */ 178 179 uint32_t Mode; /*!< DMA transfer mode */ 180 181 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 182 183 __IO uint32_t ErrorCode; /*!< DMA error code */ 184 185 void *Parent; /*!< Parent object state */ 186 187 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 188 189 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ 190 191 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 192 193 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 194 195 void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ 196 197 struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ 198 199 } DMA_HandleTypeDef; 200 /** 201 * @} 202 */ 203 204 205 /* Exported constants ------------------------------------------------------------------------------------------------*/ 206 /** @defgroup DMA_Exported_Constants DMA Exported Constants 207 * @brief DMA Exported constants 208 * @{ 209 */ 210 211 /** @defgroup DMA_Error_Codes DMA Error Codes 212 * @brief DMA Error Codes 213 * @{ 214 */ 215 #define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ 216 #define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ 217 #define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ 218 #define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ 219 #define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ 220 #define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ 221 #define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ 222 #define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ 223 #define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ 224 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition 230 * @brief DMA Interrupt Enable Definition 231 * @{ 232 */ 233 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ 234 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ 235 #define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ 236 #define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ 237 #define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ 238 #define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ 239 #define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ 240 /** 241 * @} 242 */ 243 244 /** @defgroup DMA_Flag_Definition DMA Flag Definition 245 * @brief DMA Flag Definition 246 * @{ 247 */ 248 #define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ 249 #define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ 250 #define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ 251 #define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ 252 #define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ 253 #define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ 254 #define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ 255 #define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup DMA_Request_Selection DMA Request Selection 261 * @brief DMA Request Selection 262 * @{ 263 */ 264 /* HPDMA1 requests */ 265 #define HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_RX */ 266 #define HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_TX */ 267 #define HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */ 268 #define HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */ 269 #define HPDMA1_REQUEST_XSPI3 4U /*!< HPDMA1 HW request is XSPI3 */ 270 #define HPDMA1_REQUEST_FMC2_TXRX 5U /*!< HPDMA1 HW request is FMC2_TXRX */ 271 #define HPDMA1_REQUEST_FMC2_BCH 6U /*!< HPDMA1 HW request is FMC2_BCH */ 272 #define HPDMA1_REQUEST_ADC1 7U /*!< HPDMA1 HW request is ADC1 */ 273 #define HPDMA1_REQUEST_ADC2 8U /*!< HPDMA1 HW request is ADC2 */ 274 #define HPDMA1_REQUEST_CRYP_IN 9U /*!< HPDMA1 HW request is CRYP_IN */ 275 #define HPDMA1_REQUEST_CRYP_OUT 10U /*!< HPDMA1 HW request is CRYP_OUT */ 276 #define HPDMA1_REQUEST_SAES_OUT 11U /*!< HPDMA1 HW request is SAES_OUT */ 277 #define HPDMA1_REQUEST_SAES_IN 12U /*!< HPDMA1 HW request is SAES_IN */ 278 #define HPDMA1_REQUEST_HASH_IN 13U /*!< HPDMA1 HW request is HASH_IN */ 279 280 #define HPDMA1_REQUEST_TIM1_CH1 14U /*!< HPDMA1 HW request is TIM1_CH1 */ 281 #define HPDMA1_REQUEST_TIM1_CH2 15U /*!< HPDMA1 HW request is TIM1_CH2 */ 282 #define HPDMA1_REQUEST_TIM1_CH3 16U /*!< HPDMA1 HW request is TIM1_CH3 */ 283 #define HPDMA1_REQUEST_TIM1_CH4 17U /*!< HPDMA1 HW request is TIM1_CH4 */ 284 #define HPDMA1_REQUEST_TIM1_UP 18U /*!< HPDMA1 HW request is TIM1_UP */ 285 #define HPDMA1_REQUEST_TIM1_TRIG 19U /*!< HPDMA1 HW request is TIM1_TRIG */ 286 #define HPDMA1_REQUEST_TIM1_COM 20U /*!< HPDMA1 HW request is TIM1_COM */ 287 288 #define HPDMA1_REQUEST_TIM2_CH1 21U /*!< HPDMA1 HW request is TIM2_CH1 */ 289 #define HPDMA1_REQUEST_TIM2_CH2 22U /*!< HPDMA1 HW request is TIM2_CH2 */ 290 #define HPDMA1_REQUEST_TIM2_CH3 23U /*!< HPDMA1 HW request is TIM2_CH3 */ 291 #define HPDMA1_REQUEST_TIM2_CH4 24U /*!< HPDMA1 HW request is TIM2_CH4 */ 292 #define HPDMA1_REQUEST_TIM2_UP 25U /*!< HPDMA1 HW request is TIM2_UP */ 293 #define HPDMA1_REQUEST_TIM2_TRIG 26U /*!< HPDMA1 HW request is TIM2_TRIG */ 294 295 #define HPDMA1_REQUEST_TIM3_CH1 27U /*!< HPDMA1 HW request is TIM3_CH1 */ 296 #define HPDMA1_REQUEST_TIM3_CH2 28U /*!< HPDMA1 HW request is TIM3_CH2 */ 297 #define HPDMA1_REQUEST_TIM3_CH3 29U /*!< HPDMA1 HW request is TIM3_CH3 */ 298 #define HPDMA1_REQUEST_TIM3_CH4 30U /*!< HPDMA1 HW request is TIM3_CH4 */ 299 #define HPDMA1_REQUEST_TIM3_UP 31U /*!< HPDMA1 HW request is TIM3_UP */ 300 #define HPDMA1_REQUEST_TIM3_TRIG 32U /*!< HPDMA1 HW request is TIM3_TRIG */ 301 302 #define HPDMA1_REQUEST_TIM4_CH1 33U /*!< HPDMA1 HW request is TIM4_CH1 */ 303 #define HPDMA1_REQUEST_TIM4_CH2 34U /*!< HPDMA1 HW request is TIM4_CH2 */ 304 #define HPDMA1_REQUEST_TIM4_CH3 35U /*!< HPDMA1 HW request is TIM4_CH3 */ 305 #define HPDMA1_REQUEST_TIM4_CH4 36U /*!< HPDMA1 HW request is TIM4_CH4 */ 306 #define HPDMA1_REQUEST_TIM4_UP 37U /*!< HPDMA1 HW request is TIM4_UP */ 307 #define HPDMA1_REQUEST_TIM4_TRIG 38U /*!< HPDMA1 HW request is TIM4_TRIG */ 308 309 #define HPDMA1_REQUEST_TIM5_CH1 39U /*!< HPDMA1 HW request is TIM5_CH1 */ 310 #define HPDMA1_REQUEST_TIM5_CH2 40U /*!< HPDMA1 HW request is TIM5_CH2 */ 311 #define HPDMA1_REQUEST_TIM5_CH3 41U /*!< HPDMA1 HW request is TIM5_CH3 */ 312 #define HPDMA1_REQUEST_TIM5_CH4 42U /*!< HPDMA1 HW request is TIM5_CH4 */ 313 #define HPDMA1_REQUEST_TIM5_UP 43U /*!< HPDMA1 HW request is TIM5_UP */ 314 #define HPDMA1_REQUEST_TIM5_TRIG 44U /*!< HPDMA1 HW request is TIM5_TRIG */ 315 316 #define HPDMA1_REQUEST_TIM6_UP 45U /*!< HPDMA1 HW request is TIM6_UP */ 317 #define HPDMA1_REQUEST_TIM7_UP 46U /*!< HPDMA1 HW request is TIM7_UP */ 318 319 #define HPDMA1_REQUEST_TIM8_CH1 47U /*!< HPDMA1 HW request is TIM8_CH1 */ 320 #define HPDMA1_REQUEST_TIM8_CH2 48U /*!< HPDMA1 HW request is TIM8_CH2 */ 321 #define HPDMA1_REQUEST_TIM8_CH3 49U /*!< HPDMA1 HW request is TIM8_CH3 */ 322 #define HPDMA1_REQUEST_TIM8_CH4 50U /*!< HPDMA1 HW request is TIM8_CH4 */ 323 #define HPDMA1_REQUEST_TIM8_UP 51U /*!< HPDMA1 HW request is TIM8_UP */ 324 #define HPDMA1_REQUEST_TIM8_TRIG 52U /*!< HPDMA1 HW request is TIM8_TRIG */ 325 #define HPDMA1_REQUEST_TIM8_COM 53U /*!< HPDMA1 HW request is TIM8_COM */ 326 327 /* reserved 54U */ 328 /* reserved 55U */ 329 330 #define HPDMA1_REQUEST_TIM15_CH1 56U /*!< HPDMA1 HW request is TIM15_CH1 */ 331 #define HPDMA1_REQUEST_TIM15_CH2 57U /*!< HPDMA1 HW request is TIM15_CH2 */ 332 #define HPDMA1_REQUEST_TIM15_UP 58U /*!< HPDMA1 HW request is TIM15_UP */ 333 #define HPDMA1_REQUEST_TIM15_TRIG 59U /*!< HPDMA1 HW request is TIM15_TRIG */ 334 #define HPDMA1_REQUEST_TIM15_COM 60U /*!< HPDMA1 HW request is TIM15_COM */ 335 336 #define HPDMA1_REQUEST_TIM16_CH1 61U /*!< HPDMA1 HW request is TIM16_CH1 */ 337 #define HPDMA1_REQUEST_TIM16_UP 62U /*!< HPDMA1 HW request is TIM16_UP */ 338 #define HPDMA1_REQUEST_TIM16_COM 63U /*!< HPDMA1 HW request is TIM16_COM */ 339 340 #define HPDMA1_REQUEST_TIM17_CH1 64U /*!< HPDMA1 HW request is TIM17_CH1 */ 341 #define HPDMA1_REQUEST_TIM17_UP 65U /*!< HPDMA1 HW request is TIM17_UP */ 342 #define HPDMA1_REQUEST_TIM17_COM 66U /*!< HPDMA1 HW request is TIM17_COM */ 343 344 #define HPDMA1_REQUEST_TIM18_CH1 67U /*!< HPDMA1 HW request is TIM18_CH1 */ 345 #define HPDMA1_REQUEST_TIM18_UP 68U /*!< HPDMA1 HW request is TIM18_UP */ 346 #define HPDMA1_REQUEST_TIM18_COM 69U /*!< HPDMA1 HW request is TIM18_COM */ 347 348 #define HPDMA1_REQUEST_LPTIM1_IC1 70U /*!< HPDMA1 HW request is LPTIM1_IC1 */ 349 #define HPDMA1_REQUEST_LPTIM1_IC2 71U /*!< HPDMA1 HW request is LPTIM1_IC2 */ 350 #define HPDMA1_REQUEST_LPTIM1_UE 72U /*!< HPDMA1 HW request is LPTIM1_UE */ 351 #define HPDMA1_REQUEST_LPTIM2_IC1 73U /*!< HPDMA1 HW request is LPTIM2_IC1 */ 352 #define HPDMA1_REQUEST_LPTIM2_IC2 74U /*!< HPDMA1 HW request is LPTIM2_IC2 */ 353 #define HPDMA1_REQUEST_LPTIM2_UE 75U /*!< HPDMA1 HW request is LPTIM2_UE */ 354 #define HPDMA1_REQUEST_LPTIM3_IC1 76U /*!< HPDMA1 HW request is LPTIM3_IC1 */ 355 #define HPDMA1_REQUEST_LPTIM3_IC2 77U /*!< HPDMA1 HW request is LPTIM3_IC2 */ 356 #define HPDMA1_REQUEST_LPTIM3_UE 78U /*!< HPDMA1 HW request is LPTIM3_UE */ 357 358 #define HPDMA1_REQUEST_SPI1_RX 79U /*!< HPDMA1 HW request is SPI1_RX */ 359 #define HPDMA1_REQUEST_SPI1_TX 80U /*!< HPDMA1 HW request is SPI1_TX */ 360 #define HPDMA1_REQUEST_SPI2_RX 81U /*!< HPDMA1 HW request is SPI2_RX */ 361 #define HPDMA1_REQUEST_SPI2_TX 82U /*!< HPDMA1 HW request is SPI2_TX */ 362 #define HPDMA1_REQUEST_SPI3_RX 83U /*!< HPDMA1 HW request is SPI3_RX */ 363 #define HPDMA1_REQUEST_SPI3_TX 84U /*!< HPDMA1 HW request is SPI3_TX */ 364 #define HPDMA1_REQUEST_SPI4_RX 85U /*!< HPDMA1 HW request is SPI4_RX */ 365 #define HPDMA1_REQUEST_SPI4_TX 86U /*!< HPDMA1 HW request is SPI4_TX */ 366 #define HPDMA1_REQUEST_SPI5_RX 87U /*!< HPDMA1 HW request is SPI5_RX */ 367 #define HPDMA1_REQUEST_SPI5_TX 88U /*!< HPDMA1 HW request is SPI5_TX */ 368 #define HPDMA1_REQUEST_SPI6_RX 89U /*!< HPDMA1 HW request is SPI6_RX */ 369 #define HPDMA1_REQUEST_SPI6_TX 90U /*!< HPDMA1 HW request is SPI6_TX */ 370 371 #define HPDMA1_REQUEST_SAI1_A 91U /*!< HPDMA1 HW request is SAI1_A */ 372 #define HPDMA1_REQUEST_SAI1_B 92U /*!< HPDMA1 HW request is SAI1_B */ 373 #define HPDMA1_REQUEST_SAI2_A 93U /*!< HPDMA1 HW request is SAI2_A */ 374 #define HPDMA1_REQUEST_SAI2_B 94U /*!< HPDMA1 HW request is SAI2_B */ 375 376 #define HPDMA1_REQUEST_I2C1_RX 95U /*!< HPDMA1 HW request is I2C1_RX */ 377 #define HPDMA1_REQUEST_I2C1_TX 96U /*!< HPDMA1 HW request is I2C1_TX */ 378 #define HPDMA1_REQUEST_I2C2_RX 97U /*!< HPDMA1 HW request is I2C2_RX */ 379 #define HPDMA1_REQUEST_I2C2_TX 98U /*!< HPDMA1 HW request is I2C2_TX */ 380 #define HPDMA1_REQUEST_I2C3_RX 99U /*!< HPDMA1 HW request is I2C3_RX */ 381 #define HPDMA1_REQUEST_I2C3_TX 100U /*!< HPDMA1 HW request is I2C3_TX */ 382 383 #define HPDMA1_REQUEST_I2C4_RX 101U /*!< HPDMA1 HW request is I2C4_RX */ 384 #define HPDMA1_REQUEST_I2C4_TX 102U /*!< HPDMA1 HW request is I2C4_TX */ 385 386 #define HPDMA1_REQUEST_I3C1_RX 103U /*!< HPDMA1 HW request is I3C1_RX */ 387 #define HPDMA1_REQUEST_I3C1_TX 104U /*!< HPDMA1 HW request is I3C1_TX */ 388 #define HPDMA1_REQUEST_I3C2_RX 105U /*!< HPDMA1 HW request is I3C2_RX */ 389 #define HPDMA1_REQUEST_I3C2_TX 106U /*!< HPDMA1 HW request is I3C2_TX */ 390 391 #define HPDMA1_REQUEST_USART1_RX 107U /*!< HPDMA1 HW request is USART1_RX */ 392 #define HPDMA1_REQUEST_USART1_TX 108U /*!< HPDMA1 HW request is USART1_TX */ 393 #define HPDMA1_REQUEST_USART2_RX 109U /*!< HPDMA1 HW request is USART2_RX */ 394 #define HPDMA1_REQUEST_USART2_TX 110U /*!< HPDMA1 HW request is USART2_TX */ 395 #define HPDMA1_REQUEST_USART3_RX 111U /*!< HPDMA1 HW request is USART3_RX */ 396 #define HPDMA1_REQUEST_USART3_TX 112U /*!< HPDMA1 HW request is USART3_TX */ 397 #define HPDMA1_REQUEST_UART4_RX 113U /*!< HPDMA1 HW request is UART4_RX */ 398 #define HPDMA1_REQUEST_UART4_TX 114U /*!< HPDMA1 HW request is UART4_TX */ 399 #define HPDMA1_REQUEST_UART5_RX 115U /*!< HPDMA1 HW request is UART5_RX */ 400 #define HPDMA1_REQUEST_UART5_TX 116U /*!< HPDMA1 HW request is UART5_TX */ 401 #define HPDMA1_REQUEST_USART6_RX 117U /*!< HPDMA1 HW request is USART6_RX */ 402 #define HPDMA1_REQUEST_USART6_TX 118U /*!< HPDMA1 HW request is USART6_TX */ 403 #define HPDMA1_REQUEST_UART7_RX 119U /*!< HPDMA1 HW request is UART7_RX */ 404 #define HPDMA1_REQUEST_UART7_TX 120U /*!< HPDMA1 HW request is UART7_TX */ 405 #define HPDMA1_REQUEST_UART8_RX 121U /*!< HPDMA1 HW request is UART8_RX */ 406 #define HPDMA1_REQUEST_UART8_TX 122U /*!< HPDMA1 HW request is UART8_TX */ 407 #define HPDMA1_REQUEST_UART9_RX 123U /*!< HPDMA1 HW request is UART9_RX */ 408 #define HPDMA1_REQUEST_UART9_TX 124U /*!< HPDMA1 HW request is UART9_TX */ 409 #define HPDMA1_REQUEST_USART10_RX 125U /*!< HPDMA1 HW request is USART10_RX */ 410 #define HPDMA1_REQUEST_USART10_TX 126U /*!< HPDMA1 HW request is USART10_TX */ 411 412 #define HPDMA1_REQUEST_LPUART1_RX 127U /*!< HPDMA1 HW request is LPUART1_RX */ 413 #define HPDMA1_REQUEST_LPUART1_TX 128U /*!< HPDMA1 HW request is LPUART1_TX */ 414 415 #define HPDMA1_REQUEST_SPDIFRX_CS 129U /*!< HPDMA1 HW request is SPDIFRX_CS */ 416 #define HPDMA1_REQUEST_SPDIFRX_DT 130U /*!< HPDMA1 HW request is SPDIFRX_DT */ 417 418 #define HPDMA1_REQUEST_ADF1_FLT0 131U /*!< HPDMA1 HW request is ADF1_FLT0 */ 419 420 #define HPDMA1_REQUEST_MDF1_FLT0 132U /*!< HPDMA1 HW request is MDF1_FLT0 */ 421 #define HPDMA1_REQUEST_MDF1_FLT1 133U /*!< HPDMA1 HW request is MDF1_FLT1 */ 422 #define HPDMA1_REQUEST_MDF1_FLT2 134U /*!< HPDMA1 HW request is MDF1_FLT2 */ 423 #define HPDMA1_REQUEST_MDF1_FLT3 135U /*!< HPDMA1 HW request is MDF1_FLT3 */ 424 #define HPDMA1_REQUEST_MDF1_FLT4 136U /*!< HPDMA1 HW request is MDF1_FLT4 */ 425 #define HPDMA1_REQUEST_MDF1_FLT5 137U /*!< HPDMA1 HW request is MDF1_FLT5 */ 426 427 #define HPDMA1_REQUEST_UCPD1_TX 138U /*!< HPDMA1 HW request is UCPD1_TX */ 428 #define HPDMA1_REQUEST_UCPD1_RX 139U /*!< HPDMA1 HW request is UCPD1_RX */ 429 430 #define HPDMA1_REQUEST_DCMI_PSSI 140U /*!< HPDMA1 HW request is DCMI_PSSI */ 431 432 #define HPDMA1_REQUEST_I3C1_TC 141U /*!< HPDMA1 HW request is I3C1_TC */ 433 #define HPDMA1_REQUEST_I3C1_RS 142U /*!< HPDMA1 HW request is I3C1_RS */ 434 435 #define HPDMA1_REQUEST_I3C2_TC 143U /*!< HPDMA1 HW request is I3C2_TC */ 436 #define HPDMA1_REQUEST_I3C2_RS 144U /*!< HPDMA1 HW request is I3C2_RS */ 437 438 /* GPDMA1 requests */ 439 #define GPDMA1_REQUEST_JPEG_RX 0U /*!< GPDMA1 HW request is JPEG_DMA_RX */ 440 #define GPDMA1_REQUEST_JPEG_TX 1U /*!< GPDMA1 HW request is JPEG_DMA_TX */ 441 #define GPDMA1_REQUEST_XSPI1 2U /*!< GPDMA1 HW request is XSPI1 */ 442 #define GPDMA1_REQUEST_XSPI2 3U /*!< GPDMA1 HW request is XSPI2 */ 443 #define GPDMA1_REQUEST_XSPI3 4U /*!< GPDMA1 HW request is XSPI3 */ 444 #define GPDMA1_REQUEST_FMC2_TXRX 5U /*!< GPDMA1 HW request is FMC2_TXRX */ 445 #define GPDMA1_REQUEST_FMC2_BCH 6U /*!< GPDMA1 HW request is FMC2_BCH */ 446 #define GPDMA1_REQUEST_ADC1 7U /*!< GPDMA1 HW request is ADC1 */ 447 #define GPDMA1_REQUEST_ADC2 8U /*!< GPDMA1 HW request is ADC2 */ 448 #define GPDMA1_REQUEST_CRYP_IN 9U /*!< GPDMA1 HW request is CRYP_IN */ 449 #define GPDMA1_REQUEST_CRYP_OUT 10U /*!< GPDMA1 HW request is CRYP_OUT */ 450 #define GPDMA1_REQUEST_SAES_OUT 11U /*!< GPDMA1 HW request is SAES_OUT */ 451 #define GPDMA1_REQUEST_SAES_IN 12U /*!< GPDMA1 HW request is SAES_IN */ 452 #define GPDMA1_REQUEST_HASH_IN 13U /*!< GPDMA1 HW request is HASH_IN */ 453 454 #define GPDMA1_REQUEST_TIM1_CH1 14U /*!< GPDMA1 HW request is TIM1_CH1 */ 455 #define GPDMA1_REQUEST_TIM1_CH2 15U /*!< GPDMA1 HW request is TIM1_CH2 */ 456 #define GPDMA1_REQUEST_TIM1_CH3 16U /*!< GPDMA1 HW request is TIM1_CH3 */ 457 #define GPDMA1_REQUEST_TIM1_CH4 17U /*!< GPDMA1 HW request is TIM1_CH4 */ 458 #define GPDMA1_REQUEST_TIM1_UP 18U /*!< GPDMA1 HW request is TIM1_UP */ 459 #define GPDMA1_REQUEST_TIM1_TRIG 19U /*!< GPDMA1 HW request is TIM1_TRIG */ 460 #define GPDMA1_REQUEST_TIM1_COM 20U /*!< GPDMA1 HW request is TIM1_COM */ 461 462 #define GPDMA1_REQUEST_TIM2_CH1 21U /*!< GPDMA1 HW request is TIM2_CH1 */ 463 #define GPDMA1_REQUEST_TIM2_CH2 22U /*!< GPDMA1 HW request is TIM2_CH2 */ 464 #define GPDMA1_REQUEST_TIM2_CH3 23U /*!< GPDMA1 HW request is TIM2_CH3 */ 465 #define GPDMA1_REQUEST_TIM2_CH4 24U /*!< GPDMA1 HW request is TIM2_CH4 */ 466 #define GPDMA1_REQUEST_TIM2_UP 25U /*!< GPDMA1 HW request is TIM2_UP */ 467 #define GPDMA1_REQUEST_TIM2_TRIG 26U /*!< GPDMA1 HW request is TIM2_TRIG */ 468 469 #define GPDMA1_REQUEST_TIM3_CH1 27U /*!< GPDMA1 HW request is TIM3_CH1 */ 470 #define GPDMA1_REQUEST_TIM3_CH2 28U /*!< GPDMA1 HW request is TIM3_CH2 */ 471 #define GPDMA1_REQUEST_TIM3_CH3 29U /*!< GPDMA1 HW request is TIM3_CH3 */ 472 #define GPDMA1_REQUEST_TIM3_CH4 30U /*!< GPDMA1 HW request is TIM3_CH4 */ 473 #define GPDMA1_REQUEST_TIM3_UP 31U /*!< GPDMA1 HW request is TIM3_UP */ 474 #define GPDMA1_REQUEST_TIM3_TRIG 32U /*!< GPDMA1 HW request is TIM3_TRIG */ 475 476 #define GPDMA1_REQUEST_TIM4_CH1 33U /*!< GPDMA1 HW request is TIM4_CH1 */ 477 #define GPDMA1_REQUEST_TIM4_CH2 34U /*!< GPDMA1 HW request is TIM4_CH2 */ 478 #define GPDMA1_REQUEST_TIM4_CH3 35U /*!< GPDMA1 HW request is TIM4_CH3 */ 479 #define GPDMA1_REQUEST_TIM4_CH4 36U /*!< GPDMA1 HW request is TIM4_CH4 */ 480 #define GPDMA1_REQUEST_TIM4_UP 37U /*!< GPDMA1 HW request is TIM4_UP */ 481 #define GPDMA1_REQUEST_TIM4_TRIG 38U /*!< GPDMA1 HW request is TIM4_TRIG */ 482 483 #define GPDMA1_REQUEST_TIM5_CH1 39U /*!< GPDMA1 HW request is TIM5_CH1 */ 484 #define GPDMA1_REQUEST_TIM5_CH2 40U /*!< GPDMA1 HW request is TIM5_CH2 */ 485 #define GPDMA1_REQUEST_TIM5_CH3 41U /*!< GPDMA1 HW request is TIM5_CH3 */ 486 #define GPDMA1_REQUEST_TIM5_CH4 42U /*!< GPDMA1 HW request is TIM5_CH4 */ 487 #define GPDMA1_REQUEST_TIM5_UP 43U /*!< GPDMA1 HW request is TIM5_UP */ 488 #define GPDMA1_REQUEST_TIM5_TRIG 44U /*!< GPDMA1 HW request is TIM5_TRIG */ 489 490 #define GPDMA1_REQUEST_TIM6_UP 45U /*!< GPDMA1 HW request is TIM6_UP */ 491 #define GPDMA1_REQUEST_TIM7_UP 46U /*!< GPDMA1 HW request is TIM6_UP */ 492 493 #define GPDMA1_REQUEST_TIM8_CH1 47U /*!< GPDMA1 HW request is TIM8_CH1 */ 494 #define GPDMA1_REQUEST_TIM8_CH2 48U /*!< GPDMA1 HW request is TIM8_CH2 */ 495 #define GPDMA1_REQUEST_TIM8_CH3 49U /*!< GPDMA1 HW request is TIM8_CH3 */ 496 #define GPDMA1_REQUEST_TIM8_CH4 50U /*!< GPDMA1 HW request is TIM8_CH4 */ 497 #define GPDMA1_REQUEST_TIM8_UP 51U /*!< GPDMA1 HW request is TIM8_UP */ 498 #define GPDMA1_REQUEST_TIM8_TRIG 52U /*!< GPDMA1 HW request is TIM8_TRIG */ 499 #define GPDMA1_REQUEST_TIM8_COM 53U /*!< GPDMA1 HW request is TIM8_COM */ 500 501 /* reserved 54U */ 502 /* reserved 55U */ 503 504 #define GPDMA1_REQUEST_TIM15_CH1 56U /*!< GPDMA1 HW request is TIM15_CH1 */ 505 #define GPDMA1_REQUEST_TIM15_CH2 57U /*!< GPDMA1 HW request is TIM15_CH2 */ 506 #define GPDMA1_REQUEST_TIM15_UP 58U /*!< GPDMA1 HW request is TIM15_UP */ 507 #define GPDMA1_REQUEST_TIM15_TRIG 59U /*!< GPDMA1 HW request is TIM15_TRIG */ 508 #define GPDMA1_REQUEST_TIM15_COM 60U /*!< GPDMA1 HW request is TIM15_COM */ 509 510 #define GPDMA1_REQUEST_TIM16_CH1 61U /*!< GPDMA1 HW request is TIM16_CH1 */ 511 #define GPDMA1_REQUEST_TIM16_UP 62U /*!< GPDMA1 HW request is TIM16_UP */ 512 #define GPDMA1_REQUEST_TIM16_COM 63U /*!< GPDMA1 HW request is TIM16_COM */ 513 514 #define GPDMA1_REQUEST_TIM17_CH1 64U /*!< GPDMA1 HW request is TIM17_CH1 */ 515 #define GPDMA1_REQUEST_TIM17_UP 65U /*!< GPDMA1 HW request is TIM17_UP */ 516 #define GPDMA1_REQUEST_TIM17_COM 66U /*!< GPDMA1 HW request is TIM17_COM */ 517 518 #define GPDMA1_REQUEST_TIM18_CH1 67U /*!< GPDMA1 HW request is TIM18_CH1 */ 519 #define GPDMA1_REQUEST_TIM18_UP 68U /*!< GPDMA1 HW request is TIM18_UP */ 520 #define GPDMA1_REQUEST_TIM18_COM 69U /*!< GPDMA1 HW request is TIM18_COM */ 521 522 #define GPDMA1_REQUEST_LPTIM1_IC1 70U /*!< GPDMA1 HW request is LPTIM1_IC1 */ 523 #define GPDMA1_REQUEST_LPTIM1_IC2 71U /*!< GPDMA1 HW request is LPTIM1_IC2 */ 524 #define GPDMA1_REQUEST_LPTIM1_UE 72U /*!< GPDMA1 HW request is LPTIM1_UE */ 525 #define GPDMA1_REQUEST_LPTIM2_IC1 73U /*!< GPDMA1 HW request is LPTIM2_IC1 */ 526 #define GPDMA1_REQUEST_LPTIM2_IC2 74U /*!< GPDMA1 HW request is LPTIM2_IC2 */ 527 #define GPDMA1_REQUEST_LPTIM2_UE 75U /*!< GPDMA1 HW request is LPTIM2_UE */ 528 #define GPDMA1_REQUEST_LPTIM3_IC1 76U /*!< GPDMA1 HW request is LPTIM3_IC1 */ 529 #define GPDMA1_REQUEST_LPTIM3_IC2 77U /*!< GPDMA1 HW request is LPTIM3_IC2 */ 530 #define GPDMA1_REQUEST_LPTIM3_UE 78U /*!< GPDMA1 HW request is LPTIM3_UE */ 531 532 #define GPDMA1_REQUEST_SPI1_RX 79U /*!< GPDMA1 HW request is SPI1_RX */ 533 #define GPDMA1_REQUEST_SPI1_TX 80U /*!< GPDMA1 HW request is SPI1_TX */ 534 #define GPDMA1_REQUEST_SPI2_RX 81U /*!< GPDMA1 HW request is SPI2_RX */ 535 #define GPDMA1_REQUEST_SPI2_TX 82U /*!< GPDMA1 HW request is SPI2_TX */ 536 #define GPDMA1_REQUEST_SPI3_RX 83U /*!< GPDMA1 HW request is SPI3_RX */ 537 #define GPDMA1_REQUEST_SPI3_TX 84U /*!< GPDMA1 HW request is SPI3_TX */ 538 #define GPDMA1_REQUEST_SPI4_RX 85U /*!< GPDMA1 HW request is SPI4_RX */ 539 #define GPDMA1_REQUEST_SPI4_TX 86U /*!< GPDMA1 HW request is SPI4_TX */ 540 #define GPDMA1_REQUEST_SPI5_RX 87U /*!< GPDMA1 HW request is SPI5_RX */ 541 #define GPDMA1_REQUEST_SPI5_TX 88U /*!< GPDMA1 HW request is SPI5_TX */ 542 #define GPDMA1_REQUEST_SPI6_RX 89U /*!< GPDMA1 HW request is SPI6_RX */ 543 #define GPDMA1_REQUEST_SPI6_TX 90U /*!< GPDMA1 HW request is SPI6_TX */ 544 545 #define GPDMA1_REQUEST_SAI1_A 91U /*!< GPDMA1 HW request is SAI1_A */ 546 #define GPDMA1_REQUEST_SAI1_B 92U /*!< GPDMA1 HW request is SAI1_B */ 547 #define GPDMA1_REQUEST_SAI2_A 93U /*!< GPDMA1 HW request is SAI2_A */ 548 #define GPDMA1_REQUEST_SAI2_B 94U /*!< GPDMA1 HW request is SAI2_B */ 549 550 #define GPDMA1_REQUEST_I2C1_RX 95U /*!< GPDMA1 HW request is I2C1_RX */ 551 #define GPDMA1_REQUEST_I2C1_TX 96U /*!< GPDMA1 HW request is I2C1_TX */ 552 #define GPDMA1_REQUEST_I2C2_RX 97U /*!< GPDMA1 HW request is I2C2_RX */ 553 #define GPDMA1_REQUEST_I2C2_TX 98U /*!< GPDMA1 HW request is I2C2_TX */ 554 #define GPDMA1_REQUEST_I2C3_RX 99U /*!< GPDMA1 HW request is I2C3_RX */ 555 #define GPDMA1_REQUEST_I2C3_TX 100U /*!< GPDMA1 HW request is I2C3_TX */ 556 557 #define GPDMA1_REQUEST_I2C4_RX 101U /*!< GPDMA1 HW request is I2C4_RX */ 558 #define GPDMA1_REQUEST_I2C4_TX 102U /*!< GPDMA1 HW request is I2C4_TX */ 559 560 #define GPDMA1_REQUEST_I3C1_RX 103U /*!< GPDMA1 HW request is I3C1_RX */ 561 #define GPDMA1_REQUEST_I3C1_TX 104U /*!< GPDMA1 HW request is I3C1_TX */ 562 #define GPDMA1_REQUEST_I3C2_RX 105U /*!< GPDMA1 HW request is I3C2_RX */ 563 #define GPDMA1_REQUEST_I3C2_TX 106U /*!< GPDMA1 HW request is I3C2_TX */ 564 565 #define GPDMA1_REQUEST_USART1_RX 107U /*!< GPDMA1 HW request is USART1_RX */ 566 #define GPDMA1_REQUEST_USART1_TX 108U /*!< GPDMA1 HW request is USART1_TX */ 567 #define GPDMA1_REQUEST_USART2_RX 109U /*!< GPDMA1 HW request is USART2_RX */ 568 #define GPDMA1_REQUEST_USART2_TX 110U /*!< GPDMA1 HW request is USART2_TX */ 569 #define GPDMA1_REQUEST_USART3_RX 111U /*!< GPDMA1 HW request is USART3_RX */ 570 #define GPDMA1_REQUEST_USART3_TX 112U /*!< GPDMA1 HW request is USART3_TX */ 571 #define GPDMA1_REQUEST_UART4_RX 113U /*!< GPDMA1 HW request is UART4_RX */ 572 #define GPDMA1_REQUEST_UART4_TX 114U /*!< GPDMA1 HW request is UART4_TX */ 573 #define GPDMA1_REQUEST_UART5_RX 115U /*!< GPDMA1 HW request is UART5_RX */ 574 #define GPDMA1_REQUEST_UART5_TX 116U /*!< GPDMA1 HW request is UART5_TX */ 575 #define GPDMA1_REQUEST_USART6_RX 117U /*!< GPDMA1 HW request is USART6_RX */ 576 #define GPDMA1_REQUEST_USART6_TX 118U /*!< GPDMA1 HW request is USART6_TX */ 577 #define GPDMA1_REQUEST_UART7_RX 119U /*!< GPDMA1 HW request is UART7_RX */ 578 #define GPDMA1_REQUEST_UART7_TX 120U /*!< GPDMA1 HW request is UART7_TX */ 579 #define GPDMA1_REQUEST_UART8_RX 121U /*!< GPDMA1 HW request is UART8_RX */ 580 #define GPDMA1_REQUEST_UART8_TX 122U /*!< GPDMA1 HW request is UART8_TX */ 581 #define GPDMA1_REQUEST_UART9_RX 123U /*!< GPDMA1 HW request is UART9_RX */ 582 #define GPDMA1_REQUEST_UART9_TX 124U /*!< GPDMA1 HW request is UART9_TX */ 583 #define GPDMA1_REQUEST_USART10_RX 125U /*!< GPDMA1 HW request is USART10_RX */ 584 #define GPDMA1_REQUEST_USART10_TX 126U /*!< GPDMA1 HW request is USART10_TX */ 585 586 #define GPDMA1_REQUEST_LPUART1_RX 127U /*!< GPDMA1 HW request is LPUART1_RX */ 587 #define GPDMA1_REQUEST_LPUART1_TX 128U /*!< GPDMA1 HW request is LPUART1_TX */ 588 589 #define GPDMA1_REQUEST_SPDIFRX_CS 129U /*!< GPDMA1 HW request is SPDIFRX_CS */ 590 #define GPDMA1_REQUEST_SPDIFRX_DT 130U /*!< GPDMA1 HW request is SPDIFRX_DT */ 591 592 #define GPDMA1_REQUEST_ADF1_FLT0 131U /*!< GPDMA1 HW request is ADF1_FLT0 */ 593 594 #define GPDMA1_REQUEST_MDF1_FLT0 132U /*!< GPDMA1 HW request is MDF1_FLT0 */ 595 #define GPDMA1_REQUEST_MDF1_FLT1 133U /*!< GPDMA1 HW request is MDF1_FLT1 */ 596 #define GPDMA1_REQUEST_MDF1_FLT2 134U /*!< GPDMA1 HW request is MDF1_FLT2 */ 597 #define GPDMA1_REQUEST_MDF1_FLT3 135U /*!< GPDMA1 HW request is MDF1_FLT3 */ 598 #define GPDMA1_REQUEST_MDF1_FLT4 136U /*!< GPDMA1 HW request is MDF1_FLT4 */ 599 #define GPDMA1_REQUEST_MDF1_FLT5 137U /*!< GPDMA1 HW request is MDF1_FLT5 */ 600 601 #define GPDMA1_REQUEST_UCPD1_TX 138U /*!< GPDMA1 HW request is UCPD1_TX */ 602 #define GPDMA1_REQUEST_UCPD1_RX 139U /*!< GPDMA1 HW request is UCPD1_RX */ 603 604 #define GPDMA1_REQUEST_DCMI_PSSI 140U /*!< GPDMA1 HW request is DCMI_PSSI */ 605 606 #define GPDMA1_REQUEST_I3C1_TC 141U /*!< GPDMA1 HW request is I3C1_TC */ 607 #define GPDMA1_REQUEST_I3C1_RS 142U /*!< GPDMA1 HW request is I3C1_RS */ 608 609 #define GPDMA1_REQUEST_I3C2_TC 143U /*!< GPDMA1 HW request is I3C2_TC */ 610 #define GPDMA1_REQUEST_I3C2_RS 144U /*!< GPDMA1 HW request is I3C2_RS */ 611 612 /* Software request */ 613 #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ 614 615 616 /** 617 * @} 618 */ 619 620 /** @defgroup DMA_Block_Request DMA Block Request 621 * @brief DMA Block Request 622 * @{ 623 */ 624 #define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ 625 #define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ 626 /** 627 * @} 628 */ 629 630 /** @defgroup DMA_Transfer_Direction DMA Transfer Direction 631 * @brief DMA transfer direction 632 * @{ 633 */ 634 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 635 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ 636 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ 637 /** 638 * @} 639 */ 640 641 /** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode 642 * @brief DMA Source Increment Mode 643 * @{ 644 */ 645 #define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ 646 #define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode 652 * @brief DMA Destination Increment Mode 653 * @{ 654 */ 655 #define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ 656 #define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ 657 /** 658 * @} 659 */ 660 661 /** @defgroup DMA_Source_Data_Width DMA Source Data Width 662 * @brief DMA Source Data Width 663 * @{ 664 */ 665 #define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ 666 #define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ 667 #define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ 668 #define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */ 669 /** 670 * @} 671 */ 672 673 /** @defgroup DMA_Destination_Data_Width DMA destination Data Width 674 * @brief DMA destination Data Width 675 * @{ 676 */ 677 #define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ 678 #define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ 679 #define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ 680 #define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord */ 681 682 /** 683 * @} 684 */ 685 686 /** @defgroup DMA_Priority_Level DMA Priority Level 687 * @brief DMA Priority Level 688 * @{ 689 */ 690 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ 691 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ 692 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ 693 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ 694 /** 695 * @} 696 */ 697 698 /** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port 699 * @brief DMA Transfer Allocated Port 700 * @{ 701 */ 702 #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ 703 #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ 704 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ 705 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ 706 /** 707 * @} 708 */ 709 710 /** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode 711 * @brief DMA Transfer Event Mode 712 * @{ 713 */ 714 #define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the 715 HT event is generated at the half of each block */ 716 #define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block 717 and the HT event is generated at the half of the repeated 718 block */ 719 #define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list 720 item and the HT event is generated at the half of each 721 linked-list item */ 722 #define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last 723 linked-list item and the HT event is generated at the half 724 of the last linked-list item */ 725 /** 726 * @} 727 */ 728 729 /** @defgroup DMA_Transfer_Mode DMA Transfer Mode 730 * @brief DMA Transfer Mode 731 * @{ 732 */ 733 #define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ 734 #define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ 735 /** 736 * @} 737 */ 738 739 /** @defgroup DMA_ISOLATION_MODE DMA Channel isolation mode (CID filtering) 740 * @brief DMA Channel isolation enabling (CID filtering) 741 * @{ 742 */ 743 #define DMA_ISOLATION_OFF 0U /*!< DMA Channel isolation (CID filtering) is disabled */ 744 #define DMA_ISOLATION_ON 1U /*!< DMA Channel isolation (CID filtering) is enabled */ 745 746 /** 747 * @} 748 */ 749 750 /** @defgroup DMA_Channel_CID_Filtering_Static Static DMA Channel Filtering CID (isolation) 751 * @brief DMA Channel Filtering Static CID (isolation) 752 * @{ 753 */ 754 #define DMA_CHANNEL_STATIC_CID_0 (0U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID0 in static mode */ 755 #define DMA_CHANNEL_STATIC_CID_1 (1U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID1 in static mode */ 756 #define DMA_CHANNEL_STATIC_CID_2 (2U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID2 in static mode */ 757 #define DMA_CHANNEL_STATIC_CID_3 (3U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID3 in static mode */ 758 #define DMA_CHANNEL_STATIC_CID_4 (4U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID4 in static mode */ 759 #define DMA_CHANNEL_STATIC_CID_5 (5U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID5 in static mode */ 760 #define DMA_CHANNEL_STATIC_CID_6 (6U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel control to CID6 in static mode */ 761 /** 762 * @} 763 */ 764 765 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 766 * @brief DMA Channel Security and Privilege Attributes 767 * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 768 * @{ 769 */ 770 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ 771 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 772 773 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ 774 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 775 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ 776 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 777 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ 778 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 779 780 #define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ 781 #define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ 782 /** 783 * @} 784 */ 785 786 787 /** 788 * @} 789 */ 790 791 792 /* Exported macro ----------------------------------------------------------------------------------------------------*/ 793 /** @defgroup DMA_Exported_Macros DMA Exported Macros 794 * @brief DMA Exported Macros 795 * @{ 796 */ 797 798 /** @brief Reset DMA handle state. 799 * @param __HANDLE__ : DMA handle. 800 * @retval None. 801 */ 802 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ 803 ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 804 805 /** 806 * @brief Enable the specified DMA Channel. 807 * @param __HANDLE__ : DMA handle. 808 * @retval None 809 */ 810 #define __HAL_DMA_ENABLE(__HANDLE__) \ 811 ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 812 813 /** 814 * @brief Disable the specified DMA Channel. 815 * @param __HANDLE__ : DMA handle. 816 * @retval None 817 */ 818 #define __HAL_DMA_DISABLE(__HANDLE__) \ 819 ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) 820 821 /** 822 * @brief Get the DMA channel pending flags. 823 * @param __HANDLE__ : DMA handle. 824 * @param __FLAG__ : Get the specified flag. 825 * This parameter can be any combination of the following values: 826 * @arg DMA_FLAG_TC : Transfer Complete flag. 827 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 828 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 829 * @arg DMA_FLAG_ULE : Update linked-list Error flag. 830 * @arg DMA_FLAG_USE : User Setting Error flag. 831 * @arg DMA_FLAG_TO : Trigger Overrun flag. 832 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 833 * @arg DMA_FLAG_IDLEF : Idle flag. 834 * @retval The state of FLAG (SET or RESET). 835 */ 836 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ 837 ((__HANDLE__)->Instance->CSR & (__FLAG__)) 838 839 /** 840 * @brief Clear the DMA Channel pending flags. 841 * @param __HANDLE__ : DMA handle. 842 * @param __FLAG__ : Specifies the flag to clear. 843 * This parameter can be any combination of the following values: 844 * @arg DMA_FLAG_TC : Transfer Complete flag. 845 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 846 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 847 * @arg DMA_FLAG_ULE : Update Linked-List Error flag. 848 * @arg DMA_FLAG_USE : User Setting Error flag. 849 * @arg DMA_FLAG_TO : Trigger Overrun flag. 850 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 851 * @retval None 852 */ 853 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 854 ((__HANDLE__)->Instance->CFCR = (__FLAG__)) 855 856 /** 857 * @brief Enable the specified DMA Channel interrupts. 858 * @param __HANDLE__ : DMA handle. 859 * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. 860 * This parameter can be any combination of the following values: 861 * @arg DMA_IT_TC : Transfer Complete interrupt. 862 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 863 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 864 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 865 * @arg DMA_IT_USE : User Setting Error interrupt. 866 * @arg DMA_IT_TO : Trigger Overrun interrupt. 867 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 868 * @retval None 869 */ 870 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 871 ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 872 873 /** 874 * @brief Disable the specified DMA Channel interrupts. 875 * @param __HANDLE__ : DMA handle. 876 * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. 877 * This parameter can be any combination of the following values: 878 * @arg DMA_IT_TC : Transfer Complete interrupt. 879 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 880 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 881 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 882 * @arg DMA_IT_USE : User Setting Error interrupt. 883 * @arg DMA_IT_TO : Trigger Overrun interrupt. 884 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 885 * @retval None 886 */ 887 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 888 ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 889 890 /** 891 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 892 * @param __HANDLE__ : DMA handle. 893 * @param __INTERRUPT__ : specifies the DMA interrupt source to check. 894 * @arg DMA_IT_TC : Transfer Complete interrupt. 895 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 896 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 897 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 898 * @arg DMA_IT_USE : User Setting Error interrupt. 899 * @arg DMA_IT_TO : Trigger Overrun interrupt. 900 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 901 * @retval The state of DMA_IT (SET or RESET). 902 */ 903 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 904 (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 905 906 /** 907 * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. 908 * @param __HANDLE__ : DMA handle. 909 * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). 910 */ 911 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ 912 MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) 913 914 /** 915 * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. 916 * @param __HANDLE__ : DMA handle. 917 * @retval The number of remaining data units in the current DMA Stream transfer. 918 */ 919 #define __HAL_DMA_GET_COUNTER(__HANDLE__) \ 920 (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) 921 /** 922 * @} 923 */ 924 925 926 /* Include DMA HAL Extension module */ 927 #include "stm32n6xx_hal_dma_ex.h" 928 929 930 /* Exported functions ------------------------------------------------------------------------------------------------*/ 931 /** @defgroup DMA_Exported_Functions DMA Exported Functions 932 * @brief DMA Exported Functions 933 * @{ 934 */ 935 936 /** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions 937 * @brief Initialization and De-Initialization Functions 938 * @{ 939 */ 940 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); 941 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); 942 /** 943 * @} 944 */ 945 946 /** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions 947 * @brief I/O Operation Functions 948 * @{ 949 */ 950 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, 951 uint32_t SrcAddress, 952 uint32_t DstAddress, 953 uint32_t SrcDataSize); 954 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, 955 uint32_t SrcAddress, 956 uint32_t DstAddress, 957 uint32_t SrcDataSize); 958 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); 959 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); 960 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, 961 HAL_DMA_LevelCompleteTypeDef CompleteLevel, 962 uint32_t Timeout); 963 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); 964 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, 965 HAL_DMA_CallbackIDTypeDef CallbackID, 966 void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); 967 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, 968 HAL_DMA_CallbackIDTypeDef CallbackID); 969 /** 970 * @} 971 */ 972 973 /** @defgroup DMA_Exported_Functions_Group3 State and Error Functions 974 * @brief State and Error Functions 975 * @{ 976 */ 977 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); 978 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); 979 /** 980 * @} 981 */ 982 983 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions 984 * @brief DMA Attributes Functions 985 * @{ 986 */ 987 988 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, 989 uint32_t ChannelAttributes); 990 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, 991 uint32_t *const pChannelAttributes); 992 993 #if defined (CPU_IN_SECURE_STATE) 994 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); 995 #endif /* CPU_IN_SECURE_STATE */ 996 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, 997 uint32_t *const pLockState); 998 999 1000 #if defined (CPU_IN_SECURE_STATE) 1001 HAL_StatusTypeDef HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef *const hdma, 1002 DMA_IsolationConfigTypeDef const *const pConfig); 1003 #endif /* CPU_IN_SECURE_STATE */ 1004 HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const hdma, 1005 DMA_IsolationConfigTypeDef *const pConfig); 1006 /** 1007 * @} 1008 */ 1009 1010 /** 1011 * @} 1012 */ 1013 1014 1015 /* Private constants -------------------------------------------------------------------------------------------------*/ 1016 /** @defgroup DMA_Private_Constants DMA Private Constants 1017 * @brief DMA Private Constants 1018 * @{ 1019 */ 1020 #define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ 1021 #define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ 1022 #define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ 1023 #define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ 1024 #define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ 1025 #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ 1026 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ 1027 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ 1028 #define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ 1029 #define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ 1030 #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ 1031 #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ 1032 /** 1033 * @} 1034 */ 1035 1036 1037 /* Private macros ----------------------------------------------------------------------------------------------------*/ 1038 /** @defgroup DMA_Private_Macros DMA Private Macros 1039 * @brief DMA Private Macros 1040 * @{ 1041 */ 1042 #define GET_DMA_INSTANCE(__HANDLE__) \ 1043 ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) 1044 1045 #define GET_DMA_CHANNEL(__HANDLE__) \ 1046 ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) 1047 1048 #define IS_DMA_MODE(MODE) \ 1049 (((MODE) == DMA_NORMAL) || \ 1050 ((MODE) == DMA_PFCTRL)) 1051 1052 #define IS_DMA_DIRECTION(DIRECTION) \ 1053 (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ 1054 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 1055 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 1056 1057 #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ 1058 (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ 1059 ((LEVEL) == HAL_DMA_HALF_TRANSFER)) 1060 1061 #define IS_DMA_SOURCE_INC(INC) \ 1062 (((INC) == DMA_SINC_FIXED) || \ 1063 ((INC) == DMA_SINC_INCREMENTED)) 1064 1065 #define IS_DMA_DESTINATION_INC(INC) \ 1066 (((INC) == DMA_DINC_FIXED) || \ 1067 ((INC) == DMA_DINC_INCREMENTED)) 1068 1069 #define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ 1070 (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ 1071 ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ 1072 ((WIDTH) == DMA_SRC_DATAWIDTH_WORD) || \ 1073 ((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD)) 1074 1075 #define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ 1076 (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ 1077 ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ 1078 ((WIDTH) == DMA_DEST_DATAWIDTH_WORD) || \ 1079 ((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD)) 1080 1081 #define IS_DMA_BURST_LENGTH(LENGTH) \ 1082 (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ 1083 ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) 1084 1085 #define IS_DMA_PRIORITY(PRIORITY) \ 1086 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ 1087 ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ 1088 ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ 1089 ((PRIORITY) == DMA_HIGH_PRIORITY)) 1090 1091 #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ 1092 (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) 1093 1094 #define IS_DMA_REQUEST(REQUEST) \ 1095 (((REQUEST) == DMA_REQUEST_SW) || \ 1096 ((REQUEST) <= HPDMA1_REQUEST_I3C2_RS)) 1097 1098 #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ 1099 (((MODE) == DMA_BREQ_SINGLE_BURST) || \ 1100 ((MODE) == DMA_BREQ_BLOCK)) 1101 1102 #define IS_DMA_TCEM_EVENT_MODE(MODE) \ 1103 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 1104 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 1105 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 1106 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 1107 1108 #define IS_DMA_BLOCK_SIZE(SIZE) \ 1109 (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) 1110 1111 #if defined (CPU_IN_SECURE_STATE) 1112 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 1113 (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ 1114 (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ 1115 (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) 1116 #else 1117 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 1118 (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 1119 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 1120 #endif /* CPU_IN_SECURE_STATE */ 1121 1122 #if defined (CPU_IN_SECURE_STATE) 1123 #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ 1124 (((INSTANCE)->SMISR & (GLOBAL_FLAG))) 1125 #endif /* CPU_IN_SECURE_STATE */ 1126 #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ 1127 (((INSTANCE)->MISR & (GLOBAL_FLAG))) 1128 1129 #define IS_DMA_ISOLATION_MODE(MODE) \ 1130 (((MODE) == DMA_ISOLATION_OFF) || \ 1131 ((MODE) == DMA_ISOLATION_ON)) 1132 1133 #define IS_DMA_ISOLATION_STATIC_CID(ID) \ 1134 (((ID) == DMA_CHANNEL_STATIC_CID_0) || \ 1135 ((ID) == DMA_CHANNEL_STATIC_CID_1) || \ 1136 ((ID) == DMA_CHANNEL_STATIC_CID_2) || \ 1137 ((ID) == DMA_CHANNEL_STATIC_CID_3) || \ 1138 ((ID) == DMA_CHANNEL_STATIC_CID_4) || \ 1139 ((ID) == DMA_CHANNEL_STATIC_CID_5) || \ 1140 ((ID) == DMA_CHANNEL_STATIC_CID_6)) 1141 1142 /** 1143 * @} 1144 */ 1145 1146 1147 /* Private functions -------------------------------------------------------------------------------------------------*/ 1148 /** @defgroup DMA_Private_Functions DMA Private Functions 1149 * @brief DMA Private Functions 1150 * @{ 1151 */ 1152 1153 /** 1154 * @} 1155 */ 1156 1157 /** 1158 * @} 1159 */ 1160 1161 /** 1162 * @} 1163 */ 1164 1165 /** 1166 * @} 1167 */ 1168 1169 #ifdef __cplusplus 1170 } 1171 #endif 1172 1173 #endif /* STM32N6xx_HAL_DMA_H */ 1174
